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/kernel/linux/linux-5.10/drivers/pci/controller/dwc/
Dpcie-designware-ep.c1 // SPDX-License-Identifier: GPL-2.0
12 #include "pcie-designware.h"
13 #include <linux/pci-epc.h>
14 #include <linux/pci-epf.h>
16 #include "../../pci.h"
18 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) in dw_pcie_ep_linkup() argument
20 struct pci_epc *epc = ep->epc; in dw_pcie_ep_linkup()
26 void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) in dw_pcie_ep_init_notify() argument
28 struct pci_epc *epc = ep->epc; in dw_pcie_ep_init_notify()
35 dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no) in dw_pcie_ep_get_func_from_ep() argument
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Dpci-exynos.c1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/pci.h>
26 #include "pcie-designware.h"
28 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
65 struct dw_pcie *pci; member
76 struct exynos_pcie *ep);
77 int (*get_clk_resources)(struct exynos_pcie *ep);
78 int (*init_clk_resources)(struct exynos_pcie *ep);
79 void (*deinit_clk_resources)(struct exynos_pcie *ep);
83 struct exynos_pcie *ep) in exynos5440_pcie_get_mem_resources() argument
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Dpci-layerscape-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe controller EP driver for Freescale Layerscape SoCs
15 #include <linux/pci.h>
19 #include "pcie-designware.h"
23 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
32 struct dw_pcie *pci; member
37 static int ls_pcie_establish_link(struct dw_pcie *pci) in ls_pcie_establish_link() argument
47 ls_pcie_ep_get_features(struct dw_pcie_ep *ep) in ls_pcie_ep_get_features() argument
49 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in ls_pcie_ep_get_features() local
50 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci); in ls_pcie_ep_get_features()
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Dpcie-designware-plat.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
16 #include <linux/pci.h>
22 #include "pcie-designware.h"
25 struct dw_pcie *pci; member
38 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in dw_plat_pcie_host_init() local
41 dw_pcie_wait_for_link(pci); in dw_plat_pcie_host_init()
49 pp->num_vectors = MAX_MSI_IRQS; in dw_plat_set_num_vectors()
57 static int dw_plat_pcie_establish_link(struct dw_pcie *pci) in dw_plat_pcie_establish_link() argument
66 static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep) in dw_plat_pcie_ep_init() argument
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Dpcie-designware.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #include <linux/dma-mapping.h>
18 #include <linux/pci.h>
20 #include <linux/pci-epc.h>
21 #include <linux/pci-epf.h>
32 /* Synopsys-specific PCIe configuration registers */
121 * iATU Unroll-specific register definitions
210 void (*ep_init)(struct dw_pcie_ep *ep);
211 int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
213 const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
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Dpcie-uniphier-ep.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/pci.h>
19 #include "pcie-designware.h"
59 struct dw_pcie pci; member
66 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
73 val = readl(priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
78 writel(val, priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
86 val = readl(priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()
91 writel(val, priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()
98 /* set EP mode */ in uniphier_pcie_init_ep()
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Dpcie-artpec6.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Axis ARTPEC-6 SoC
14 #include <linux/pci.h>
23 #include "pcie-designware.h"
25 #define to_artpec6_pcie(x) dev_get_drvdata((x)->dev)
33 struct dw_pcie *pci; member
34 struct regmap *regmap; /* DT axis,syscon-pcie */
47 /* ARTPEC-6 specific registers */
61 /* ARTPEC-7 specific fields */
66 /* ARTPEC-7 specific fields */
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Dpci-dra7xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
21 #include <linux/pci.h>
31 #include "../../pci.h"
32 #include "pcie-designware.h"
88 struct dw_pcie *pci; member
90 int phy_count; /* DT phy-names count */
101 #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
105 return readl(pcie->base + offset); in dra7xx_pcie_readl()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare PCI Core Support"
4 depends on PCI
33 This controller can work either as EP or RC. In order to enable
34 host-specific features PCI_DRA7XX_HOST must be selected and in order
35 to enable device-specific features PCI_DRA7XX_EP must be selected.
48 This controller can work either as EP or RC. In order to enable
49 host-specific features PCI_DRA7XX_HOST must be selected and in order
50 to enable device-specific features PCI_DRA7XX_EP must be selected.
57 bool "Platform bus based DesignWare PCIe Controller - Host mode"
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/kernel/linux/linux-6.6/drivers/pci/controller/dwc/
Dpcie-designware-ep.c1 // SPDX-License-Identifier: GPL-2.0
13 #include "pcie-designware.h"
14 #include <linux/pci-epc.h>
15 #include <linux/pci-epf.h>
17 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) in dw_pcie_ep_linkup() argument
19 struct pci_epc *epc = ep->epc; in dw_pcie_ep_linkup()
25 void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) in dw_pcie_ep_init_notify() argument
27 struct pci_epc *epc = ep->epc; in dw_pcie_ep_init_notify()
34 dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no) in dw_pcie_ep_get_func_from_ep() argument
38 list_for_each_entry(ep_func, &ep->func_list, list) { in dw_pcie_ep_get_func_from_ep()
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Dpci-exynos.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
17 #include <linux/pci.h>
24 #include "pcie-designware.h"
26 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
55 struct dw_pcie pci; member
63 static int exynos_pcie_init_clk_resources(struct exynos_pcie *ep) in exynos_pcie_init_clk_resources() argument
65 struct device *dev = ep->pci.dev; in exynos_pcie_init_clk_resources()
68 ret = clk_prepare_enable(ep->clk); in exynos_pcie_init_clk_resources()
74 ret = clk_prepare_enable(ep->bus_clk); in exynos_pcie_init_clk_resources()
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Dpci-layerscape-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe controller EP driver for Freescale Layerscape SoCs
15 #include <linux/pci.h>
19 #include "pcie-designware.h"
35 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
44 struct dw_pcie *pci; member
54 struct dw_pcie *pci = pcie->pci; in ls_lut_readl() local
56 if (pcie->big_endian) in ls_lut_readl()
57 return ioread32be(pci->dbi_base + offset); in ls_lut_readl()
59 return ioread32(pci->dbi_base + offset); in ls_lut_readl()
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Dpcie-designware.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #include <linux/dma-mapping.h>
22 #include <linux/pci.h>
25 #include <linux/pci-epc.h>
26 #include <linux/pci-epf.h>
28 /* DWC PCIe IP-core versions (native support since v4.70a) */
38 ((_pci)->version _op DW_PCIE_VER_ ## _ver)
58 test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)
61 set_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)
72 /* Synopsys-specific PCIe configuration registers */
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Dpcie-designware-plat.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
16 #include <linux/pci.h>
21 #include "pcie-designware.h"
24 struct dw_pcie *pci; member
35 static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep) in dw_plat_pcie_ep_init() argument
37 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in dw_plat_pcie_ep_init() local
41 dw_pcie_ep_reset_bar(pci, bar); in dw_plat_pcie_ep_init()
44 static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, in dw_plat_pcie_ep_raise_irq() argument
48 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in dw_plat_pcie_ep_raise_irq() local
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Dpcie-uniphier-ep.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/pci.h>
20 #include "pcie-designware.h"
74 struct dw_pcie pci; member
88 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
95 val = readl(priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
100 writel(val, priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
108 val = readl(priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()
113 writel(val, priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()
120 /* set EP mode */ in uniphier_pcie_pro5_init_ep()
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Dpcie-artpec6.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Axis ARTPEC-6 SoC
14 #include <linux/pci.h>
23 #include "pcie-designware.h"
25 #define to_artpec6_pcie(x) dev_get_drvdata((x)->dev)
33 struct dw_pcie *pci; member
34 struct regmap *regmap; /* DT axis,syscon-pcie */
47 /* ARTPEC-6 specific registers */
61 /* ARTPEC-7 specific fields */
66 /* ARTPEC-7 specific fields */
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Dpcie-keembay.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/pci.h>
22 #include "pcie-designware.h"
59 struct dw_pcie pci; member
74 gpiod_set_value_cansleep(pcie->reset, 1); in keembay_ep_reset_assert()
83 * For more details, refer to PCI Express Card Electromechanical in keembay_ep_reset_deassert()
84 * Specification Revision 1.1, Table-2.4. in keembay_ep_reset_deassert()
88 gpiod_set_value_cansleep(pcie->reset, 0); in keembay_ep_reset_deassert()
96 val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
101 writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
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Dpci-dra7xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
22 #include <linux/pci.h>
32 #include "../../pci.h"
33 #include "pcie-designware.h"
89 struct dw_pcie *pci; member
91 int phy_count; /* DT phy-names count */
103 #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
107 return readl(pcie->base + offset); in dra7xx_pcie_readl()
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/kernel/linux/linux-6.6/drivers/acpi/
Dviot.c1 // SPDX-License-Identifier: GPL-2.0
6 * para-virtual IOMMUs and the endpoints they manage. The OS uses it to
16 * hasn't yet been initialized, VIOT returns -EPROBE_DEFER to postpone probing
25 #include <linux/pci.h>
37 /* PCI range */
62 max_t(size_t, sizeof(*viot), viot->node_offset)); in viot_check_bounds()
63 end = ACPI_ADD_PTR(struct acpi_viot_header, viot, viot->header.length); in viot_check_bounds()
68 return -EOVERFLOW; in viot_check_bounds()
70 if (hdr->length < sizeof(*hdr)) { in viot_check_bounds()
72 return -EINVAL; in viot_check_bounds()
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/kernel/linux/linux-6.6/drivers/video/fbdev/
Dsunxvr500.c1 /* sunxvr500.c: Sun 3DLABS XVR-500 Expert3D fb driver for sparc64 systems
11 #include <linux/pci.h>
17 /* XXX This device has a 'dev-comm' property which apparently is
22 * XXX as the values in the 'dev-comm' area are accurate then
56 static int e3d_get_props(struct e3d_info *ep) in e3d_get_props() argument
58 ep->width = of_getintprop_default(ep->of_node, "width", 0); in e3d_get_props()
59 ep->height = of_getintprop_default(ep->of_node, "height", 0); in e3d_get_props()
60 ep->depth = of_getintprop_default(ep->of_node, "depth", 8); in e3d_get_props()
62 if (!ep->width || !ep->height) { in e3d_get_props()
64 pci_name(ep->pdev)); in e3d_get_props()
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/kernel/linux/linux-5.10/drivers/video/fbdev/
Dsunxvr500.c1 /* sunxvr500.c: Sun 3DLABS XVR-500 Expert3D fb driver for sparc64 systems
10 #include <linux/pci.h>
16 /* XXX This device has a 'dev-comm' property which apparently is
21 * XXX as the values in the 'dev-comm' area are accurate then
55 static int e3d_get_props(struct e3d_info *ep) in e3d_get_props() argument
57 ep->width = of_getintprop_default(ep->of_node, "width", 0); in e3d_get_props()
58 ep->height = of_getintprop_default(ep->of_node, "height", 0); in e3d_get_props()
59 ep->depth = of_getintprop_default(ep->of_node, "depth", 8); in e3d_get_props()
61 if (!ep->width || !ep->height) { in e3d_get_props()
63 pci_name(ep->pdev)); in e3d_get_props()
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/kernel/linux/linux-6.6/Documentation/PCI/endpoint/
Dpci-ntb-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide
9 This document is a guide to help users use pci-epf-ntb function driver
11 be followed in the host side and EP side is given below. For the hardware
13 Documentation/PCI/endpoint/pci-ntb-function.rst
19 ---------------------------
27 2900000.pcie-ep 2910000.pcie-ep
32 2900000.pcie-ep 2910000.pcie-ep
36 -------------------------
40 # ls /sys/bus/pci-epf/drivers
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dpci-keystone.txt3 Keystone PCI host Controller is based on the Synopsys DesignWare PCI
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
22 interrupt-cells: should be set to 1
23 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-pcie-ep
22 - socionext,uniphier-nx1-pcie-ep
28 reg-names:
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Dti,j721e-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI EP (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: cdns-pcie-ep.yaml#
19 - const: ti,j721e-pcie-ep
20 - description: PCIe EP controller in AM64
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