| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pci-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
100 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
101 #define AFI_CONFIGURATION_CLKEN_OVERRIDE (1 << 31)
106 #define AFI_INTR_MASK_INT_MASK (1 << 0)
107 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
111 #define AFI_INTR_INI_SLAVE_ERROR 1
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| D | pcie-altera.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
6 * Description: Altera PCIe host controller driver
45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
50 /* TLP configuration type 0 and 1 */
53 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
54 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
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| D | pcie-rcar-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe endpoint driver for Renesas R-Car SoCs
6 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
16 #include <linux/pci-epc.h>
20 #include "pcie-rcar.h"
22 #define RCAR_EPC_MAX_FUNCTIONS 1
24 /* Structure representing the PCIe interface */
26 struct rcar_pcie pcie; member
36 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie) in rcar_pcie_ep_hw_init() argument
40 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_ep_hw_init()
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| D | pcie-brcmstb.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
34 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
37 /* Broadcom STB PCIe Register Offsets */
144 /* PCIe parameters */
163 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
164 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
175 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) argument
176 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) argument
177 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) argument
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| D | pci-aardvark.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
28 #include "../pci-bridge-emul.h"
30 /* PCIe core registers */
40 #define PCIE_CORE_INT_A_ASSERT_ENABLE 1
53 #define PIO_COMPLETION_STATUS_UR 1
73 #define SPEED_GEN_2 1
75 #define IS_RC_MSK 1
80 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
97 #define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1)
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| D | pcie-rcar-host.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
33 #include "pcie-rcar.h"
50 /* Structure representing the PCIe interface */
52 struct rcar_pcie pcie; member
61 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) in rcar_read_conf() argument
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| /kernel/linux/linux-6.6/drivers/pci/controller/ |
| D | pci-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
86 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
87 #define AFI_CONFIGURATION_CLKEN_OVERRIDE (1 << 31)
92 #define AFI_INTR_MASK_INT_MASK (1 << 0)
93 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
97 #define AFI_INTR_INI_SLAVE_ERROR 1
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| D | pcie-altera.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
6 * Description: Altera PCIe host controller driver
44 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
45 (((pcie)->hip_base) + (reg) + (1 << 20))
46 #define S10_RP_SECONDARY(pcie) \ argument
47 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
49 /* TLP configuration type 0 and 1 */
52 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
53 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
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| D | pci-aardvark.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
20 #include <linux/pci-ecam.h>
30 #include "../pci-bridge-emul.h"
32 /* PCIe core registers */
53 #define PIO_COMPLETION_STATUS_UR 1
73 #define SPEED_GEN_2 1
75 #define IS_RC_MSK 1
80 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
97 #define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1)
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| D | pcie-brcmstb.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
40 /* Broadcom STB PCIe Register Offsets */
147 /* PCIe parameters */
152 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
154 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
169 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
170 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
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| D | pcie-rcar-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe endpoint driver for Renesas R-Car SoCs
6 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 #include <linux/pci-epc.h>
17 #include "pcie-rcar.h"
19 #define RCAR_EPC_MAX_FUNCTIONS 1
21 /* Structure representing the PCIe interface */
23 struct rcar_pcie pcie; member
33 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie) in rcar_pcie_ep_hw_init() argument
37 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_ep_hw_init()
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| D | pcie-rcar-host.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
16 #include <linux/clk-provider.h>
33 #include "pcie-rcar.h"
44 /* Structure representing the PCIe interface */
46 struct rcar_pcie pcie; member
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| D | pcie-iproc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
28 #define EP_MODE_SURVIVE_PERST_SHIFT 1
43 #define CFG_ADDR_CFG_TYPE_1 1
56 #define CFG_RD_UR 1
73 #define OARR_SIZE_CFG_SHIFT 1
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
20 - enum:
21 - qcom,pcie-apq8064
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| D | fsl,imx6q-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe RC/EP controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 Generic Freescale i.MX PCIe Root Port and Endpoint controller
22 clock-names:
26 num-lanes:
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| /kernel/linux/linux-5.10/drivers/pci/controller/mobiveil/ |
| D | pcie-mobiveil-host.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Mobiveil PCIe Host controller
6 * Copyright 2019-2020 NXP
28 #include "pcie-mobiveil.h"
40 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
47 * mobiveil_pcie_map_bus - routine to get the configuration base of either
53 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
54 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
62 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
70 value = bus->number << PAB_BUS_SHIFT | in mobiveil_pcie_map_bus()
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| D | pcie-mobiveil.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Mobiveil PCIe Host controller
18 #include "pcie-mobiveil.h"
21 * mobiveil_pcie_sel_page - routine to access paged register
28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
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| /kernel/linux/linux-6.6/drivers/pci/controller/mobiveil/ |
| D | pcie-mobiveil-host.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Mobiveil PCIe Host controller
6 * Copyright 2019-2020 NXP
25 #include "pcie-mobiveil.h"
37 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
44 * mobiveil_pcie_map_bus - routine to get the configuration base of either
50 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
51 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
59 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
67 value = bus->number << PAB_BUS_SHIFT | in mobiveil_pcie_map_bus()
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| D | pcie-mobiveil.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Mobiveil PCIe Host controller
18 #include "pcie-mobiveil.h"
21 * mobiveil_pcie_sel_page - routine to access paged register
28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | qcom,sc8280xp-qmp-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
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| /kernel/linux/linux-6.6/drivers/pci/controller/cadence/ |
| D | pcie-cadence-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe endpoint controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include <linux/pci-epc.h>
13 #include "pcie-cadence.h"
19 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) in cdns_pcie_get_fn_from_vfn() argument
27 first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); in cdns_pcie_get_fn_from_vfn()
28 stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); in cdns_pcie_get_fn_from_vfn()
29 fn = fn + first_vf_offset + ((vfn - 1) * stride); in cdns_pcie_get_fn_from_vfn()
39 struct cdns_pcie *pcie = &ep->pcie; in cdns_pcie_ep_write_header() local
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| D | pci-j721e.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
10 #include <linux/clk-provider.h>
25 #include "pcie-cadence.h"
27 #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
32 #define LINK_DOWN BIT(1)
39 #define LINK_STATUS GENMASK(1, 0)
51 #define GENERATION_SEL_MASK GENMASK(1, 0)
72 unsigned int quirk_retrain_flag:1;
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| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | pcie-tegra194.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Tegra194 SoC
34 #include "pcie-designware.h"
36 #include <soc/tegra/bpmp-abi.h>
50 #define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0)
71 #define APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN BIT(1)
76 #define APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED BIT(1)
85 #define APPL_INTR_STATUS_L1_15_CFG_BME_CHGED BIT(1)
108 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR BIT(1)
113 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR BIT(1)
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| /kernel/linux/linux-6.6/drivers/pci/controller/dwc/ |
| D | pcie-tegra194.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for the following SoCs
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
35 #include "pcie-designware.h"
37 #include <soc/tegra/bpmp-abi.h>
54 #define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0)
76 #define APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN BIT(1)
81 #define APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED BIT(1)
90 #define APPL_INTR_STATUS_L1_15_CFG_BME_CHGED BIT(1)
113 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR BIT(1)
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| D | pcie-intel-gw.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Intel Gateway SoCs
20 #include "pcie-designware.h"
22 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
26 /* PCIe Application logic Registers */
84 static inline void pcie_app_wr(struct intel_pcie *pcie, u32 ofs, u32 val) in pcie_app_wr() argument
86 writel(val, pcie->app_base + ofs); in pcie_app_wr()
89 static void pcie_app_wr_mask(struct intel_pcie *pcie, u32 ofs, in pcie_app_wr_mask() argument
92 pcie_update_bits(pcie->app_base, ofs, mask, val); in pcie_app_wr_mask()
95 static inline u32 pcie_rc_cfg_rd(struct intel_pcie *pcie, u32 ofs) in pcie_rc_cfg_rd() argument
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