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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dqcom,qmp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
14 QMP phy controller supports physical layer functionality for a number of
20 - qcom,ipq8074-qmp-pcie-phy
21 - qcom,ipq8074-qmp-usb3-phy
22 - qcom,msm8996-qmp-pcie-phy
[all …]
Dbcm-ns-usb2-phy.txt1 Driver for Broadcom Northstar USB 2.0 PHY
4 - compatible: brcm,ns-usb2-phy
5 - reg: iomem address range of DMU (Device Management Unit)
6 - reg-names: "dmu", the only needed & supported reg right now
7 - clocks: USB PHY reference clock
8 - clock-names: "phy-ref-clk", the only needed & supported clock right now
10 To initialize USB 2.0 PHY driver needs to setup PLL correctly. To do this it
11 requires passing phandle to the USB PHY reference clock.
14 usb2-phy {
15 compatible = "brcm,ns-usb2-phy";
[all …]
Dphy-mtk-xsphy.txt1 MediaTek XS-PHY binding
2 --------------------------
4 The XS-PHY controller supports physical layer functionality for USB3.1
8 - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
9 soc-model is the name of SoC, such as mt3611 etc;
12 - "mediatek,mt3611-xsphy"
14 - #address-cells, #size-cells : should use the same values as the root node
15 - ranges: must be present
18 - reg : offset and length of register shared by multiple U3 ports,
21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR803x PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
23 $ref: /schemas/types.yaml#/definitions/uint32
[all …]
Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
26 - compatible
29 - $ref: snps,dwmac.yaml#
[all …]
Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7110-dwmac
21 - compatible
26 - enum:
27 - starfive,jh7110-dwmac
[all …]
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI DP83869 ethernet PHY
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR803x PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
23 $ref: /schemas/types.yaml#/definitions/uint32
[all …]
Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/stm32-dwmac.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Alexandre Torgue <alexandre.torgue@st.com>
12 - Christophe Roullier <christophe.roullier@st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
26 - compatible
29 - $ref: "snps,dwmac.yaml#"
[all …]
Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI DP83867 ethernet PHY
11 - $ref: "ethernet-controller.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
27 Specifications about the Ethernet PHY can be found at:
34 ti,min-output-impedance:
[all …]
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI DP83869 ethernet PHY
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8 SoC series PCIe PHY
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
[all …]
Dmediatek,xsphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek XS-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The XS-PHY controller supports physical layer functionality for USB3.1
18 ----------------------------------
45 pattern: "^xs-phy@[0-9a-f]+$"
49 - enum:
[all …]
Dbcm-ns-usb2-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/bcm-ns-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Northstar USB 2.0 PHY
10 To initialize USB 2.0 PHY driver needs to setup PLL correctly.
11 To do this it requires passing phandle to the USB PHY reference clock.
14 - Rafał Miłecki <rafal@milecki.pl>
18 const: brcm,ns-usb2-phy
22 - maxItems: 1
[all …]
Dqcom,usb-hs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm's USB HS PHY
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 - qcom,usb-hs-phy-apq8064
18 - qcom,usb-hs-phy-msm8960
24 reset-names:
33 reset-names:
[all …]
Dmediatek,tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/
Dnxp,imx8mq-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ MIPI CSI-2 receiver
10 - Martin Kepplinger <martin.kepplinger@puri.sm>
12 description: |-
13 This binding covers the CSI-2 RX PHY and host controller included in the
20 - fsl,imx8mq-mipi-csi2
27 - description: core is the RX Controller Core Clock input. This clock
[all …]
Dnxp,imx-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
[all …]
/kernel/linux/linux-6.6/drivers/phy/broadcom/
Dphy-bcm-ns-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom Northstar USB 2.0 PHY Driver
9 #include <linux/clk.h>
16 #include <linux/phy/phy.h>
23 struct clk *ref_clk;
24 struct phy *phy; member
32 static int bcm_ns_usb2_phy_init(struct phy *phy) in bcm_ns_usb2_phy_init() argument
34 struct bcm_ns_usb2 *usb2 = phy_get_drvdata(phy); in bcm_ns_usb2_phy_init()
35 struct device *dev = usb2->dev; in bcm_ns_usb2_phy_init()
39 err = clk_prepare_enable(usb2->ref_clk); in bcm_ns_usb2_phy_init()
[all …]
/kernel/linux/linux-5.10/drivers/phy/broadcom/
Dphy-bcm-ns-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom Northstar USB 2.0 PHY Driver
9 #include <linux/clk.h>
15 #include <linux/phy/phy.h>
21 struct clk *ref_clk;
22 struct phy *phy; member
26 static int bcm_ns_usb2_phy_init(struct phy *phy) in bcm_ns_usb2_phy_init() argument
28 struct bcm_ns_usb2 *usb2 = phy_get_drvdata(phy); in bcm_ns_usb2_phy_init()
29 struct device *dev = usb2->dev; in bcm_ns_usb2_phy_init()
30 void __iomem *dmu = usb2->dmu; in bcm_ns_usb2_phy_init()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/
Dnwl-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
10 - Guido Gúnther <agx@sigxcpu.org>
11 - Robert Chiras <robert.chiras@nxp.com>
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
18 - $ref: ../dsi-controller.yaml#
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
27 $ref: usb.yaml#
29 $ref: usb-xhci.yaml#
[all …]
Dfsl,imx8mq-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/fsl,imx8mq-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Jun <jun.li@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
18 - fsl,imx8mq-dwc3
20 - compatible
25 - const: fsl,imx8mq-dwc3
26 - const: snps,dwc3
[all …]
/kernel/linux/linux-5.10/drivers/phy/qualcomm/
Dphy-qcom-snps-femto-v2.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
14 #include <linux/phy/phy.h>
63 "vdda-pll", "vdda33", "vdda18",
69 * struct qcom_snps_hsphy - snps hs phy attributes
73 * @phy: generic phy
74 * @base: iomapped memory space for snps hs phy
78 * @phy_reset: phy reset control
80 * @phy_initialized: if PHY has been initialized correctly
81 * @mode: contains the current mode the PHY is in
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/ufs/
Dufs-qcom.txt1 * Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY
3 UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
4 Each UFS PHY node should have its own node.
6 To bind UFS PHY with UFS host controller, the controller node should
7 contain a phandle reference to UFS PHY node.
10 - compatible : compatible list, contains one of the following -
11 "qcom,ufs-phy-qmp-20nm" for 20nm ufs phy,
12 "qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy,
13 "qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy
15 - reg : should contain PHY register address space (mandatory),
[all …]

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