| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/leds/ |
| D | kinetic,ktd2692.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Markuss Broks <markuss.broks@gmail.com>
13 KTD2692 is the ideal power solution for high-power flash LEDs.
14 It uses ExpressWire single-wire programming for maximum flexibility.
16 The ExpressWire interface through CTRL pin can control LED on/off and
17 enable/disable the IC, Movie(max 1/3 of Flash current) / Flash mode current,
20 Also, When the AUX pin is pulled high while CTRL pin is high,
21 LED current will be ramped up to the flash-mode current level.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/leds/ |
| D | leds-ktd2692.txt | 1 * Kinetic Technologies - KTD2692 Flash LED Driver
3 KTD2692 is the ideal power solution for high-power flash LEDs.
4 It uses ExpressWire single-wire programming for maximum flexibility.
6 The ExpressWire interface through CTRL pin can control LED on/off and
7 enable/disable the IC, Movie(max 1/3 of Flash current) / Flash mode current,
10 Also, When the AUX pin is pulled high while CTRL pin is high,
11 LED current will be ramped up to the flash-mode current level.
14 - compatible : Should be "kinetic,ktd2692".
15 - ctrl-gpios : Specifier of the GPIO connected to CTRL pin.
16 - aux-gpios : Specifier of the GPIO connected to AUX pin.
[all …]
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| /kernel/linux/linux-5.10/drivers/rtc/ |
| D | rtc-jz4740.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
41 /* Magic value to enable writes on jz4780 */
66 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
71 uint32_t ctrl; in jz4740_rtc_wait_write_ready() local
75 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL); in jz4740_rtc_wait_write_ready()
76 } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout); in jz4740_rtc_wait_write_ready()
78 return timeout ? 0 : -EIO; in jz4740_rtc_wait_write_ready()
83 uint32_t ctrl; in jz4780_rtc_enable_write() local
90 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
[all …]
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| /kernel/linux/linux-6.6/drivers/pinctrl/qcom/ |
| D | pinctrl-lpass-lpi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
15 #include <linux/pinctrl/pinconf-generic.h>
19 #include "../pinctrl-utils.h"
21 #include "pinctrl-lpass-lpi.h"
29 struct pinctrl_dev *ctrl; member
41 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, in lpi_gpio_read() argument
44 return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); in lpi_gpio_read()
47 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, in lpi_gpio_write() argument
50 iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); in lpi_gpio_write()
[all …]
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| /kernel/linux/linux-6.6/drivers/rtc/ |
| D | rtc-jz4740.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/clk-provider.h>
45 /* Magic value to enable writes on jz4780 */
75 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
80 uint32_t ctrl; in jz4740_rtc_wait_write_ready() local
82 return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl, in jz4740_rtc_wait_write_ready()
83 ctrl & JZ_RTC_CTRL_WRDY, 0, 1000); in jz4740_rtc_wait_write_ready()
88 uint32_t ctrl; in jz4780_rtc_enable_write() local
95 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/samsung/ |
| D | pinctrl-samsung.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 // pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
28 #include <dt-bindings/pinctrl/samsung.h>
31 #include "pinctrl-samsung.h"
41 { "samsung,pin-pud", PINCFG_TYPE_PUD },
42 { "samsung,pin-drv", PINCFG_TYPE_DRV },
43 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
44 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
45 { "samsung,pin-val", PINCFG_TYPE_DAT },
54 return pmx->nr_groups; in samsung_get_group_count()
[all …]
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| D | pinctrl-samsung.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
27 * @PINCFG_TYPE_DAT: Pin value configuration.
30 * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
45 * pin configuration (pull up/down and drive strength) type and its value are
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
57 * enum eint_type - possible external interrupt types.
64 * in a pin bank can support external gpio interrupts or external wakeup
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/ |
| D | pinctrl-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
29 #include <linux/pinctrl/pinconf-generic.h>
34 #include <dt-bindings/pinctrl/rockchip.h>
88 * @offset: if initialized to -1 it will be autocalculated, by specifying
121 * @offset: if initialized to -1 it will be autocalculated, by specifying
139 * @pin_base: first pin number
188 { .offset = -1 }, \
[all …]
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| /kernel/linux/linux-6.6/drivers/pinctrl/samsung/ |
| D | pinctrl-samsung.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 // pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
31 #include "pinctrl-samsung.h"
41 { "samsung,pin-pud", PINCFG_TYPE_PUD },
42 { "samsung,pin-drv", PINCFG_TYPE_DRV },
43 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
44 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
45 { "samsung,pin-val", PINCFG_TYPE_DAT },
54 return pmx->nr_groups; in samsung_get_group_count()
62 return pmx->pin_groups[group].name; in samsung_get_group_name()
[all …]
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| D | pinctrl-samsung.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
27 * @PINCFG_TYPE_DAT: Pin value configuration.
30 * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
45 * pin configuration (pull up/down and drive strength) type and its value are
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
57 * Values for the pin CON register, choosing pin function.
65 * enum eint_type - possible external interrupt types.
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/intel/igc/ |
| D | igc_ptp.c | 1 // SPDX-License-Identifier: GPL-2.0
26 struct igc_hw *hw = &adapter->hw; in igc_ptp_read()
33 ts->tv_sec = sec; in igc_ptp_read()
34 ts->tv_nsec = nsec; in igc_ptp_read()
40 struct igc_hw *hw = &adapter->hw; in igc_ptp_write_i225()
42 wr32(IGC_SYSTIML, ts->tv_nsec); in igc_ptp_write_i225()
43 wr32(IGC_SYSTIMH, ts->tv_sec); in igc_ptp_write_i225()
50 struct igc_hw *hw = &igc->hw; in igc_ptp_adjfine_i225()
57 scaled_ppm = -scaled_ppm; in igc_ptp_adjfine_i225()
79 spin_lock_irqsave(&igc->tmreg_lock, flags); in igc_ptp_adjtime_i225()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/tilcdc/ |
| D | panel.txt | 1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/tilcdc/ |
| D | panel.txt | 1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | oxnas,pinctrl.txt | 1 * Oxford Semiconductor OXNAS SoC Family Pin Controller
3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
5 pin controller, GPIO, and interrupt bindings.
7 OXNAS 'pin configuration node' is a node of a group of pins which can be
11 Required properties for pin controller node:
12 - compatible: "oxsemi,ox810se-pinctrl" or "oxsemi,ox820-pinctrl"
13 - oxsemi,sys-ctrl: a phandle to the system controller syscon node
15 Required properties for pin configuration sub-nodes:
16 - pins: List of pins to which the configuration applies.
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/intel/igb/ |
| D | igb_ptp.c | 1 // SPDX-License-Identifier: GPL-2.0+
38 * +--------------+ +---+---+------+
40 * +--------------+ +---+---+------+
43 * +----------+---+ +--------------+
45 * +----------+---+ +--------------+
50 * 2^45 * 10^-9 / 3600 = 9.77 hours.
53 * 2^40 * 10^-9 / 60 = 18.3 minutes.
67 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
77 struct e1000_hw *hw = &igb->hw; in igb_ptp_read_82576()
94 struct e1000_hw *hw = &igb->hw; in igb_ptp_read_82580()
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/intel/igb/ |
| D | igb_ptp.c | 1 // SPDX-License-Identifier: GPL-2.0+
38 * +--------------+ +---+---+------+
40 * +--------------+ +---+---+------+
43 * +----------+---+ +--------------+
45 * +----------+---+ +--------------+
50 * 2^45 * 10^-9 / 3600 = 9.77 hours.
53 * 2^40 * 10^-9 / 60 = 18.3 minutes.
67 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
79 struct e1000_hw *hw = &igb->hw; in igb_ptp_read_82576()
96 struct e1000_hw *hw = &igb->hw; in igb_ptp_read_82580()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | armada-370-synology-ds213j.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
12 * were delivered with an older version of u-boot that left internal
17 * installing it from u-boot prompt) or adjust the Devive Tree
21 /dts-v1/;
23 #include <dt-bindings/input/input.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "armada-370.dtsi"
30 "marvell,armada-370-xp";
33 stdout-path = "serial0:115200n8";
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/ |
| D | armada-370-synology-ds213j.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
12 * were delivered with an older version of u-boot that left internal
17 * installing it from u-boot prompt) or adjust the Devive Tree
21 /dts-v1/;
23 #include <dt-bindings/input/input.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "armada-370.dtsi"
30 "marvell,armada-370-xp";
33 stdout-path = "serial0:115200n8";
[all …]
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| /kernel/linux/linux-6.6/drivers/pinctrl/ |
| D | pinctrl-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
30 #include <linux/pinctrl/pinconf-generic.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
41 #include "pinctrl-rockchip.h"
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
[all …]
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| /kernel/linux/linux-6.6/drivers/net/phy/ |
| D | icplus.c | 1 // SPDX-License-Identifier: GPL-2.0+
33 /* IP101A/G - IP1001 */
42 #define IP101A_G_IRQ_PIN_USED BIT(15) /* INTR pin used */
69 /* The 32-pin IP101GR package can re-configure the mode of the RXER/INTR_32 pin
70 * (pin number 21). The hardware default is RXER (receive error) mode. But it
102 err = mdiobus_write(phydev->mdio.bus, 30, 0, 0x175c); in ip175c_config_init()
107 err = mdiobus_read(phydev->mdio.bus, 30, 0); in ip175c_config_init()
112 /* enable IP175C mode */ in ip175c_config_init()
113 err = mdiobus_write(phydev->mdio.bus, 29, 31, 0x175c); in ip175c_config_init()
118 err = mdiobus_write(phydev->mdio.bus, 29, 22, 0x420); in ip175c_config_init()
[all …]
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| D | bcm-phy-ptp.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #include "bcm-phy-lib.h"
134 struct ptp_pin_desc pin; member
158 #define BCM_SKB_CB(skb) ((struct bcm_ptp_skb_cb *)(skb)->cb)
161 #define BCM_MAX_PULSE_8NS ((1U << 9) - 1)
162 #define BCM_MAX_PERIOD_8NS ((1U << 30) - 1)
165 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
192 ts->tv_sec = (hb[3] << 16) | hb[2]; in bcm_ptp_get_framesync_ts()
193 ts->tv_nsec = (hb[1] << 16) | hb[0]; in bcm_ptp_get_framesync_ts()
198 u16 ctrl = orig_ctrl & ~(NSE_FRAMESYNC_MASK | NSE_CAPTURE_EN); in bcm_ptp_framesync_disable() local
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/regulator/ |
| D | qcom,spmi-regulator.txt | 3 - compatible:
7 "qcom,pm8004-regulators"
8 "qcom,pm8005-regulators"
9 "qcom,pm8841-regulators"
10 "qcom,pm8916-regulators"
11 "qcom,pm8941-regulators"
12 "qcom,pm8950-regulators"
13 "qcom,pm8994-regulators"
14 "qcom,pmi8994-regulators"
15 "qcom,pm660-regulators"
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/qcom/ |
| D | pinctrl-spmi-mpp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
10 #include <linux/pinctrl/pinconf-generic.h>
18 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
21 #include "../pinctrl-utils.h"
26 * Pull Up Values - it indicates whether a pull-up should be
97 /* Qualcomm specific pin configurations */
104 * struct pmic_mpp_pad - keep current MPP settings
108 * @out_value: Cached pin output value.
111 * @paired: Pin operates in paired mode
[all …]
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| /kernel/linux/linux-5.10/arch/sparc/kernel/ |
| D | leon_pci_grpci2.c | 1 // SPDX-License-Identifier: GPL-2.0
29 * - barcfgs : Custom Configuration of Host's 6 target BARs
30 * - irq_mask : Limit which PCI interrupts are enabled
31 * - do_reset : Force PCI Reset on startup
39 * -1 means not configured (let host driver do default setup).
48 * Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default
63 /* Enable Debugging Configuration Space Access */
70 unsigned int ctrl; /* 0x00 Control */ member
77 unsigned int bars[6]; /* 0x20 read-only PCI BARs */
79 unsigned int ahbmst_map[16]; /* 0x40 AHB->PCI Map per AHB Master */
[all …]
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| /kernel/linux/linux-6.6/arch/sparc/kernel/ |
| D | leon_pci_grpci2.c | 1 // SPDX-License-Identifier: GPL-2.0
31 * - barcfgs : Custom Configuration of Host's 6 target BARs
32 * - irq_mask : Limit which PCI interrupts are enabled
33 * - do_reset : Force PCI Reset on startup
41 * -1 means not configured (let host driver do default setup).
50 * Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default
65 /* Enable Debugging Configuration Space Access */
72 unsigned int ctrl; /* 0x00 Control */ member
79 unsigned int bars[6]; /* 0x20 read-only PCI BARs */
81 unsigned int ahbmst_map[16]; /* 0x40 AHB->PCI Map per AHB Master */
[all …]
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