| /kernel/linux/linux-6.6/drivers/gpio/ |
| D | gpio-lpc32xx.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
168 static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset) in gpreg_read() argument
170 return __raw_readl(group->reg_base + offset); in gpreg_read()
173 static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset) in gpreg_write() argument
175 __raw_writel(val, group->reg_base + offset); in gpreg_write()
178 static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, in __set_gpio_dir_p012() argument
179 unsigned pin, int input) in __set_gpio_dir_p012() argument
182 gpreg_write(group, GPIO012_PIN_TO_BIT(pin), in __set_gpio_dir_p012()
183 group->gpio_grp->dir_clr); in __set_gpio_dir_p012()
185 gpreg_write(group, GPIO012_PIN_TO_BIT(pin), in __set_gpio_dir_p012()
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-lpc32xx.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
168 static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset) in gpreg_read() argument
170 return __raw_readl(group->reg_base + offset); in gpreg_read()
173 static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset) in gpreg_write() argument
175 __raw_writel(val, group->reg_base + offset); in gpreg_write()
178 static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, in __set_gpio_dir_p012() argument
179 unsigned pin, int input) in __set_gpio_dir_p012() argument
182 gpreg_write(group, GPIO012_PIN_TO_BIT(pin), in __set_gpio_dir_p012()
183 group->gpio_grp->dir_clr); in __set_gpio_dir_p012()
185 gpreg_write(group, GPIO012_PIN_TO_BIT(pin), in __set_gpio_dir_p012()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,armada-37xx-pinctrl.txt | 1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
11 GPIO and pin controller:
12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
18 of the phrase "pin configuration node".
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
[all …]
|
| D | fsl,mxs-pinctrl.txt | 1 * Freescale MXS Pin Controller
3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
11 pin controller.
13 Please refer to pinctrl-bindings.txt in this directory for details of the
16 The node of mxs pin controller acts as a container for an arbitrary number of
18 a group of pins, and only affects those parameters that are explicitly listed.
[all …]
|
| D | cnxt,cx92755-pinctrl.txt | 1 Conexant Digicolor CX92755 General Purpose Pin Mapping
3 This document describes the device tree binding of the pin mapping hardware
7 === Pin Controller Node ===
11 - compatible: Must be "cnxt,cx92755-pinctrl"
12 - reg: Base address of the General Purpose Pin Mapping register block and the
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells: Must be <2>. The first cell is the pin number and the
16 second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
22 compatible = "cnxt,cx92755-pinctrl";
24 gpio-controller;
[all …]
|
| D | brcm,bcm11351-pinctrl.txt | 1 Broadcom BCM281xx Pin Controller
3 This is a pin controller for the Broadcom BCM281xx SoC family, which includes
6 === Pin Controller Node ===
10 - compatible: Must be "brcm,bcm11351-pinctrl"
11 - reg: Base address of the PAD Controller register block and the size
17 compatible = "brcm,bcm11351-pinctrl";
21 As a pin controller device, in addition to the required properties, this node
22 should also contain the pin configuration nodes that client devices reference,
25 === Pin Configuration Node ===
27 Each pin configuration node is a sub-node of the pin controller node and is a
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,armada-37xx-pinctrl.txt | 1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
11 GPIO and pin controller:
12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
18 of the phrase "pin configuration node".
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
[all …]
|
| D | fsl,mxs-pinctrl.txt | 1 * Freescale MXS Pin Controller
3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
11 pin controller.
13 Please refer to pinctrl-bindings.txt in this directory for details of the
16 The node of mxs pin controller acts as a container for an arbitrary number of
18 a group of pins, and only affects those parameters that are explicitly listed.
[all …]
|
| D | cnxt,cx92755-pinctrl.txt | 1 Conexant Digicolor CX92755 General Purpose Pin Mapping
3 This document describes the device tree binding of the pin mapping hardware
7 === Pin Controller Node ===
11 - compatible: Must be "cnxt,cx92755-pinctrl"
12 - reg: Base address of the General Purpose Pin Mapping register block and the
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells: Must be <2>. The first cell is the pin number and the
16 second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
22 compatible = "cnxt,cx92755-pinctrl";
24 gpio-controller;
[all …]
|
| /kernel/linux/linux-6.6/drivers/pinctrl/ |
| D | pinctrl-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP pin controller
11 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <linux/firmware/xlnx-zynqmp.h>
20 #include <linux/pinctrl/pinconf-generic.h>
26 #include "pinctrl-utils.h"
47 * struct zynqmp_pmux_function - a pinmux function
48 * @name: Name of the pin mux function
49 * @groups: List of pin groups for this function
52 * This structure holds information about pin control function
[all …]
|
| D | pinmux.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin muxing portions of the pin control subsystem
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
24 #include <linux/radix-tree.h>
38 const struct pinmux_ops *ops = pctldev->desc->pmxops; in pinmux_check_ops()
44 !ops->get_functions_count || in pinmux_check_ops()
45 !ops->get_function_name || in pinmux_check_ops()
46 !ops->get_function_groups || in pinmux_check_ops()
47 !ops->set_mux) { in pinmux_check_ops()
[all …]
|
| D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Core private header for the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
14 #include <linux/radix-tree.h>
30 * struct pinctrl_dev - pin control class device
31 * @node: node to include this pin controller in the global pin controller list
32 * @desc: the pin controller descriptor supplied when initializing this pin
34 * @pin_desc_tree: each pin descriptor for this pin controller is stored in
36 * @pin_group_tree: optionally each pin group can be stored in this radix tree
[all …]
|
| /kernel/linux/linux-5.10/drivers/pinctrl/ |
| D | pinmux.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin muxing portions of the pin control subsystem
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
20 #include <linux/radix-tree.h>
33 const struct pinmux_ops *ops = pctldev->desc->pmxops; in pinmux_check_ops()
39 !ops->get_functions_count || in pinmux_check_ops()
40 !ops->get_function_name || in pinmux_check_ops()
41 !ops->get_function_groups || in pinmux_check_ops()
42 !ops->set_mux) { in pinmux_check_ops()
[all …]
|
| D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Core private header for the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
13 #include <linux/radix-tree.h>
20 * struct pinctrl_dev - pin control class device
21 * @node: node to include this pin controller in the global pin controller list
22 * @desc: the pin controller descriptor supplied when initializing this pin
24 * @pin_desc_tree: each pin descriptor for this pin controller is stored in
26 * @pin_group_tree: optionally each pin group can be stored in this radix tree
[all …]
|
| /kernel/linux/linux-5.10/drivers/pinctrl/meson/ |
| D | pinctrl-meson8-pmx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 /* For this first generation of pinctrl driver every pinmux group can be
11 * a given pin are disabled the pin acts as a GPIO.
18 #include "pinctrl-meson.h"
19 #include "pinctrl-meson8-pmx.h"
22 * meson8_pmx_disable_other_groups() - disable other groups using a given pin
24 * @pc: meson pin controller device
25 * @pin: number of the pin
26 * @sel_group: index of the selected group, or -1 if none
28 * The function disables all pinmux groups using a pin except the
[all …]
|
| /kernel/linux/linux-6.6/drivers/pinctrl/meson/ |
| D | pinctrl-meson8-pmx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 /* For this first generation of pinctrl driver every pinmux group can be
11 * a given pin are disabled the pin acts as a GPIO.
18 #include "pinctrl-meson.h"
19 #include "pinctrl-meson8-pmx.h"
22 * meson8_pmx_disable_other_groups() - disable other groups using a given pin
24 * @pc: meson pin controller device
25 * @pin: number of the pin
26 * @sel_group: index of the selected group, or -1 if none
28 * The function disables all pinmux groups using a pin except the
[all …]
|
| /kernel/linux/linux-6.6/drivers/pinctrl/aspeed/ |
| D | pinmux-aspeed.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * functions. The SoC function enabled on a pin is determined on a priority
12 * basis where a given pin can provide a number of different signal types.
14 * The signal active on a pin is described by both a priority level and
16 * bits. Some difficulty arises as the pin's function bit masks for each
21 * read-only).
23 * SoC Multi-function Pin Expression Examples
24 * ------------------------------------------
30 * D6 is a pin with a single function (beside GPIO); a high priority signal
34 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
[all …]
|
| /kernel/linux/linux-5.10/drivers/pinctrl/aspeed/ |
| D | pinmux-aspeed.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * functions. The SoC function enabled on a pin is determined on a priority
13 * basis where a given pin can provide a number of different signal types.
15 * The signal active on a pin is described by both a priority level and
17 * bits. Some difficulty arises as the pin's function bit masks for each
22 * read-only).
24 * SoC Multi-function Pin Expression Examples
25 * ------------------------------------------
31 * D6 is a pin with a single function (beside GPIO); a high priority signal
35 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
[all …]
|
| /kernel/linux/linux-5.10/drivers/pinctrl/samsung/ |
| D | pinctrl-exynos-arm64.c | 1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include "pinctrl-samsung.h"
20 #include "pinctrl-exynos.h"
46 /* pin banks of exynos5433 pin-controller - ALIVE */
48 /* Must start with EINTG banks, ordered by EINT group number. */
60 /* pin banks of exynos5433 pin-controller - AUD */
62 /* Must start with EINTG banks, ordered by EINT group number. */
67 /* pin banks of exynos5433 pin-controller - CPIF */
69 /* Must start with EINTG banks, ordered by EINT group number. */
[all …]
|
| /kernel/linux/linux-5.10/drivers/pinctrl/intel/ |
| D | pinctrl-intel.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
26 * struct intel_pingroup - Description about group of pins
28 * @pins: All pins in this group
30 * @mode: Native mode in which the group is muxed out @pins. Used if @modes
32 * @modes: If not %NULL this will hold mode for each pin in @pins
43 * struct intel_function - Description about a function
55 * struct intel_padgroup - Hardware pad group information
57 * @base: Starting pin of this group
58 * @size: Size of this group (maximum is 32).
59 * @gpio_base: Starting GPIO base of this group
[all …]
|
| /kernel/linux/linux-6.6/drivers/pinctrl/intel/ |
| D | pinctrl-intel.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
26 * struct intel_pingroup - Description about group of pins
27 * @grp: Generic data of the pin group (name and pins)
28 * @mode: Native mode in which the group is muxed out @pins. Used if @modes is %NULL.
29 * @modes: If not %NULL this will hold mode for each pin in @pins
38 * struct intel_function - Description about a function
39 * @func: Generic data of the pin function (name and groups of pins)
48 * struct intel_padgroup - Hardware pad group information
50 * @base: Starting pin of this group
51 * @size: Size of this group (maximum is %INTEL_PINCTRL_MAX_GPP_SIZE).
[all …]
|
| /kernel/linux/linux-6.6/drivers/pinctrl/pxa/ |
| D | pinctrl-pxa2xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell PXA2xx family pin control
15 #include <linux/pinctrl/pinconf-generic.h>
21 #include "../pinctrl-utils.h"
22 #include "pinctrl-pxa2xx.h"
28 return pctl->ngroups; in pxa2xx_pctrl_get_groups_count()
35 struct pxa_pinctrl_group *group = pctl->groups + tgroup; in pxa2xx_pctrl_get_group_name() local
37 return group->name; in pxa2xx_pctrl_get_group_name()
46 struct pxa_pinctrl_group *group = pctl->groups + tgroup; in pxa2xx_pctrl_get_group_pins() local
48 *pins = (unsigned *)&group->pin; in pxa2xx_pctrl_get_group_pins()
[all …]
|
| /kernel/linux/linux-5.10/drivers/pinctrl/pxa/ |
| D | pinctrl-pxa2xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell PXA2xx family pin control
15 #include <linux/pinctrl/pinconf-generic.h>
21 #include "../pinctrl-utils.h"
22 #include "pinctrl-pxa2xx.h"
28 return pctl->ngroups; in pxa2xx_pctrl_get_groups_count()
35 struct pxa_pinctrl_group *group = pctl->groups + tgroup; in pxa2xx_pctrl_get_group_name() local
37 return group->name; in pxa2xx_pctrl_get_group_name()
46 struct pxa_pinctrl_group *group = pctl->groups + tgroup; in pxa2xx_pctrl_get_group_pins() local
48 *pins = (unsigned *)&group->pin; in pxa2xx_pctrl_get_group_pins()
[all …]
|
| /kernel/linux/linux-6.6/Documentation/driver-api/ |
| D | pin-control.rst | 2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
28 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
[all …]
|
| /kernel/linux/linux-6.6/drivers/pinctrl/samsung/ |
| D | pinctrl-exynos-arm64.c | 1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include "pinctrl-samsung.h"
20 #include "pinctrl-exynos.h"
44 * Bank type for non-alive type. Bit fields:
64 /* pin banks of exynos5433 pin-controller - ALIVE */
66 /* Must start with EINTG banks, ordered by EINT group number. */
78 /* pin banks of exynos5433 pin-controller - AUD */
80 /* Must start with EINTG banks, ordered by EINT group number. */
85 /* pin banks of exynos5433 pin-controller - CPIF */
[all …]
|