| /kernel/linux/linux-5.10/drivers/pinctrl/ |
| D | pinmux.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin muxing portions of the pin control subsystem
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
20 #include <linux/radix-tree.h>
33 const struct pinmux_ops *ops = pctldev->desc->pmxops; in pinmux_check_ops()
39 !ops->get_functions_count || in pinmux_check_ops()
40 !ops->get_function_name || in pinmux_check_ops()
41 !ops->get_function_groups || in pinmux_check_ops()
42 !ops->set_mux) { in pinmux_check_ops()
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| D | pinctrl-lantiq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinctrl-lantiq.c
4 * based on linux/drivers/pinctrl/pinctrl-pxa3xx.c
16 #include "pinctrl-lantiq.h"
21 return info->num_grps; in ltq_get_group_count()
28 if (selector >= info->num_grps) in ltq_get_group_name()
30 return info->grps[selector].name; in ltq_get_group_name()
39 if (selector >= info->num_grps) in ltq_get_group_pins()
40 return -EINVAL; in ltq_get_group_pins()
41 *pins = info->grps[selector].pins; in ltq_get_group_pins()
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| D | pinctrl-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
29 #include <linux/pinctrl/pinconf-generic.h>
34 #include <dt-bindings/pinctrl/rockchip.h>
88 * @offset: if initialized to -1 it will be autocalculated, by specifying
121 * @offset: if initialized to -1 it will be autocalculated, by specifying
139 * @pin_base: first pin number
188 { .offset = -1 }, \
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| D | pinctrl-at91.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
26 #include "pinctrl-at91.h"
95 * struct at91_pmx_func - describes AT91 pinmux functions
97 * @groups: corresponding pin groups
115 * struct at91_pmx_pin - describes an At91 pin mux
116 * @bank: the bank of the pin
117 * @pin: the pin number in the @bank
118 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
119 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
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| /kernel/linux/linux-6.6/drivers/pinctrl/ |
| D | pinmux.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin muxing portions of the pin control subsystem
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
24 #include <linux/radix-tree.h>
38 const struct pinmux_ops *ops = pctldev->desc->pmxops; in pinmux_check_ops()
44 !ops->get_functions_count || in pinmux_check_ops()
45 !ops->get_function_name || in pinmux_check_ops()
46 !ops->get_function_groups || in pinmux_check_ops()
47 !ops->set_mux) { in pinmux_check_ops()
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| D | pinctrl-lantiq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinctrl-lantiq.c
4 * based on linux/drivers/pinctrl/pinctrl-pxa3xx.c
17 #include "pinctrl-lantiq.h"
22 return info->num_grps; in ltq_get_group_count()
29 if (selector >= info->num_grps) in ltq_get_group_name()
31 return info->grps[selector].name; in ltq_get_group_name()
40 if (selector >= info->num_grps) in ltq_get_group_pins()
41 return -EINVAL; in ltq_get_group_pins()
42 *pins = info->grps[selector].pins; in ltq_get_group_pins()
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| D | pinctrl-at91.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
29 #include "pinctrl-at91.h"
46 * @ops: at91 pinctrl mux ops
114 * struct at91_pmx_func - describes AT91 pinmux functions
116 * @groups: corresponding pin groups
134 * struct at91_pmx_pin - describes an At91 pin mux
135 * @bank: the bank of the pin
136 * @pin: the pin number in the @bank
137 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
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| D | pinctrl-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
30 #include <linux/pinctrl/pinconf-generic.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
41 #include "pinctrl-rockchip.h"
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | lantiq,pinctrl-xway.txt | 4 - compatible: "lantiq,<chip>-pinctrl", where <chip> is:
10 - reg: Should contain the physical address and length of the gpio/pinmux
13 Please refer to pinctrl-bindings.txt in this directory for details of the
15 phrase "pin configuration node".
17 Lantiq's pin configuration nodes act as a container for an arbitrary number of
19 pin, a group, or a list of pins or groups. This configuration can include the
20 mux function to select on those group(s), and two pin configuration parameters:
21 pull-up and open-drain
27 other words, a subnode that lists a mux function but no pin configuration
28 parameters implies no information about any pin configuration parameters.
[all …]
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| D | cortina,gemini-pinctrl.txt | 1 Cortina Systems Gemini pin controller
3 This pin controller is found in the Cortina Systems Gemini SoC family,
4 see further arm/gemini.txt. It is a purely group-based multiplexing pin
7 The pin controller node must be a subnode of the system controller node.
10 - compatible: "cortina,gemini-pinctrl"
12 Subnodes of the pin controller contain pin control multiplexing set-up
13 and pin configuration of individual pins.
15 Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
16 and generic pin config nodes.
19 - skew-delay is supported on the Ethernet pins
[all …]
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| D | lantiq,pinctrl-falcon.txt | 4 - compatible: "lantiq,pinctrl-falcon"
5 - reg: Should contain the physical address and length of the gpio/pinmux
8 Please refer to pinctrl-bindings.txt in this directory for details of the
10 phrase "pin configuration node".
12 Lantiq's pin configuration nodes act as a container for an arbitrary number of
14 pin, a group, or a list of pins or groups. This configuration can include the
15 mux function to select on those group(s), and two pin configuration parameters:
16 pull-up and open-drain
22 other words, a subnode that lists a mux function but no pin configuration
23 parameters implies no information about any pin configuration parameters.
[all …]
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| D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
15 used for a specific device or function. This node represents both mux and config
16 of the pins in that group. The 'mux' selects the function mode(also named mux
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
24 Required properties for pin configuration node:
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/zte/ |
| D | pinctrl-zx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/pinctrl/pinconf-generic.h>
18 #include "../pinctrl-utils.h"
20 #include "pinctrl-zx.h"
61 struct zx_pinctrl_soc_info *info = zpctl->info; in zx_set_mux()
62 const struct pinctrl_pin_desc *pindesc = info->pins + group_selector; in zx_set_mux()
63 struct zx_pin_data *data = pindesc->drv_data; in zx_set_mux()
64 struct zx_mux_desc *mux; in zx_set_mux() local
70 /* Skip reserved pin */ in zx_set_mux()
72 return -EINVAL; in zx_set_mux()
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| D | pinctrl-zx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * struct zx_mux_desc - hardware mux descriptor
12 * @name: mux function name
13 * @muxval: mux register bit value
21 * struct zx_pin_data - hardware per-pin data
22 * @aon_pin: whether it's an AON pin
28 * @muxes: available mux function names and corresponding register values
31 * arbitrarily, AON pinmux register bits are well organized per pin id, and
32 * each pin occupies two bits, so that we can calculate the AON register offset
33 * and bit position from pin id. Thus, we only need to define TOP pinmux and
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | lantiq,pinctrl-xway.txt | 4 - compatible: "lantiq,pinctrl-xway", (DEPRECATED: Use "lantiq,pinctrl-danube")
5 "lantiq,pinctrl-xr9", (DEPRECATED: Use "lantiq,xrx100-pinctrl" or
6 "lantiq,xrx200-pinctrl")
7 "lantiq,pinctrl-ase", (DEPRECATED: Use "lantiq,ase-pinctrl")
8 "lantiq,<chip>-pinctrl", where <chip> is:
14 - reg: Should contain the physical address and length of the gpio/pinmux
17 Please refer to pinctrl-bindings.txt in this directory for details of the
19 phrase "pin configuration node".
21 Lantiq's pin configuration nodes act as a container for an arbitrary number of
23 pin, a group, or a list of pins or groups. This configuration can include the
[all …]
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| D | cortina,gemini-pinctrl.txt | 1 Cortina Systems Gemini pin controller
3 This pin controller is found in the Cortina Systems Gemini SoC family,
4 see further arm/gemini.txt. It is a purely group-based multiplexing pin
7 The pin controller node must be a subnode of the system controller node.
10 - compatible: "cortina,gemini-pinctrl"
12 Subnodes of the pin controller contain pin control multiplexing set-up
13 and pin configuration of individual pins.
15 Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
16 and generic pin config nodes.
19 - skew-delay is supported on the Ethernet pins
[all …]
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| D | lantiq,pinctrl-falcon.txt | 4 - compatible: "lantiq,pinctrl-falcon"
5 - reg: Should contain the physical address and length of the gpio/pinmux
8 Please refer to pinctrl-bindings.txt in this directory for details of the
10 phrase "pin configuration node".
12 Lantiq's pin configuration nodes act as a container for an arbitrary number of
14 pin, a group, or a list of pins or groups. This configuration can include the
15 mux function to select on those group(s), and two pin configuration parameters:
16 pull-up and open-drain
22 other words, a subnode that lists a mux function but no pin configuration
23 parameters implies no information about any pin configuration parameters.
[all …]
|
| D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
15 used for a specific device or function. This node represents both mux and config
16 of the pins in that group. The 'mux' selects the function mode(also named mux
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
24 Required properties for pin configuration node:
[all …]
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| /kernel/linux/linux-6.6/drivers/pinctrl/bcm/ |
| D | pinctrl-ns2-mux.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * corresponding mfio pin group is selected as gpio.
16 #include <linux/pinctrl/pinconf-generic.h>
22 #include "../pinctrl-utils.h"
45 * @offset: register offset for mux configuration of a group
46 * @shift: bit shift for mux configuration of a group
63 * @is_configured: flag to indicate whether a mux setting has already
67 struct ns2_mux mux; member
77 * @mux: Northstar2 group based IOMUX configuration
83 const struct ns2_mux mux; member
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| D | pinctrl-nsp-mux.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * a group based selection. The gpio_a 8 - 11 are muxed with gpio_b and pwm.
10 * gpio_a (8 - 11)
11 * +----------
13 * gpio_a (8-11) | gpio_b (0 - 3)
14 * ------------------------+-------+----------
16 * | pwm (0 - 3)
17 * +----------
27 #include <linux/pinctrl/pinconf-generic.h>
33 #include "../pinctrl-utils.h"
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| /kernel/linux/linux-5.10/drivers/pinctrl/bcm/ |
| D | pinctrl-ns2-mux.c | 14 * corresponding mfio pin group is selected as gpio.
21 #include <linux/pinctrl/pinconf-generic.h>
28 #include "../pinctrl-utils.h"
51 * @offset: register offset for mux configuration of a group
52 * @shift: bit shift for mux configuration of a group
69 * @is_configured: flag to indicate whether a mux setting has already
73 struct ns2_mux mux; member
83 * @mux: Northstar2 group based IOMUX configuration
89 const struct ns2_mux mux; member
93 * Northstar2 mux function and supported pin groups
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| D | pinctrl-nsp-mux.c | 15 * a group based selection. The gpio_a 8 - 11 are muxed with gpio_b and pwm.
18 * gpio_a (8 - 11)
19 * +----------
21 * gpio_a (8-11) | gpio_b (0 - 3)
22 * ------------------------+-------+----------
24 * | pwm (0 - 3)
25 * +----------
32 #include <linux/pinctrl/pinconf-generic.h>
39 #include "../pinctrl-utils.h"
48 * @shift: bit shift for mux configuration of a group
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mux/ |
| D | gpio-mux.txt | 1 GPIO-based multiplexer controller bindings
7 - compatible : "gpio-mux"
8 - mux-gpios : list of gpios used to control the multiplexer, least
10 - #mux-control-cells : <0>
11 * Standard mux-controller bindings as decribed in mux-controller.txt
14 - idle-state : if present, the state the mux will have when idle. The
18 multiplexer GPIO pins, where the first pin is the least significant
19 bit. An active pin is a binary 1, an inactive pin is a binary 0.
23 mux: mux-controller {
24 compatible = "gpio-mux";
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| /kernel/linux/linux-5.10/drivers/pinctrl/tegra/ |
| D | pinctrl-tegra.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
44 /* argument: Integer, range is HW-dependant */
46 /* argument: Integer, range is HW-dependant */
48 /* argument: Integer, range is HW-dependant */
50 /* argument: Integer, range is HW-dependant */
52 /* argument: Integer, range is HW-dependant */
72 * struct tegra_function - Tegra pinctrl mux function
74 * @groups: An array of pin groups that may select this function.
84 * struct tegra_pingroup - Tegra pin group
85 * @name The name of the pin group.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mux/ |
| D | gpio-mux.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/gpio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
17 multiplexer GPIO pins, where the first pin is the least significant
18 bit. An active pin is a binary 1, an inactive pin is a binary 0.
22 const: gpio-mux
24 mux-gpios:
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