| /kernel/linux/linux-5.10/drivers/ide/ |
| D | ide-xfer-mode.c | 1 // SPDX-License-Identifier: GPL-2.0-only
21 * ide_xfer_verbose - return IDE mode names
22 * @mode: transfer mode
24 * Returns a constant string giving the name of the mode
28 const char *ide_xfer_verbose(u8 mode) in ide_xfer_verbose() argument
31 u8 i = mode & 0xf; in ide_xfer_verbose()
33 if (mode >= XFER_UDMA_0 && mode <= XFER_UDMA_7) in ide_xfer_verbose()
35 else if (mode >= XFER_MW_DMA_0 && mode <= XFER_MW_DMA_4) in ide_xfer_verbose()
37 else if (mode >= XFER_SW_DMA_0 && mode <= XFER_SW_DMA_2) in ide_xfer_verbose()
39 else if (mode >= XFER_PIO_0 && mode <= XFER_PIO_6) in ide_xfer_verbose()
[all …]
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| D | it821x.c | 12 * modes. In pass through mode then it is an IDE controller. In its smart
13 * mode its actually quite a capable hardware raid controller disguised
14 * as an IDE controller. Smart mode only understands DMA read/write and
16 * in other respects but lacks the raid mode.
24 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
26 * o Smart mode without RAID doesn't clear all the necessary identify
30 * - In pass through mode we do all the work you would expect
31 * - In smart mode the clocking set up is done by the controller generally
33 * - There are a few extra vendor commands that actually talk to the
34 * controller but only work PIO with no IRQ.
[all …]
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| D | sc1200.c | 2 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
66 * Here are the standard PIO mode 0-4 timings for each "format".
67 * Format-0 uses fast data reg timings, with slower command reg timings.
68 * Format-1 uses fast timings for all registers, but won't work with all drives.
77 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
81 static void sc1200_tunepio(ide_drive_t *drive, u8 pio) in sc1200_tunepio() argument
83 ide_hwif_t *hwif = drive->hwif; in sc1200_tunepio()
84 struct pci_dev *pdev = to_pci_dev(hwif->dev); in sc1200_tunepio()
85 unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0; in sc1200_tunepio()
91 pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3), in sc1200_tunepio()
[all …]
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| D | it8213.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 * it8213_set_pio_mode - set host controller for PIO mode
24 * Set the interface PIO mode.
29 struct pci_dev *dev = to_pci_dev(hwif->dev); in it8213_set_pio_mode()
30 int is_slave = drive->dn & 1; in it8213_set_pio_mode()
38 const u8 pio = drive->pio_mode - XFER_PIO_0; in it8213_set_pio_mode() local
50 if (pio > 1) in it8213_set_pio_mode()
52 if (drive->media != ide_disk) in it8213_set_pio_mode()
54 if (ide_pio_need_iordy(drive, pio)) in it8213_set_pio_mode()
59 if (pio > 1) in it8213_set_pio_mode()
[all …]
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| D | ht6560b.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1995-2000 Linus Torvalds & author (see below)
7 * HT-6560B EIDE-controller support
9 * Use hdparm utility to enable PIO mode support.
11 * Author: Mikko Ala-Fossi <maf@iki.fi>
35 * The special i/o-port that HT-6560B uses to configuration:
40 * The special i/o-port that HT-6560A uses to configuration:
43 * bit2 (0x04): "0" enables multi-master system (?)
54 * FIFO + PREFETCH (both a/b-model)
75 * gives. [see cmd640.c for an extreme example of this. -ml]
[all …]
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| /kernel/linux/linux-5.10/drivers/ata/ |
| D | pata_artop.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_artop.c - ARTOP ATA controller driver
9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
11 * driver by Thibaut VARENE <varenet@parisc-linux.org>
43 * artop62x0_pre_reset - probe begin
57 struct ata_port *ap = link->ap; in artop62x0_pre_reset()
58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in artop62x0_pre_reset()
61 if ((pdev->device & 1) && in artop62x0_pre_reset()
62 !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) in artop62x0_pre_reset()
63 return -ENOENT; in artop62x0_pre_reset()
[all …]
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| D | pata_cs5520.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * PIO mode and smarter silicon.
11 * drive for the right PIO mode. We must also ignore all the blacklists
13 * further we can do DMA on PIO only drives.
52 * cs5520_set_timings - program PIO timings
56 * Program the PIO mode timings for the controller according to the pio
60 static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio) in cs5520_set_timings() argument
62 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in cs5520_set_timings()
63 int slave = adev->devno; in cs5520_set_timings()
65 pio -= XFER_PIO_0; in cs5520_set_timings()
[all …]
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| D | pata_atiixp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_atiixp.c - ATI PATA for new ATA layer
5 * (C) 2009-2010 Bartlomiej Zolnierkiewicz
9 * linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004
39 /* Board has onboard PATA<->SATA converters */
40 .ident = "MSI E350DM-E33",
43 DMI_MATCH(DMI_BOARD_NAME, "E350DM-E33(MS-7720)"),
51 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in atiixp_cable_detect()
58 raw detection not play follow the bios mode guess */ in atiixp_cable_detect()
59 pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma); in atiixp_cable_detect()
[all …]
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| D | pata_optidma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_optidma.c - Opti DMA PATA for new ATA layer
6 * The Opti DMA controllers are related to the older PIO PCI controllers
11 * This driver should support Viper-N+, FireStar, FireStar Plus.
48 * optidma_pre_reset - probe begin
57 struct ata_port *ap = link->ap; in optidma_pre_reset()
58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in optidma_pre_reset()
63 if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits)) in optidma_pre_reset()
64 return -ENOENT; in optidma_pre_reset()
70 * optidma_unlock - unlock control registers
[all …]
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| D | pata_pdc2027x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
15 * as Documentation/driver-api/libata.rst
82 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
83 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
84 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
85 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
86 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
92 { 0xdf, 0x5f }, /* MDMA mode 0 */
93 { 0x6b, 0x27 }, /* MDMA mode 1 */
[all …]
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| D | pata_it821x.c | 2 * pata_it821x.c - IT821x PATA for new ATA layer
23 * modes. In pass through mode then it is an IDE controller. In its smart
24 * mode its actually quite a capable hardware raid controller disguised
25 * as an IDE controller. Smart mode only understands DMA read/write and
27 * in other respects but lacks the raid mode.
35 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
37 * o Smart mode without RAID doesn't clear all the necessary identify
41 * - In pass through mode we do all the work you would expect
42 * - In smart mode the clocking set up is done by the controller generally
44 * - There are a few extra vendor commands that actually talk to the
[all …]
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| D | pata_efar.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_efar.c - EFAR PIIX clone controller driver
6 * (C) 2009-2010 Bartlomiej Zolnierkiewicz
11 * Intel ICH controllers the EFAR widened the UDMA mode register bits
29 * efar_pre_reset - Enable bits
43 struct ata_port *ap = link->ap; in efar_pre_reset()
44 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in efar_pre_reset()
46 if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no])) in efar_pre_reset()
47 return -ENOENT; in efar_pre_reset()
53 * efar_cable_detect - check for 40/80 pin
[all …]
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| D | pata_sch.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_sch.c - Intel SCH PATA controllers
10 * Intel SCH (AF82US15W, AF82US15L, AF82UL11L) chipsets -- see spec at:
31 PM = 0x07, /* PIO Mode Bit Mask */
32 MDM = (0x03 << 8), /* Multi-word DMA Mode Bit Mask */
33 UDM = (0x07 << 16), /* Ultra DMA Mode Bit Mask */
80 MODULE_DESCRIPTION("SCSI low-level driver for Intel SCH PATA controllers");
86 * sch_set_piomode - Initialize host controller PATA PIO timings
90 * Set PIO mode for device, in host controller PCI config space.
98 unsigned int pio = adev->pio_mode - XFER_PIO_0; in sch_set_piomode() local
[all …]
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| /kernel/linux/linux-6.6/drivers/ata/ |
| D | pata_artop.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_artop.c - ARTOP ATA controller driver
9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
11 * driver by Thibaut VARENE <varenet@parisc-linux.org>
43 * artop62x0_pre_reset - probe begin
57 struct ata_port *ap = link->ap; in artop62x0_pre_reset()
58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in artop62x0_pre_reset()
61 if ((pdev->device & 1) && in artop62x0_pre_reset()
62 !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) in artop62x0_pre_reset()
63 return -ENOENT; in artop62x0_pre_reset()
[all …]
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| D | pata_atiixp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_atiixp.c - ATI PATA for new ATA layer
5 * (C) 2009-2010 Bartlomiej Zolnierkiewicz
9 * linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004
39 /* Board has onboard PATA<->SATA converters */
40 .ident = "MSI E350DM-E33",
43 DMI_MATCH(DMI_BOARD_NAME, "E350DM-E33(MS-7720)"),
51 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in atiixp_cable_detect()
58 raw detection not play follow the bios mode guess */ in atiixp_cable_detect()
59 pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma); in atiixp_cable_detect()
[all …]
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| D | pata_cs5520.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * PIO mode and smarter silicon.
11 * drive for the right PIO mode. We must also ignore all the blacklists
13 * further we can do DMA on PIO only drives.
52 * cs5520_set_timings - program PIO timings
55 * @pio: PIO ID
57 * Program the PIO mode timings for the controller according to the pio
61 static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio) in cs5520_set_timings() argument
63 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in cs5520_set_timings()
64 int slave = adev->devno; in cs5520_set_timings()
[all …]
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| D | pata_optidma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_optidma.c - Opti DMA PATA for new ATA layer
6 * The Opti DMA controllers are related to the older PIO PCI controllers
11 * This driver should support Viper-N+, FireStar, FireStar Plus.
48 * optidma_pre_reset - probe begin
57 struct ata_port *ap = link->ap; in optidma_pre_reset()
58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in optidma_pre_reset()
63 if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits)) in optidma_pre_reset()
64 return -ENOENT; in optidma_pre_reset()
70 * optidma_unlock - unlock control registers
[all …]
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| D | pata_it821x.c | 2 * pata_it821x.c - IT821x PATA for new ATA layer
23 * modes. In pass through mode then it is an IDE controller. In its smart
24 * mode its actually quite a capable hardware raid controller disguised
25 * as an IDE controller. Smart mode only understands DMA read/write and
27 * in other respects but lacks the raid mode.
35 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
37 * o Smart mode without RAID doesn't clear all the necessary identify
41 * - In pass through mode we do all the work you would expect
42 * - In smart mode the clocking set up is done by the controller generally
44 * - There are a few extra vendor commands that actually talk to the
[all …]
|
| D | pata_pdc2027x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
15 * as Documentation/driver-api/libata.rst
75 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
76 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
77 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
78 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
79 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
85 { 0xdf, 0x5f }, /* MDMA mode 0 */
86 { 0x6b, 0x27 }, /* MDMA mode 1 */
[all …]
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| D | pata_efar.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_efar.c - EFAR PIIX clone controller driver
6 * (C) 2009-2010 Bartlomiej Zolnierkiewicz
11 * Intel ICH controllers the EFAR widened the UDMA mode register bits
29 * efar_pre_reset - Enable bits
43 struct ata_port *ap = link->ap; in efar_pre_reset()
44 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in efar_pre_reset()
46 if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no])) in efar_pre_reset()
47 return -ENOENT; in efar_pre_reset()
53 * efar_cable_detect - check for 40/80 pin
[all …]
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| D | pata_sch.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_sch.c - Intel SCH PATA controllers
10 * Intel SCH (AF82US15W, AF82US15L, AF82UL11L) chipsets -- see spec at:
31 PM = 0x07, /* PIO Mode Bit Mask */
32 MDM = (0x03 << 8), /* Multi-word DMA Mode Bit Mask */
33 UDM = (0x07 << 16), /* Ultra DMA Mode Bit Mask */
80 MODULE_DESCRIPTION("SCSI low-level driver for Intel SCH PATA controllers");
86 * sch_set_piomode - Initialize host controller PATA PIO timings
90 * Set PIO mode for device, in host controller PCI config space.
98 unsigned int pio = adev->pio_mode - XFER_PIO_0; in sch_set_piomode() local
[all …]
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| /kernel/linux/linux-5.10/arch/mips/sgi-ip27/ |
| D | ip27-hubio.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1992-1997, 2000-2003 Silicon Graphics, Inc.
6 * Support functions for the HUB ASIC - mostly PIO mapping related.
22 * hub_pio_map - establish a HUB PIO mapping
24 * @hub: hub to perform PIO mapping on
25 * @widget: widget ID to perform PIO mapping for
27 * @size: size of the PIO mapping
35 /* use small-window mapping if possible */ in hub_pio_map()
40 printk(KERN_WARNING "PIO mapping at hub %d widget %d addr 0x%lx" in hub_pio_map()
46 xtalk_addr &= ~(BWIN_SIZE-1); in hub_pio_map()
[all …]
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| /kernel/linux/linux-6.6/arch/mips/sgi-ip27/ |
| D | ip27-hubio.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1992-1997, 2000-2003 Silicon Graphics, Inc.
6 * Support functions for the HUB ASIC - mostly PIO mapping related.
22 * hub_pio_map - establish a HUB PIO mapping
24 * @hub: hub to perform PIO mapping on
25 * @widget: widget ID to perform PIO mapping for
27 * @size: size of the PIO mapping
35 /* use small-window mapping if possible */ in hub_pio_map()
40 printk(KERN_WARNING "PIO mapping at hub %d widget %d addr 0x%lx" in hub_pio_map()
46 xtalk_addr &= ~(BWIN_SIZE-1); in hub_pio_map()
[all …]
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| /kernel/linux/linux-6.6/drivers/net/wireless/broadcom/b43legacy/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Broadcom 43xx-legacy wireless support (mac80211 stack)"
18 b43-fwcutter.
23 # Auto-select SSB PCI-HOST support, if possible
31 # Auto-select SSB PCICORE driver, if possible
46 # This config option automatically enables b43 HW-RNG support,
47 # if the HW-RNG core is enabled.
54 bool "Broadcom 43xx-legacy debugging"
70 prompt "Broadcom 43xx-legacy data transfer mode"
75 bool "DMA + PIO"
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/broadcom/b43legacy/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Broadcom 43xx-legacy wireless support (mac80211 stack)"
18 b43-fwcutter.
23 # Auto-select SSB PCI-HOST support, if possible
31 # Auto-select SSB PCICORE driver, if possible
46 # This config option automatically enables b43 HW-RNG support,
47 # if the HW-RNG core is enabled.
54 bool "Broadcom 43xx-legacy debugging"
70 prompt "Broadcom 43xx-legacy data transfer mode"
75 bool "DMA + PIO"
[all …]
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