| /kernel/linux/linux-6.6/drivers/media/i2c/ |
| D | ccs-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * drivers/media/i2c/ccs-pll.h
5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
17 /* CSI-2 or CCP-2 */
22 /* op pix clock is for all lanes in total normally */
25 /* CCS PLL flags */
37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39 * A single branch front-end of the CCS PLL tree.
41 * @pre_pll_clk_div: Pre-PLL clock divisor
42 * @pll_multiplier: PLL multiplier
[all …]
|
| D | aptina-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Aptina Sensor PLL Configuration
13 #include "aptina-pll.h"
17 struct aptina_pll *pll) in aptina_pll_calculate() argument
26 dev_dbg(dev, "PLL: ext clock %u pix clock %u\n", in aptina_pll_calculate()
27 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
29 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
30 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
31 dev_err(dev, "pll: invalid external clock frequency.\n"); in aptina_pll_calculate()
32 return -EINVAL; in aptina_pll_calculate()
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | qoriq-clock.txt | 1 * Clock Block on Freescale QorIQ Platforms
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5 multiple phase locked loops (PLL) to create a variety of frequencies
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
[all …]
|
| D | silabs,si5351.txt | 1 Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
5 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
7 The Si5351a/b/c are programmable i2c clock generators with up to 8 output
8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
9 3 output clocks are accessible. The internal structure of the clock
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
[all …]
|
| D | fsl,plldig.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock
10 - Wen He <wen.he_1@nxp.com>
13 NXP LS1028A has a clock domain PXLCLK0 used for the Display output
14 interface in the display core, as implemented in TSMC CLN28HPM PLL.
19 const: fsl,ls1028a-plldig
27 '#clock-cells':
[all …]
|
| D | silabs,si5341.txt | 2 i2c clock generator.
6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
12 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
15 The internal structure of the clock generators can be found in [2].
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | qoriq-clock.txt | 1 * Clock Block on Freescale QorIQ Platforms
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5 multiple phase locked loops (PLL) to create a variety of frequencies
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
[all …]
|
| D | clock-bindings.txt | 1 This binding is a work-in-progress, and are based on some experimental
4 Sources of clock signal can be represented by any node in the device
5 tree. Those nodes are designated as clock providers. Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
7 outputs to clock inputs. Similar to the gpio specifiers, a clock
8 specifier is an array of zero, one or more cells identifying the clock
9 output on a device. The length of a clock specifier is defined by the
10 value of a #clock-cells property in the clock provider node.
14 ==Clock providers==
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
[all …]
|
| D | silabs,si5351.txt | 1 Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
7 The Si5351a/b/c are programmable i2c clock generators with up to 8 output
8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
9 3 output clocks are accessible. The internal structure of the clock
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
20 - reg: i2c device address, shall be 0x60 or 0x61.
[all …]
|
| D | fsl,plldig.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
10 - Wen He <wen.he_1@nxp.com>
13 NXP LS1028A has a clock domain PXLCLK0 used for the Display output
14 interface in the display core, as implemented in TSMC CLN28HPM PLL.
19 const: fsl,ls1028a-plldig
27 '#clock-cells':
[all …]
|
| D | silabs,si5341.txt | 2 i2c clock generator.
6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
12 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
15 The internal structure of the clock generators can be found in [2].
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
34 - compatible: shall be one of the following:
35 "silabs,si5340" - Si5340 A/B/C/D
[all …]
|
| /kernel/linux/linux-6.6/drivers/staging/sm750fb/ |
| D | ddk750_chip.c | 1 // SPDX-License-Identifier: GPL-2.0
52 * This function set up the main chip clock.
54 * Input: Frequency to be set.
56 static void set_chip_clock(unsigned int frequency) in set_chip_clock() argument
58 struct pll_value pll; in set_chip_clock() local
60 /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */ in set_chip_clock()
64 if (frequency) { in set_chip_clock()
66 * Set up PLL structure to hold the value to be set in clocks. in set_chip_clock()
68 pll.input_freq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */ in set_chip_clock()
69 pll.clock_type = MXCLK_PLL; in set_chip_clock()
[all …]
|
| /kernel/linux/linux-5.10/drivers/staging/sm750fb/ |
| D | ddk750_chip.c | 1 // SPDX-License-Identifier: GPL-2.0
52 * This function set up the main chip clock.
54 * Input: Frequency to be set.
56 static void set_chip_clock(unsigned int frequency) in set_chip_clock() argument
58 struct pll_value pll; in set_chip_clock() local
60 /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */ in set_chip_clock()
64 if (frequency) { in set_chip_clock()
66 * Set up PLL structure to hold the value to be set in clocks. in set_chip_clock()
68 pll.input_freq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */ in set_chip_clock()
69 pll.clock_type = MXCLK_PLL; in set_chip_clock()
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/zynq/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Zynq PLL driver
10 #include <linux/clk-provider.h>
15 * struct zynq_pll - pll clock
16 * @hw: Handle between common and hardware-specific interfaces
17 * @pll_ctrl: PLL control register
18 * @pll_status: PLL status register
20 * @lockbit: Indicates the associated PLL_LOCKED bit in the PLL status
45 * zynq_pll_round_rate() - Round a clock frequency
46 * @hw: Handle between common and hardware-specific interfaces
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/zynq/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Zynq PLL driver
10 #include <linux/clk-provider.h>
16 * @hw: Handle between common and hardware-specific interfaces
17 * @pll_ctrl: PLL control register
18 * @pll_status: PLL status register
20 * @lockbit: Indicates the associated PLL_LOCKED bit in the PLL status
45 * zynq_pll_round_rate() - Round a clock frequency
46 * @hw: Handle between common and hardware-specific interfaces
47 * @rate: Desired clock frequency
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/c6x/ |
| D | clocks.txt | 1 C6X PLL Clock Controllers
2 -------------------------
4 This is a first-cut support for the SoC clock controllers. This is still
6 clock support is added to the kernel.
10 - compatible: "ti,c64x+pll"
11 May also have SoC-specific value to support SoC-specific initialization
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/zynqmp/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC PLL driver
5 * Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
16 * @clk_id: PLL clock ID
43 * zynqmp_pll_get_mode() - Get mode of PLL
44 * @hw: Handle between common and hardware-specific interfaces
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/zynqmp/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC PLL driver
5 * Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
16 * @clk_id: PLL clock ID
44 * zynqmp_pll_get_mode() - Get mode of PLL
45 * @hw: Handle between common and hardware-specific interfaces
[all …]
|
| /kernel/linux/linux-5.10/drivers/media/i2c/ |
| D | aptina-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Aptina Sensor PLL Configuration
14 #include "aptina-pll.h"
18 struct aptina_pll *pll) in aptina_pll_calculate() argument
27 dev_dbg(dev, "PLL: ext clock %u pix clock %u\n", in aptina_pll_calculate()
28 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
30 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
31 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
32 dev_err(dev, "pll: invalid external clock frequency.\n"); in aptina_pll_calculate()
33 return -EINVAL; in aptina_pll_calculate()
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/analogbits/ |
| D | wrpll-cln28hpc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
8 * the CLN28HPC variant of the Analog Bits Wide Range PLL. The
10 * integrates this PLL; thus the register structure and programming
13 * The bulk of this code is primarily useful for clock configurations
14 * that must operate at arbitrary rates, as opposed to clock configurations
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/analogbits/ |
| D | wrpll-cln28hpc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
8 * the CLN28HPC variant of the Analog Bits Wide Range PLL. The
10 * integrates this PLL; thus the register structure and programming
13 * The bulk of this code is primarily useful for clock configurations
14 * that must operate at arbitrary rates, as opposed to clock configurations
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
76 * @rate: input frequency from source
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/tegra/ |
| D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
76 * @rate: input frequency from source
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/bcm/ |
| D | clk-iproc.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
17 #define bit_mask(width) ((1 << (width)) - 1)
22 /* PLL that requires gating through ASIU */
25 /* PLL that has fractional part of the NDIV */
29 * Some of the iProc PLL/clocks may have an ASIC bug that requires read back
36 * Some PLLs require the PLL SW override bit to be set before changes can be
37 * applied to the PLL
42 * Some PLLs use a different way to control clock power, via the PWRDWN bit in
43 * the PLL control register
[all …]
|
| /kernel/linux/linux-5.10/drivers/iio/frequency/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Frequency
5 # Clock Distribution device drivers
6 # Phase-Locked Loop (PLL) frequency synthesizers
10 menu "Frequency Synthesizers DDS/PLL"
12 menu "Clock Generator/Distribution"
15 tristate "Analog Devices AD9523 Low Jitter Clock Generator"
19 Clock Generator. The driver provides direct access via sysfs.
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
|