Home
last modified time | relevance | path

Searched +full:port +full:- +full:base (Results 1 – 25 of 1111) sorted by relevance

12345678910>>...45

/kernel/linux/linux-5.10/drivers/tty/
Disicom.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Original driver code supplied by Multi-Tech
13 * Rough port to 2.1.x
25 * dumps the Port Count information
32 * when the last port on the card is
52 * ISIHP-4X card
55 * ISI port problem. Now the link
60 * among ISI-PCI cards.
89 * 06/01/05 Alan Cox Merged the ISI and base kernel strands
99 * ftp://ftp.multitech.com/ISI-Cards/
[all …]
/kernel/linux/linux-5.10/drivers/gpio/
Dgpio-ws16c48.c1 // SPDX-License-Identifier: GPL-2.0-only
24 static unsigned int base[MAX_NUM_WS16C48]; variable
26 module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
27 MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
34 * struct ws16c48_gpio - GPIO device private data structure
41 * @base: base port address of the GPIO device
50 unsigned base; member
56 const unsigned port = offset / 8; in ws16c48_gpio_get_direction() local
59 if (ws16c48gpio->io_state[port] & mask) in ws16c48_gpio_get_direction()
68 const unsigned port = offset / 8; in ws16c48_gpio_direction_input() local
[all …]
Dgpio-gpio-mm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the Diamond Systems GPIO-MM
6 * This driver supports the following Diamond Systems devices: GPIO-MM and
7 * GPIO-MM-12.
25 static unsigned int base[MAX_NUM_GPIOMM]; variable
27 module_param_hw_array(base, uint, ioport, &num_gpiomm, 0);
28 MODULE_PARM_DESC(base, "Diamond Systems GPIO-MM base addresses");
31 * struct gpiomm_gpio - GPIO device private data structure
37 * @base: base port address of the GPIO device
45 unsigned int base; member
[all …]
Dgpio-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
7 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
26 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
27 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
28 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
29 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
30 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
31 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
32 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
33 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
[all …]
Dgpio-mxc.c1 // SPDX-License-Identifier: GPL-2.0+
8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
61 void __iomem *base; member
81 .edge_sel_reg = -EINVAL,
96 .edge_sel_reg = -EINVAL,
121 #define GPIO_DR (mxc_gpio_hwdata->dr_reg)
122 #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
123 #define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
124 #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
125 #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
[all …]
Dgpio-104-dio-48e.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES 104-DIO-48E series
6 * This driver supports the following ACCES devices: 104-DIO-48E and
7 * 104-DIO-24E.
27 static unsigned int base[MAX_NUM_DIO48E]; variable
29 module_param_hw_array(base, uint, ioport, &num_dio48e, 0);
30 MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
34 MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
37 * struct dio48e_gpio - GPIO device private data structure
43 * @base: base port address of the GPIO device
[all …]
Dgpio-tegra186.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2017 NVIDIA Corporation
15 #include <dt-bindings/gpio/tegra186-gpio.h>
16 #include <dt-bindings/gpio/tegra194-gpio.h>
57 unsigned int port; member
86 void __iomem *base; member
94 for (i = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_get_port()
95 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_get_port() local
97 if (*pin >= start && *pin < start + port->pins) { in tegra186_gpio_get_port()
98 *pin -= start; in tegra186_gpio_get_port()
[all …]
Dgpio-vf610.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale vf610 GPIO support through PORT and GPIO
26 /* SoCs has a Port Data Direction Register (PDDR) */
33 void __iomem *base; member
69 { .compatible = "fsl,vf610-gpio", .data = NULL, },
70 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
86 struct vf610_gpio_port *port = gpiochip_get_data(gc); in vf610_gpio_get() local
90 if (port->sdata && port->sdata->have_paddr) { in vf610_gpio_get()
91 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR); in vf610_gpio_get()
96 return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio)); in vf610_gpio_get()
[all …]
/kernel/linux/linux-5.10/drivers/pci/controller/
Dpcie-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
36 /* PCIe per port registers */
72 /* PCIe V2 per-port registers */
125 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
143 * struct mtk_pcie_soc - differentiate between host generations
156 int (*startup)(struct mtk_pcie_port *port);
157 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
161 * struct mtk_pcie_port - PCIe port information
162 * @base: IO mapped register base
163 * @list: port list
[all …]
/kernel/linux/linux-6.6/drivers/pci/controller/
Dpcie-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
38 /* PCIe per port registers */
74 /* PCIe V2 per-port registers */
127 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
145 * struct mtk_pcie_soc - differentiate between host generations
160 int (*startup)(struct mtk_pcie_port *port);
161 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
165 * struct mtk_pcie_port - PCIe port information
166 * @base: IO mapped register base
167 * @list: port list
[all …]
Dpcie-apple.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host bridge driver for Apple system-on-chips.
6 * the driver mostly deals MSI mapping and handling of per-port
31 #include <linux/pci-ecam.h>
43 #define CORE_LANE_CFG(port) (0x84000 + 0x4000 * (port)) argument
49 #define CORE_LANE_CTL(port) (0x84004 + 0x4000 * (port)) argument
127 * address (in the bottom 4GB, as the base register is only 32bit).
136 void __iomem *base; member
148 void __iomem *base; member
189 msg->address_hi = upper_32_bits(DOORBELL_ADDR); in apple_msi_compose_msg()
[all …]
Dpcie-mt7621.c1 // SPDX-License-Identifier: GPL-2.0+
35 /* MediaTek-specific configuration registers */
40 /* Host-PCI bridge registers */
67 * struct mt7621_pcie_port - PCIe port information
68 * @base: I/O mapped register base
69 * @list: port list
71 * @clk: pointer to the port clock gate
73 * @pcie_rst: pointer to port reset control
75 * @slot: port slot
76 * @enabled: indicates if port is enabled
[all …]
/kernel/linux/linux-6.6/drivers/gpio/
Dgpio-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
7 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
25 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
26 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
27 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
28 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
29 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
30 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
31 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
32 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
[all …]
Dgpio-mxc.c1 // SPDX-License-Identifier: GPL-2.0+
8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
61 void __iomem *base; member
86 .edge_sel_reg = -EINVAL,
101 .edge_sel_reg = -EINVAL,
123 #define GPIO_DR (port->hwdata->dr_reg)
124 #define GPIO_GDIR (port->hwdata->gdir_reg)
125 #define GPIO_PSR (port->hwdata->psr_reg)
126 #define GPIO_ICR1 (port->hwdata->icr1_reg)
127 #define GPIO_ICR2 (port->hwdata->icr2_reg)
[all …]
Dgpio-gpio-mm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the Diamond Systems GPIO-MM
6 * This driver supports the following Diamond Systems devices: GPIO-MM and
7 * GPIO-MM-12.
19 #include "gpio-i8255.h"
26 static unsigned int base[MAX_NUM_GPIOMM]; variable
28 module_param_hw_array(base, uint, ioport, &num_gpiomm, 0);
29 MODULE_PARM_DESC(base, "Diamond Systems GPIO-MM base addresses");
52 "Port 1A0", "Port 1A1", "Port 1A2", "Port 1A3", "Port 1A4", "Port 1A5",
53 "Port 1A6", "Port 1A7", "Port 1B0", "Port 1B1", "Port 1B2", "Port 1B3",
[all …]
Dgpio-vf610.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale vf610 GPIO support through PORT and GPIO
26 /* SoCs has a Port Data Direction Register (PDDR) */
32 void __iomem *base; member
68 { .compatible = "fsl,vf610-gpio", .data = NULL, },
69 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
85 struct vf610_gpio_port *port = gpiochip_get_data(gc); in vf610_gpio_get() local
89 if (port->sdata && port->sdata->have_paddr) { in vf610_gpio_get()
90 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR); in vf610_gpio_get()
95 return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio)); in vf610_gpio_get()
[all …]
/kernel/linux/linux-5.10/drivers/phy/tegra/
Dxusb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
17 /* legacy entry points for backwards-compatibility */
53 struct tegra_xusb_lane base; member
59 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
63 struct tegra_xusb_lane base; member
72 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
76 struct tegra_xusb_lane base; member
82 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
86 struct tegra_xusb_lane base; member
[all …]
Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
[all …]
/kernel/linux/linux-6.6/drivers/hwtracing/intel_th/
Dgth.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Intel Corporation.
25 * struct gth_output - GTH view on an output port
28 * @index: output port number
29 * @port_type: one of GTH_* port type values
41 * struct gth_device - GTH device
43 * @base: register window base address
47 * @master: master/output port assignments
52 void __iomem *base; member
61 static void gth_output_set(struct gth_device *gth, int port, in gth_output_set() argument
[all …]
/kernel/linux/linux-5.10/drivers/hwtracing/intel_th/
Dgth.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Intel Corporation.
25 * struct gth_output - GTH view on an output port
28 * @index: output port number
29 * @port_type: one of GTH_* port type values
41 * struct gth_device - GTH device
43 * @base: register window base address
47 * @master: master/output port assignments
52 void __iomem *base; member
61 static void gth_output_set(struct gth_device *gth, int port, in gth_output_set() argument
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
Dintel_ddi.c96 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level()
98 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
114 * Starting with Haswell, DDI port buffers must be programmed with correct
121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers()
124 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers() local
127 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
128 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
133 intel_bios_dp_boost_level(encoder->devdata)) in hsw_prepare_dp_ddi_buffers()
137 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), in hsw_prepare_dp_ddi_buffers()
138 trans->entries[i].hsw.trans1 | iboost_bit); in hsw_prepare_dp_ddi_buffers()
[all …]
/kernel/linux/linux-6.6/drivers/phy/tegra/
Dxusb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
19 /* legacy entry points for backwards-compatibility */
59 struct tegra_xusb_lane base; member
65 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
69 struct tegra_xusb_lane base; member
78 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
82 struct tegra_xusb_lane base; member
88 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
92 struct tegra_xusb_lane base; member
[all …]
Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/ibm/ehea/
Dehea_ethtool.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * Jan-Bernd Themann <themann@de.ibm.com>
23 struct ehea_port *port = netdev_priv(dev); in ehea_get_link_ksettings() local
28 ret = ehea_sense_port_attr(port); in ehea_get_link_ksettings()
34 switch (port->port_speed) { in ehea_get_link_ksettings()
48 speed = -1; in ehea_get_link_ksettings()
51 cmd->base.duplex = port->full_duplex == 1 ? in ehea_get_link_ksettings()
55 cmd->base.duplex = DUPLEX_UNKNOWN; in ehea_get_link_ksettings()
57 cmd->base.speed = speed; in ehea_get_link_ksettings()
59 if (cmd->base.speed == SPEED_10000) { in ehea_get_link_ksettings()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/ibm/ehea/
Dehea_ethtool.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * Jan-Bernd Themann <themann@de.ibm.com>
23 struct ehea_port *port = netdev_priv(dev); in ehea_get_link_ksettings() local
28 ret = ehea_sense_port_attr(port); in ehea_get_link_ksettings()
34 switch (port->port_speed) { in ehea_get_link_ksettings()
48 speed = -1; in ehea_get_link_ksettings()
51 cmd->base.duplex = port->full_duplex == 1 ? in ehea_get_link_ksettings()
55 cmd->base.duplex = DUPLEX_UNKNOWN; in ehea_get_link_ksettings()
57 cmd->base.speed = speed; in ehea_get_link_ksettings()
59 if (cmd->base.speed == SPEED_10000) { in ehea_get_link_ksettings()
[all …]

12345678910>>...45