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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/frequency/
Dadi,admv1013.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1013
26 spi-max-frequency:
34 clock-names:
36 - const: lo_in
38 vcm-supply:
42 vcc-drv-supply:
[all …]
Dadi,admv1014.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1014
26 spi-max-frequency:
32 clock-names:
34 - const: lo_in
38 vcm-supply:
40 Common-mode voltage regulator.
[all …]
/kernel/linux/linux-6.6/drivers/counter/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
31 tristate "ACCES 104-QUAD-8 driver"
37 Say yes here to build support for the ACCES 104-QUAD-8 quadrature
38 encoder counter/interface device family (104-QUAD-8, 104-QUAD-4).
41 operation on the respective count value attribute. The 104-QUAD-8
58 module will be called ftm-quaddec.
69 will be called intel-qep.
79 module will be called interrupt-cnt.
91 module will be called microchip-tcb-capture.
98 SoCs. This IP supports both 16-bit and 32-bit phase counting mode
[all …]
Dftm-quaddec.c1 // SPDX-License-Identifier: GPL-2.0
37 if (ftm->big_endian) in ftm_read()
38 *data = ioread32be(ftm->ftm_base + offset); in ftm_read()
40 *data = ioread32(ftm->ftm_base + offset); in ftm_read()
45 if (ftm->big_endian) in ftm_write()
46 iowrite32be(data, ftm->ftm_base + offset); in ftm_write()
48 iowrite32(data, ftm->ftm_base + offset); in ftm_write()
90 /* Select quad mode, reset other fields to zero */ in ftm_quaddec_init()
135 mutex_lock(&ftm->ftm_quaddec_mutex); in ftm_quaddec_set_prescaler()
144 mutex_unlock(&ftm->ftm_quaddec_mutex); in ftm_quaddec_set_prescaler()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/regulator/
Ddlg,da9121.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adam Ward <Adam.Ward.opensource@diasemi.com>
13 Dialog Semiconductor DA9121 Single-channel 10A double-phase buck converter
14 Dialog Semiconductor DA9122 Double-channel 5A single-phase buck converter
15 Dialog Semiconductor DA9220 Double-channel 3A single-phase buck converter
16 Dialog Semiconductor DA9217 Single-channel 6A double-phase buck converter
17 Dialog Semiconductor DA9130 Single-channel 10A double-phase buck converter
18 Dialog Semiconductor DA9131 Double-channel 5A single-phase buck converter
[all …]
/kernel/linux/linux-5.10/drivers/mtd/spi-nor/
Dsfdp.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 #define BFPT_DWORD(i) ((i) - 1)
56 * Quad Enable Requirements (QER):
57 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
59 * instruction phase.
60 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
63 * Writing only one byte to the status register has the side-effect of
67 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
70 * - 011b: QE is bit 7 of status register 2. It is set via Write status
74 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
[all …]
/kernel/linux/linux-5.10/drivers/counter/
Dftm-quaddec.c1 // SPDX-License-Identifier: GPL-2.0
37 if (ftm->big_endian) in ftm_read()
38 *data = ioread32be(ftm->ftm_base + offset); in ftm_read()
40 *data = ioread32(ftm->ftm_base + offset); in ftm_read()
45 if (ftm->big_endian) in ftm_write()
46 iowrite32be(data, ftm->ftm_base + offset); in ftm_write()
48 iowrite32(data, ftm->ftm_base + offset); in ftm_write()
90 /* Select quad mode, reset other fields to zero */ in ftm_quaddec_init()
121 struct ftm_quaddec *ftm = counter->priv; in ftm_quaddec_get_prescaler()
135 struct ftm_quaddec *ftm = counter->priv; in ftm_quaddec_set_prescaler()
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/kernel/linux/linux-6.6/drivers/mtd/spi-nor/
Dsfdp.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define SFDP_DWORD(i) ((i) - 1)
56 * Quad Enable Requirements (QER):
57 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
59 * instruction phase.
60 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
63 * Writing only one byte to the status register has the side-effect of
67 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
70 * - 011b: QE is bit 7 of status register 2. It is set via Write status
74 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
[all …]
Dcore.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mtd/spi-nor.h>
30 * For everything but full-chip erase; probably could be much smaller, but kept
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
60 switch (nor->cmd_ext_type) { in spi_nor_get_cmd_ext()
62 return ~op->cmd.opcode; in spi_nor_get_cmd_ext()
65 return op->cmd.opcode; in spi_nor_get_cmd_ext()
68 dev_err(nor->dev, "Unknown command extension type\n"); in spi_nor_get_cmd_ext()
74 * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op.
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/kernel/linux/linux-6.6/drivers/net/ethernet/intel/ice/
Dice_ptp.c1 // SPDX-License-Identifier: GPL-2.0
116 return -EINVAL; in ice_ptp_set_sma_config_e810t()
121 return -EINVAL; in ice_ptp_set_sma_config_e810t()
193 struct ice_hw *hw = &pf->hw; in ice_ptp_set_sma_e810t()
197 return -EOPNOTSUPP; in ice_ptp_set_sma_e810t()
237 return -EOPNOTSUPP; in ice_verify_pin_e810t()
245 return -EOPNOTSUPP; in ice_verify_pin_e810t()
249 return -EOPNOTSUPP; in ice_verify_pin_e810t()
252 return -EOPNOTSUPP; in ice_verify_pin_e810t()
259 * ice_set_tx_tstamp - Enable or disable Tx timestamping
[all …]
/kernel/linux/linux-5.10/drivers/spi/
Dspi-falcon.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #define DRV_NAME "sflash-falcon"
43 /* Dummy Phase Length */
52 /* SCK Rise-edge Position */
58 /* SCK Fall-edge Position */
82 /* 8-bit multiplexed */
100 struct device *dev = &spi->dev; in falcon_sflash_xfer()
101 struct falcon_sflash *priv = spi_master_get_devdata(spi->master); in falcon_sflash_xfer()
102 const u8 *txp = t->tx_buf; in falcon_sflash_xfer()
103 u8 *rxp = t->rx_buf; in falcon_sflash_xfer()
[all …]
Dspi-xilinx.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * 2002-2007 (c) MontaVista Software, Inc.
56 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
120 if (!xspi->tx_ptr) { in xilinx_spi_tx()
121 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); in xilinx_spi_tx()
125 switch (xspi->bytes_per_word) { in xilinx_spi_tx()
127 data = *(u8 *)(xspi->tx_ptr); in xilinx_spi_tx()
130 data = *(u16 *)(xspi->tx_ptr); in xilinx_spi_tx()
133 data = *(u32 *)(xspi->tx_ptr); in xilinx_spi_tx()
137 xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET); in xilinx_spi_tx()
[all …]
Dspi-rspi.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on spi-sh.c:
21 #include <linux/dma-mapping.h>
40 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
68 /* SPCR - Control Register */
77 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
78 /* QSPI on R-Car Gen2 only */
79 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
80 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
82 /* SSLP - Slave Select Polarity Register */
[all …]
Dspi-zynqmp-gqspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
24 #include <linux/spi/spi-mem.h>
119 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
141 * struct zynqmp_qspi - Defines qspi driver instance
181 * zynqmp_gqspi_read - For GQSPI controller read operation
188 return readl_relaxed(xqspi->regs + offset); in zynqmp_gqspi_read()
[all …]
/kernel/linux/linux-6.6/drivers/spi/
Dspi-falcon.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #define DRV_NAME "sflash-falcon"
43 /* Dummy Phase Length */
52 /* SCK Rise-edge Position */
58 /* SCK Fall-edge Position */
82 /* 8-bit multiplexed */
100 struct device *dev = &spi->dev; in falcon_sflash_xfer()
101 struct falcon_sflash *priv = spi_controller_get_devdata(spi->controller); in falcon_sflash_xfer()
102 const u8 *txp = t->tx_buf; in falcon_sflash_xfer()
103 u8 *rxp = t->rx_buf; in falcon_sflash_xfer()
[all …]
Dspi-xilinx.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * 2002-2007 (c) MontaVista Software, Inc.
56 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
120 if (!xspi->tx_ptr) { in xilinx_spi_tx()
121 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); in xilinx_spi_tx()
125 switch (xspi->bytes_per_word) { in xilinx_spi_tx()
127 data = *(u8 *)(xspi->tx_ptr); in xilinx_spi_tx()
130 data = *(u16 *)(xspi->tx_ptr); in xilinx_spi_tx()
133 data = *(u32 *)(xspi->tx_ptr); in xilinx_spi_tx()
137 xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET); in xilinx_spi_tx()
[all …]
Dspi-rspi.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on spi-sh.c:
21 #include <linux/dma-mapping.h>
41 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
69 /* SPCR - Control Register */
78 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
79 /* QSPI on R-Car Gen2 only */
80 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
81 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
83 /* SSLP - Slave Select Polarity Register */
[all …]
Dspi-zynqmp-gqspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
23 #include <linux/spi/spi-mem.h>
120 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
161 * struct qspi_platform_data - zynqmp qspi platform data structure
169 * struct zynqmp_qspi - Defines qspi driver instance
215 * zynqmp_gqspi_read - For GQSPI controller read operation
[all …]
/kernel/linux/linux-5.10/tools/spi/
Dspidev_test.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
71 while (length-- > 0) { in hex_dump()
91 * Unescape - process hexadecimal escape character
92 * converts shell input "\x23" -> 0x23
175 printf("Usage: %s [-DsbdlHOLC3vpNR24SI]\n", prog); in print_usage()
176 puts(" -D --device device to use (default /dev/spidev1.1)\n" in print_usage()
177 " -s --speed max speed (Hz)\n" in print_usage()
178 " -d --delay delay (usec)\n" in print_usage()
179 " -b --bpw bits per word\n" in print_usage()
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/kernel/linux/linux-5.10/Documentation/hwmon/
Dltc2978.rst10 Addresses scanned: -
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/kernel/linux/linux-6.6/Documentation/hwmon/
Dltc2978.rst10 Addresses scanned: -
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/kernel/linux/linux-6.6/tools/spi/
Dspidev_test.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
71 while (length-- > 0) { in hex_dump()
91 * Unescape - process hexadecimal escape character
92 * converts shell input "\x23" -> 0x23
175 printf("Usage: %s [-2348CDFHILMNORSZbdilopsv]\n", prog); in print_usage()
177 " -D --device device to use (default /dev/spidev1.1)\n" in print_usage()
178 " -s --speed max speed (Hz)\n" in print_usage()
179 " -d --delay delay (usec)\n" in print_usage()
180 " -l --loop loopback\n" in print_usage()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/
Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
28 - enum:
29 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
30 - ad,ad7414
31 # ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
32 - ad,adm9240
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/kernel/linux/linux-6.6/drivers/usb/gadget/udc/cdns2/
Dcdns2-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * USBHS-DEV device controller driver header file
14 #include <linux/dma-direction.h>
22 * struct cdns2_ep0_regs - endpoint 0 related registers.
45 /* EP0CS - bitmasks. */
54 /* Send STALL in the data stage phase. */
59 /* EP0FIFO - bitmasks. */
70 * struct cdns2_epx_base - base endpoint registers.
87 /* rxcon/txcon - endpoint control register bitmasks. */
88 /* Endpoint buffering: 0 - single buffering ... 3 - quad buffering. */
[all …]
/kernel/linux/linux-5.10/arch/x86/crypto/
Daesni-intel_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Implement AES algorithm in Intel AES-NI instructions.
5 * The white paper of AES-NI instructions can be downloaded from:
6 * http://softwarecommunity.intel.com/isn/downloads/intelavx/AES-Instructions-Set_WP.pdf
13 * Added RFC4106 AES-GCM support for 128-bit keys under the AEAD
14 * interface for 64-bit kernels.
30 #include <asm/nospec-branch.h>
35 * movaps (move aligned packed single) or integer use movdqa (move double quad
252 # Clobbers rax, r10-r13 and xmm0-xmm6, %xmm13
278 # Clobbers rax, r10-r13, and xmm0-xmm15
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