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/third_party/mesa3d/.gitlab-ci/
Drun-shader-db.sh4 set -e
6 . "${SCRIPTS_DIR}/setup-test-env.sh"
8 ARTIFACTSDIR=$(pwd)/shader-db
9 mkdir -p "$ARTIFACTSDIR"
15 cd /usr/local/shader-db
18 section_start shader-db-${driver} "Running shader-db for $driver"
20 ./run -j"${FDO_CI_CONCURRENT:-4}" ./shaders \
21 > "$ARTIFACTSDIR/${driver}-shader-db.txt"
22 section_end shader-db-${driver}
25 # Run shader-db over a number of supported chipsets for nouveau
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/third_party/mesa3d/.gitlab-ci/container/
Dbuild-shader-db.sh4 # .gitlab-ci/image-tags.yml tags:
7 set -ex
9 uncollapsed_section_start shader-db "Building shader-db"
12 git clone https://gitlab.freedesktop.org/mesa/shader-db.git --depth 1
13 rm -rf shader-db/.git
14 cd shader-db
18 section_end shader-db
/third_party/mesa3d/src/gallium/drivers/zink/
Dzink_descriptors.c67 VKSCR(GetDescriptorSetLayoutSupport)(screen->dev, &dcslci, &supp); in descriptor_layout_create()
73 VkResult result = VKSCR(CreateDescriptorSetLayout)(screen->dev, &dcslci, 0, &dsl); in descriptor_layout_create()
84 hash = XXH32(&k->num_bindings, sizeof(unsigned), hash); in hash_descriptor_layout()
86 for (unsigned i = 0; i < k->num_bindings; i++) in hash_descriptor_layout()
87 hash = XXH32(&k->bindings[i], offsetof(VkDescriptorSetLayoutBinding, stageFlags), hash); in hash_descriptor_layout()
97 return a_k->num_bindings == b_k->num_bindings && in equals_descriptor_layout()
98 …(!a_k->num_bindings || !memcmp(a_k->bindings, b_k->bindings, a_k->num_bindings * sizeof(VkDescript… in equals_descriptor_layout()
112 k->num_bindings = num_bindings; in create_layout()
114 k->bindings = (void *)(k + 1); in create_layout()
115 memcpy(k->bindings, bindings, bindings_size); in create_layout()
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Dzink_context.c17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
72 if (ctx->track_renderpasses) { in update_tc_info()
73 const struct tc_renderpass_info *info = threaded_context_get_renderpass_info(ctx->tc); in update_tc_info()
74 ctx->rp_changed |= ctx->dynamic_fb.tc_info.data != info->data; in update_tc_info()
75 ctx->dynamic_fb.tc_info.data = info->data; in update_tc_info()
77 struct tc_renderpass_info info = ctx->dynamic_fb.tc_info; in update_tc_info()
78 bool zsbuf_used = !ctx->zsbuf_unused; in update_tc_info()
80 ctx->dynamic_fb.tc_info.data32[0] = 0; in update_tc_info()
81 if (ctx->clears_enabled & PIPE_CLEAR_DEPTHSTENCIL) in update_tc_info()
82 ctx->dynamic_fb.tc_info.zsbuf_clear_partial = true; in update_tc_info()
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/third_party/mesa3d/src/broadcom/common/
Dv3d_debug.c57 /* `shaderdb` is *not* used by shader-db, but is here so that any other
58 * game/app can dump its stats in the shader-db format, allowing them
59 * to be compared using shader-db's report.py tool.
62 "Dump program compile information for shader-db analysis" },
67 "Print performance-related events during runtime" },
82 "Precompiles shader variant at shader state creation time (v3d only)" },
86 "Force 32-bit precision on all TMU operations" },
88 * require full 32-bit precision, but can improve performance
92 "Force 16-bit precision on all TMU operations" },
95 { "db", V3D_DEBUG_DOUBLE_BUFFER,
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/third_party/mesa3d/docs/drivers/panfrost/
Ddrm-shim.rst2 drm-shim
5 Panfrost implements ``drm-shim``, stubbing out the Panfrost kernel interface.
8 - Future hardware bring up
9 - Running shader-db on non-Mali workstations
10 - Reproducing compiler (and some driver) bugs without Mali hardware
14 compiler on shader-db on an Intel desktop.
16 To build Mesa with Panfrost drm-shim, configure Meson with
17 ``-Dgallium-drivers=panfrost`` and ``-Dtools=drm-shim``. See the above
18 building section for a full invocation. The drm-shim binary will be built to
19 ``build/src/panfrost/drm-shim/libpanfrost_noop_drm_shim.so``.
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/third_party/mesa3d/src/broadcom/drm-shim/
DREADME.md3 This implements the minimum of v3d in order to make shader-db work.
12 This implements the minimum of vc4 in order to make shader-db work.
/third_party/mesa3d/docs/relnotes/
D24.2.6.rst1 Mesa 24.2.6 Release Notes / 2024-10-30
18 -------------
22 SHA256: 2b68c4a6f204c1999815a457299f81c41ba7bf48c4674b0b2d1d8864f41f3709 mesa-24.2.6.tar.xz
23 …5007d138079e1fafb3568f658e777e7894e95b5ce75d2bd6836b0473fa70d32270005e482b1a2da mesa-24.2.6.tar.xz
27 ------------
29 - None
33 ---------
35 - radv: wrong index value in radv_skip_graphics_pipeline_compile
36 - Disk Cache DB file descriptors are not closed on exec
37 - Shader cache takes too many fds
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/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_debug_options.h4 OPT_BOOL(dump_shader_binary, false, "Dump shader binary as part of ddebug_dumps")
6 "Report shader disassembly as part of driver debug messages (for shader db)")
12 OPT_BOOL(vrs2x2, false, "Enable 2x2 coarse shading for non-GUI elements")
19 OPT_BOOL(dcc_msaa, true, "Enable DCC for MSAA for GFX10-10.3")
22 OPT_BOOL(cache_rb_gl2, false, "Enable GL2 caching for CB and DB.")
Dsi_barrier.c4 * SPDX-License-Identifier: MIT
12 struct si_screen *sscreen = ctx->screen; in si_get_wait_mem_scratch_bo()
14 assert(ctx->gfx_level < GFX11); in si_get_wait_mem_scratch_bo()
17 return ctx->wait_mem_scratch; in si_get_wait_mem_scratch_bo()
19 assert(sscreen->info.has_tmz_support); in si_get_wait_mem_scratch_bo()
20 if (!ctx->wait_mem_scratch_tmz) { in si_get_wait_mem_scratch_bo()
21 ctx->wait_mem_scratch_tmz = in si_get_wait_mem_scratch_bo()
22 si_aligned_buffer_create(&sscreen->b, in si_get_wait_mem_scratch_bo()
27 sscreen->info.tcc_cache_line_size); in si_get_wait_mem_scratch_bo()
28 si_cp_write_data(ctx, ctx->wait_mem_scratch_tmz, 0, 4, V_370_MEM, V_370_ME, in si_get_wait_mem_scratch_bo()
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/third_party/mesa3d/src/amd/common/
Dgfx10_format_table.py4 # SPDX-License-Identifier: MIT
23 # ----------------------------------------------------------------------------
24 # Hard-coded mappings
85 # ----------------------------------------------------------------------------
90 // DO NOT EDIT -- AUTOMATICALLY GENERATED
115 RE_plain_channel = re.compile(r'X?([0-9]+)')
129 # Keep the bit sizes in little-endian order
172 # Shader-based work-around for 32-bit non-pure-integer
184 # Shader-based work-around for 32-bit non-pure-integer
196 # Shader-based work-around for doubles
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/third_party/mesa3d/docs/
Dshading.rst10 ---------------------
12 The **MESA_GLSL** environment variable can be set to a comma-separated
13 list of keywords to control some aspects of the GLSL compiler and shader
16 - **dump** - print GLSL shader code, IR, and NIR to stdout at link time
17 - **source** - print GLSL shader code to stdout at link time
18 - **log** - log all GLSL shaders to files. The filenames will be
19 "shader_X.vert" or "shader_X.frag" where X the shader ID.
20 - **cache_info** - print debug information about shader cache
21 - **cache_fb** - force cached shaders to be ignored and do a full
23 - **uniform** - print message to stdout when glUniform is called
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Denvvars.rst6 but they can sometimes be useful for debugging end-user issues.
9 ---------------------------
42 - using a VK driver which has no WSI implementation for your display server
43 - profiling the DRI frontend against your VK driver's WSI implementation
50 - running xrdp
51 - using a VK driver which doesn't support modifiers
54 -------------------------------
69 following comma-separated list of named flags, which adds extra
99 ``GL_EXT_foo -GL_EXT_bar`` will enable the ``GL_EXT_foo`` extension
107 or before year X will be reported. This is to work-around a bug in
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/third_party/mesa3d/docs/drivers/
Dvc4.rst7 option as of the 2016-02-09 Raspbian release using ``raspi-config``.
19 -------------
25 --------------
30 * 4-byte index buffers.
59 front/back mode don't match, we would need to run the vertex shader in
65 -------------
68 <https://gitlab.freedesktop.org/mesa/mesa/-/issues>`__ page.
80 useful. Install `vc4-gpu-tools
81 <https://github.com/anholt/vc4-gpu-tools/>`__ and use
82 ``vc4_dump_hang_state my-app.hang``. Sometimes the hang file will
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/third_party/mesa3d/src/gallium/drivers/freedreno/ir3/
Dir3_cache.h3 * SPDX-License-Identifier: MIT
19 * An in-memory cache for mapping shader state objects plus shader key to
20 * hw specific state object for the specified shader variant. This is to
21 * allow re-using things like the register setup for varying linkage, etc.
30 * not the compiled shader:
36 /* per-gen backend program state object should subclass this for it's
55 /* construct a shader cache. Free with ralloc_free() */
60 /* debug callback is used for shader-db logs in case the lookup triggers
61 * shader variant compilation.
Dir3_gallium.c3 * SPDX-License-Identifier: MIT
31 * The hardware cso for shader state
37 struct ir3_shader *shader; member
46 * The only case where util_debug_message() is used in the initial-variants
49 * compile the initial shader variant asynchronously.
54 return unlikely(ctx->debug.debug_message) || FD_DBG(SHADERDB) || in initial_variants_synchronous()
67 "%s shader: %u inst, %u nops, %u non-nops, %u mov, %u cov, " in dump_shader_info()
68 "%u dwords, %u last-baryf, %u last-helper, %u half, %u full, %u constlen, " in dump_shader_info()
71 "%d loops, %u preamble inst, %d early-preamble\n", in dump_shader_info()
72 ir3_shader_stage(v), v->info.instrs_count, v->info.nops_count, in dump_shader_info()
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/third_party/mesa3d/src/gallium/drivers/iris/
Diris_indirect_gen.c2 * SPDX-License-Identifier: MIT
115 screen->vtbl.load_shader_lib_spv = load_shader_lib_spv; in genX()
116 screen->vtbl.call_generation_shader = iris_call_generation_shader; in genX()
120 * Stream out temporary/short-lived state.
123 * returned offset (which works because all state lives in 32-bit memory
134 u_upload_alloc(uploader, 0, size, alignment, &ref->offset, &ref->res, &p); in upload_state()
135 iris_use_pinned_bo(batch, iris_resource_bo(ref->res), false, IRIS_DOMAIN_NONE); in upload_state()
154 iris_record_state_size(batch->state_sizes, in stream_state()
155 bo->address + *out_offset, size); in stream_state()
168 struct iris_screen *screen = batch->screen; in emit_indirect_generate_draw()
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/third_party/mesa3d/src/intel/tools/
DREADME.md26 is useful to test compiler changes (using shader-db/fossils-db
32 $ intel_stub_gpu -p dg2 fossilize-replay /path/to/fossilize.foz --enable-pipeline-stats /tmp/dg2.csv
37 $ intel_stub_gpu -p icl fossilize-replay /path/to/fossilize.foz --enable-pipeline-stats /tmp/icl.csv
43 uncompressed/easy-to-modify binary file (format described in
70 $ ./src/intel/tools/intel_hang_replay -d /tmp/error.dmp
84 ./src/intel/tools/intel_hang_viewer -p dg2 /tmp/error.dmp
90 ./src/intel/tools/intel_hang_viewer -e -p dg2 /tmp/error.dmp
/third_party/mesa3d/src/etnaviv/drm-shim/
DREADME.md3 This implements the minimum of etnaviv in order to make shader-db work.
13 - GC2000 (default)
14 - GC3000
15 - GC7000L
/third_party/mesa3d/src/freedreno/drm-shim/
DREADME.md3 This implements the minimum of msm in order to make shader-db work.
/third_party/mesa3d/src/util/
Dfossilize_db.c24 /* This is a basic c implementation of a fossilize db like format intended for
25 * use with the Mesa shader cache.
27 * The format is compatible enough to allow the fossilize db tools to be used
28 * to do things like merge db collections.
52 #include "mesa-sha1.h"
65 * makes collisions virtually impossible for our use case. However the foz db
76 shift--; in truncate_hash_to_64bits()
105 if (asprintf(filename, "%s/%s.foz", cache_path, name) == -1) in create_foz_db_filenames()
108 if (asprintf(idx_filename, "%s/%s_idx.foz", cache_path, name) == -1) { in create_foz_db_filenames()
152 if (offset + header->payload_size > len || in update_foz_index()
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/third_party/mesa3d/src/amd/drm-shim/
DREADME.md3 This implements the minimum of the radeon kernel driver in order to make shader-db work.
7 LD_PRELOAD=$prefix/lib/libradeon_noop_drm_shim.so`. (or r600 for r600-class HW)
22 - `renoir` to expose a `CHIP_RENOIR` device
23 - `raven` to expose a `CHIP_RAVEN` device
24 - `stoney` to expose a `CHIP_STONEY` device
/third_party/mesa3d/src/drm-shim/
DREADME.md1 # DRM shim - Fake GEM kernel drivers in userspace for CI
4 be able to present either no-op GEM devices (for shader-db runs) or
5 simulator-backed GEM devices (for testing against a software simulator
11 - Doesn't know how to handle DRM fds getting passed over the wire from
13 - libc interception is rather glibc-specific and fragile.
14 - Can easily break gdb if the libc interceptor code is what's broken.
15 (ulimit -c unlimited and doing gdb on the core after the fact can
34 See your drm-shim backend's README for details on how to use it.
/third_party/mesa3d/src/freedreno/ci/
Dgitlab-ci.yml2 - local: 'src/freedreno/ci/gitlab-ci-inc.yml'
4 a306-gl:
6 - .baremetal-deqp-test
7 - .a306-test
9 DEQP_SUITE: freedreno-a307
13 a306-piglit:
15 - .baremetal-deqp-test
16 - .a306-test
17 - .google-freedreno-manual-rules
20 DEQP_SUITE: freedreno-a306-piglit
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/third_party/mesa3d/src/gallium/drivers/vc4/
Dvc4_context.h37 #include "drm-uapi/vc4_drm.h"
112 /** A name for this program, so you can track it in shader-db output. */
114 /** How many variants of this program were compiled, for shader-db. */
121 * Array of the meanings of the VPM inputs this shader needs.
137 * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
138 * uniforms have to be rewritten (and therefore the shader state
149 * failure. In this case, we have no shader to run and should not try
158 /* Byte offsets for the start of the vertex attributes 0-7, and the
190 /* Hash table key for vc4->jobs */
274 uint32_t clear_depth; /**< 24-bit unorm depth */
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