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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dpci.txt3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
21 - max-link-speed:
27 - reset-gpios:
30 - supports-clkreq:
31 If present this property specifies that CLKREQ signal routing exists from
33 which depends on CLKREQ signal existence. For example, programming root port
34 not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
[all …]
Dnvidia,tegra194-pcie.txt4 and thus inherits all the common properties defined in designware-pcie.txt.
9 - power-domains: A phandle to the node that controls power to the respective
19 "include/dt-bindings/power/tegra194-powergate.h" file.
20 - reg: A list of physical base address and length pairs for each set of
21 controller registers. Must contain an entry for each entry in the reg-names
23 - reg-names: Must include the following entries:
25 "config": As per the definition in designware-pcie.txt
31 - interrupts: A list of interrupt outputs of the controller. Must contain an
32 entry for each entry in the interrupt-names property.
33 - interrupt-names: Must include the following entries:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dpci.txt3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
21 - max-link-speed:
27 - reset-gpios:
30 - supports-clkreq:
31 If present this property specifies that CLKREQ signal routing exists from
33 which depends on CLKREQ signal existence. For example, programming root port
34 not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
[all …]
Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/
Dnuvoton,npcm7xx-pinctrl.txt3 The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
4 the multiplexing block, Each pin supports GPIO functionality (GPIOx)
9 - #address-cells : should be 1.
10 - #size-cells : should be 1.
11 - compatible : "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
12 - ranges : defines mapping ranges between pin controller node (parent)
17 The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.
19 Required GPIO Bank subnode-properties:
20 - reg : specifies physical base address and size of the GPIO
22 - gpio-controller : Marks the device node as a GPIO controller.
[all …]
Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
13 This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
37 mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
38 ptp-2(trig)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dnuvoton,npcm7xx-pinctrl.txt3 The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
4 the multiplexing block, Each pin supports GPIO functionality (GPIOx)
9 - #address-cells : should be 1.
10 - #size-cells : should be 1.
11 - compatible : "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
12 - ranges : defines mapping ranges between pin controller node (parent)
17 The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.
19 Required GPIO Bank subnode-properties:
20 - reg : specifies physical base address and size of the GPIO
22 - gpio-controller : Marks the device node as a GPIO controller.
[all …]
Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
13 This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
37 mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
38 ptp-2(trig)
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/
Darmada-388-clearfog.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include "armada-388.dtsi"
9 #include "armada-38x-solidrun-microsom.dtsi"
13 /* So that mvebu u-boot can update the MAC addresses */
20 stdout-path = "serial0:115200n8";
23 reg_3p3v: regulator-3p3v {
24 compatible = "regulator-fixed";
25 regulator-name = "3P3V";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Darmada-388-clearfog.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include "armada-388.dtsi"
9 #include "armada-38x-solidrun-microsom.dtsi"
13 /* So that mvebu u-boot can update the MAC addresses */
20 stdout-path = "serial0:115200n8";
23 reg_3p3v: regulator-3p3v {
24 compatible = "regulator-fixed";
25 regulator-name = "3P3V";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dtypes.h34 /* Board supports the Front End Module */
55 /* Flag to implement alternative A-band PLL settings */
59 /* Board supports the 2X4 diversity switch */
61 /* Board supports 5G band power gain */
63 /* Board overrides ASPM and Clkreq settings */
68 /* Board has a WAR for clock-harmonic spurs */
70 /* Flag to narrow G-band PLL loop b/w */
74 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
76 /* Flag to widen G-band PLL loop b/w */
86 * board specific GPIO assignment, gpio 0-3 are also customer-configurable
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dtypes.h34 /* Board supports the Front End Module */
55 /* Flag to implement alternative A-band PLL settings */
59 /* Board supports the 2X4 diversity switch */
61 /* Board supports 5G band power gain */
63 /* Board overrides ASPM and Clkreq settings */
68 /* Board has a WAR for clock-harmonic spurs */
70 /* Flag to narrow G-band PLL loop b/w */
74 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
76 /* Flag to widen G-band PLL loop b/w */
86 * board specific GPIO assignment, gpio 0-3 are also customer-configurable
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtw88/
Dpci.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
45 return skb->priority; in rtw_pci_get_tx_qsel()
51 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read8()
53 return readb(rtwpci->mmap + addr); in rtw_pci_read8()
58 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read16()
60 return readw(rtwpci->mmap + addr); in rtw_pci_read16()
65 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read32()
67 return readl(rtwpci->mmap + addr); in rtw_pci_read32()
72 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_write8()
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw88/
Dpci.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
46 return skb->priority; in rtw_pci_get_tx_qsel()
52 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read8()
54 return readb(rtwpci->mmap + addr); in rtw_pci_read8()
59 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read16()
61 return readw(rtwpci->mmap + addr); in rtw_pci_read16()
66 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read32()
68 return readl(rtwpci->mmap + addr); in rtw_pci_read32()
73 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_write8()
[all …]
/kernel/linux/linux-5.10/drivers/pci/controller/dwc/
Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
34 #include "pcie-designware.h"
36 #include <soc/tegra/bpmp-abi.h>
324 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
329 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
344 * NOTE:- Since this scenario is uncommon and link as such is not in apply_bad_link_workaround()
346 * transitioning to Gen-2 speed in apply_bad_link_workaround()
348 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
351 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
352 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); in apply_bad_link_workaround()
[all …]
/kernel/linux/linux-6.6/drivers/pci/controller/dwc/
Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
35 #include "pcie-designware.h"
37 #include <soc/tegra/bpmp-abi.h>
303 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
308 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
317 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_icc_set()
320 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_icc_set()
327 if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0)) in tegra_pcie_icc_set()
328 dev_err(pcie->dev, "can't set bw[%u]\n", val); in tegra_pcie_icc_set()
[all …]
/kernel/linux/linux-5.10/include/linux/ssb/
Dssb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
108 #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
168 * in two-byte quantities.
202 #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
218 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
219 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
225 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
226 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
[all …]
/kernel/linux/linux-6.6/include/linux/ssb/
Dssb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
108 #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
168 * in two-byte quantities.
202 #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
218 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
219 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
225 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
226 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/broadcom/b43/
Db43.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 /* 32-bit DMA */
68 /* 64-bit DMA */
179 #define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
181 #define B43_BFL_FEM 0x0800 /* supports the Front End Module */
203 #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
206 #define B43_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
207 #define B43_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
209 #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
211 #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/b43/
Db43.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 /* 32-bit DMA */
68 /* 64-bit DMA */
179 #define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
181 #define B43_BFL_FEM 0x0800 /* supports the Front End Module */
203 #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
206 #define B43_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
207 #define B43_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
209 #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
211 #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw89/
Dpci.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
18 MODULE_PARM_DESC(disable_clkreq, "Set Y to disable PCI clkreq support");
35 return -EBUSY; in rtw89_pci_rst_bdram_pcie()
46 rp = bd_ring->rp; in rtw89_pci_dma_recalc()
47 wp = bd_ring->wp; in rtw89_pci_dma_recalc()
48 len = bd_ring->len; in rtw89_pci_dma_recalc()
52 cnt = cur_rp >= rp ? cur_rp - rp : len - (rp - cur_rp); in rtw89_pci_dma_recalc()
54 cnt = cur_rp >= wp ? cur_rp - wp : len - (wp - cur_rp); in rtw89_pci_dma_recalc()
56 bd_ring->rp = cur_rp; in rtw89_pci_dma_recalc()
64 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; in rtw89_pci_txbd_recalc()
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/
Dmt8192-asurada.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/spmi/spmi.h>
25 stdout-path = "serial0:115200n8";
33 backlight_lcd0: backlight-lcd0 {
34 compatible = "pwm-backlight";
36 power-supply = <&ppvar_sys>;
37 enable-gpios = <&pio 152 0>;
38 brightness-levels = <0 1023>;
[all …]
/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0012_linux_drivers_ata.patch7 Change-Id: I4bec2b3114e101143470dc3704e3addbefcb19db
9 diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c
11 --- a/drivers/ata/ahci_imx.c
13 @@ -44,9 +44,23 @@ enum {
17 - IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET = 0x03,
18 - IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET = 0x09,
19 - IMX8QM_SATA_PHY_IMPED_RATIO_85OHM = 0x6c,
40 @@ -56,10 +70,31 @@ enum {
72 @@ -76,7 +111,10 @@ enum {
83 @@ -99,6 +137,12 @@ struct imx_ahci_priv {
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/nvidia/
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
[all …]

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