| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | mediatek,topckgen.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#
14 The Mediatek topckgen controller provides various clocks to the system.
21 - mediatek,mt6797-topckgen
22 - mediatek,mt7622-topckgen
23 - mediatek,mt8135-topckgen
24 - mediatek,mt8173-topckgen
25 - mediatek,mt8516-topckgen
27 - const: mediatek,mt7623-topckgen
28 - const: mediatek,mt2701-topckgen
32 - mediatek,mt2701-topckgen
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,topckgen.txt | 1 Mediatek topckgen controller
4 The Mediatek topckgen controller provides various clocks to the system.
9 - "mediatek,mt2701-topckgen"
10 - "mediatek,mt2712-topckgen", "syscon"
11 - "mediatek,mt6765-topckgen", "syscon"
12 - "mediatek,mt6779-topckgen", "syscon"
13 - "mediatek,mt6797-topckgen"
14 - "mediatek,mt7622-topckgen"
15 - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
16 - "mediatek,mt7629-topckgen"
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/ |
| D | mt8186-afe-pcm.yaml | 36 mediatek,topckgen:
38 description: The phandle of the mediatek topckgen controller
103 - mediatek,topckgen
122 mediatek,topckgen = <&topckgen>;
125 <&topckgen 15>, //CLK_TOP_AUDIO
126 <&topckgen 16>, //CLK_TOP_AUD_INTBUS
127 <&topckgen 70>, //CLK_TOP_MAINPLL_D2_D4
128 <&topckgen 17>, //CLK_TOP_AUD_1
130 <&topckgen 18>, //CLK_TOP_AUD_2
132 <&topckgen 19>, //CLK_TOP_AUD_ENGEN1
[all …]
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| D | mt2701-afe-pcm.txt | 69 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
70 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
71 <&topckgen CLK_TOP_AUD_48K_TIMING>,
72 <&topckgen CLK_TOP_AUD_44K_TIMING>,
73 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
74 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
75 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
76 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
77 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
78 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
[all …]
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| D | mediatek,mt8188-afe.yaml | 34 mediatek,topckgen:
36 description: The phandle of the mediatek topckgen controller
166 - mediatek,topckgen
186 mediatek,topckgen = <&topckgen>;
196 <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0
197 <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1
198 <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2
199 <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3
200 <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9
201 <&topckgen 83>, //CLK_TOP_A1SYS_HP
[all …]
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| D | mt8195-afe-pcm.yaml | 34 mediatek,topckgen:
36 description: The phandle of the mediatek topckgen controller
138 - mediatek,topckgen
157 mediatek,topckgen = <&topckgen>;
161 <&topckgen 163>, //CLK_TOP_APLL1
162 <&topckgen 166>, //CLK_TOP_APLL2
163 <&topckgen 233>, //CLK_TOP_APLL12_DIV0
164 <&topckgen 234>, //CLK_TOP_APLL12_DIV1
165 <&topckgen 235>, //CLK_TOP_APLL12_DIV2
166 <&topckgen 236>, //CLK_TOP_APLL12_DIV3
[all …]
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| D | mtk-afe-pcm.txt | 26 <&topckgen TOP_AUDIO_SEL>,
27 <&topckgen TOP_AUD_INTBUS_SEL>,
28 <&topckgen TOP_APLL1_DIV0>,
29 <&topckgen TOP_APLL2_DIV0>,
30 <&topckgen TOP_I2S0_M_CK_SEL>,
31 <&topckgen TOP_I2S1_M_CK_SEL>,
32 <&topckgen TOP_I2S2_M_CK_SEL>,
33 <&topckgen TOP_I2S3_M_CK_SEL>,
34 <&topckgen TOP_I2S3_B_CK_SEL>;
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | mt2701-afe-pcm.txt | 69 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
70 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
71 <&topckgen CLK_TOP_AUD_48K_TIMING>,
72 <&topckgen CLK_TOP_AUD_44K_TIMING>,
73 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
74 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
75 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
76 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
77 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
78 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
[all …]
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| D | mtk-afe-pcm.txt | 26 <&topckgen TOP_AUDIO_SEL>,
27 <&topckgen TOP_AUD_INTBUS_SEL>,
28 <&topckgen TOP_APLL1_DIV0>,
29 <&topckgen TOP_APLL2_DIV0>,
30 <&topckgen TOP_I2S0_M_CK_SEL>,
31 <&topckgen TOP_I2S1_M_CK_SEL>,
32 <&topckgen TOP_I2S2_M_CK_SEL>,
33 <&topckgen TOP_I2S3_M_CK_SEL>,
34 <&topckgen TOP_I2S3_B_CK_SEL>;
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/ |
| D | mt8516.dtsi | 58 <&topckgen CLK_TOP_MAINPLL_D2>;
71 <&topckgen CLK_TOP_MAINPLL_D2>;
84 <&topckgen CLK_TOP_MAINPLL_D2>;
97 <&topckgen CLK_TOP_MAINPLL_D2>;
182 topckgen: topckgen@10000000 { label
183 compatible = "mediatek,mt8516-topckgen", "syscon";
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
245 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
246 <&topckgen CLK_TOP_PMICWRAP_AP>;
[all …]
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| D | mt7622.dtsi | 243 clocks = <&topckgen CLK_TOP_HIF_SEL>;
252 <&topckgen CLK_TOP_AXI_SEL>;
285 topckgen: topckgen@10210000 { label
286 compatible = "mediatek,mt7622-topckgen",
325 clocks = <&topckgen CLK_TOP_RTC>;
389 clocks = <&topckgen CLK_TOP_UART_SEL>,
400 clocks = <&topckgen CLK_TOP_UART_SEL>,
411 clocks = <&topckgen CLK_TOP_UART_SEL>,
422 clocks = <&topckgen CLK_TOP_UART_SEL>,
433 clocks = <&topckgen CLK_TOP_PWM_SEL>,
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/ |
| D | mt8516.dtsi | 58 <&topckgen CLK_TOP_MAINPLL_D2>;
71 <&topckgen CLK_TOP_MAINPLL_D2>;
84 <&topckgen CLK_TOP_MAINPLL_D2>;
97 <&topckgen CLK_TOP_MAINPLL_D2>;
182 topckgen: topckgen@10000000 { label
183 compatible = "mediatek,mt8516-topckgen", "syscon";
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
251 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
252 <&topckgen CLK_TOP_PMICWRAP_AP>;
[all …]
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| D | mt8192.dtsi | 443 topckgen: syscon@10000000 { label
444 compatible = "mediatek,mt8192-topckgen", "syscon";
501 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
519 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,
520 <&topckgen CLK_TOP_MFG_REF_SEL>;
562 clocks = <&topckgen CLK_TOP_DISP_SEL>,
576 clocks = <&topckgen CLK_TOP_IPE_SEL>,
589 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
599 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
609 clocks = <&topckgen CLK_TOP_MDP_SEL>,
[all …]
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| D | mt7622.dtsi | 251 clocks = <&topckgen CLK_TOP_HIF_SEL>;
260 <&topckgen CLK_TOP_AXI_SEL>;
292 topckgen: clock-controller@10210000 { label
293 compatible = "mediatek,mt7622-topckgen";
331 clocks = <&topckgen CLK_TOP_RTC>;
395 clocks = <&topckgen CLK_TOP_UART_SEL>,
406 clocks = <&topckgen CLK_TOP_UART_SEL>,
417 clocks = <&topckgen CLK_TOP_UART_SEL>,
428 clocks = <&topckgen CLK_TOP_UART_SEL>,
439 clocks = <&topckgen CLK_TOP_PWM_SEL>,
[all …]
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| D | mt7986a.dtsi | 156 topckgen: topckgen@1001b000 { label
157 compatible = "mediatek,mt7986-topckgen", "syscon";
202 clocks = <&topckgen CLK_TOP_PWM_SEL>,
242 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
255 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
257 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
258 <&topckgen CLK_TOP_UART_SEL>;
271 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
284 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
308 clocks = <&topckgen CLK_TOP_MPLL_D2>,
[all …]
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| D | mt8195.dtsi | 483 topckgen: syscon@10000000 { label
484 compatible = "mediatek,mt8195-topckgen", "syscon";
544 <&topckgen CLK_TOP_MFG_CORE_TMP>;
580 clocks = <&topckgen CLK_TOP_VPP>,
581 <&topckgen CLK_TOP_CAM>,
582 <&topckgen CLK_TOP_CCU>,
583 <&topckgen CLK_TOP_IMG>,
584 <&topckgen CLK_TOP_VENC>,
585 <&topckgen CLK_TOP_VDEC>,
586 <&topckgen CLK_TOP_WPE_VPP>,
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | mediatek-vcodec.txt | 57 <&topckgen CLK_TOP_UNIVPLL_D2>,
58 <&topckgen CLK_TOP_CCI400_SEL>,
59 <&topckgen CLK_TOP_VDEC_SEL>,
60 <&topckgen CLK_TOP_VCODECPLL>,
62 <&topckgen CLK_TOP_VENC_LT_SEL>,
63 <&topckgen CLK_TOP_VCODECPLL_370P5>;
72 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
73 <&topckgen CLK_TOP_CCI400_SEL>,
74 <&topckgen CLK_TOP_VDEC_SEL>,
77 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | mt7629.dtsi | 98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
138 topckgen: syscon@10210000 { label
139 compatible = "mediatek,mt7629-topckgen", "syscon";
216 clocks = <&topckgen CLK_TOP_UART_SEL>,
227 clocks = <&topckgen CLK_TOP_UART_SEL>,
238 clocks = <&topckgen CLK_TOP_UART_SEL>,
248 clocks = <&topckgen CLK_TOP_PWM_SEL>,
252 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
[all …]
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| D | mt2701.dtsi | 126 topckgen: syscon@10000000 { label
127 compatible = "mediatek,mt2701-topckgen", "syscon";
156 clocks = <&topckgen CLK_TOP_MM_SEL>,
157 <&topckgen CLK_TOP_MFG_SEL>,
158 <&topckgen CLK_TOP_ETHIF_SEL>;
343 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
344 <&topckgen CLK_TOP_SPI0_SEL>,
390 <&topckgen CLK_TOP_FLASH_SEL>;
403 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
404 <&topckgen CLK_TOP_SPI1_SEL>,
[all …]
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| D | mt7623.dtsi | 226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
278 clocks = <&topckgen CLK_TOP_MM_SEL>,
279 <&topckgen CLK_TOP_MFG_SEL>,
280 <&topckgen CLK_TOP_ETHIF_SEL>;
424 clocks = <&topckgen CLK_TOP_PWM_SEL>,
488 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
489 <&topckgen CLK_TOP_SPI0_SEL>,
553 <&topckgen CLK_TOP_FLASH_SEL>;
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/mediatek/ |
| D | mt7629.dtsi | 98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
137 topckgen: syscon@10210000 { label
138 compatible = "mediatek,mt7629-topckgen", "syscon";
215 clocks = <&topckgen CLK_TOP_UART_SEL>,
226 clocks = <&topckgen CLK_TOP_UART_SEL>,
237 clocks = <&topckgen CLK_TOP_UART_SEL>,
247 clocks = <&topckgen CLK_TOP_PWM_SEL>,
251 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
[all …]
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| D | mt2701.dtsi | 126 topckgen: syscon@10000000 { label
127 compatible = "mediatek,mt2701-topckgen", "syscon";
156 clocks = <&topckgen CLK_TOP_MM_SEL>,
157 <&topckgen CLK_TOP_MFG_SEL>,
158 <&topckgen CLK_TOP_ETHIF_SEL>;
342 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
343 <&topckgen CLK_TOP_SPI0_SEL>,
389 <&topckgen CLK_TOP_FLASH_SEL>;
402 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
403 <&topckgen CLK_TOP_SPI1_SEL>,
[all …]
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| D | mt7623.dtsi | 226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
277 clocks = <&topckgen CLK_TOP_MM_SEL>,
278 <&topckgen CLK_TOP_MFG_SEL>,
279 <&topckgen CLK_TOP_ETHIF_SEL>;
423 clocks = <&topckgen CLK_TOP_PWM_SEL>,
487 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
488 <&topckgen CLK_TOP_SPI0_SEL>,
552 <&topckgen CLK_TOP_FLASH_SEL>;
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/ |
| D | mediatek,vcodec-decoder.yaml | 175 <&topckgen CLK_TOP_UNIVPLL_D2>,
176 <&topckgen CLK_TOP_CCI400_SEL>,
177 <&topckgen CLK_TOP_VDEC_SEL>,
178 <&topckgen CLK_TOP_VCODECPLL>,
180 <&topckgen CLK_TOP_VENC_LT_SEL>,
181 <&topckgen CLK_TOP_VCODECPLL_370P5>;
190 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
191 <&topckgen CLK_TOP_CCI400_SEL>,
192 <&topckgen CLK_TOP_VDEC_SEL>,
195 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | spi-slave-mt27xx.txt | 13 - assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
16 - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.
18 - <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.
19 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
20 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
30 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
31 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
|