1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16#include <dt-bindings/reset/mt8195-resets.h> 17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 19 20/ { 21 compatible = "mediatek,mt8195"; 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 dp-intf0 = &dp_intf0; 28 dp-intf1 = &dp_intf1; 29 gce0 = &gce0; 30 gce1 = &gce1; 31 ethdr0 = ðdr0; 32 mutex0 = &mutex; 33 mutex1 = &mutex1; 34 merge1 = &merge1; 35 merge2 = &merge2; 36 merge3 = &merge3; 37 merge4 = &merge4; 38 merge5 = &merge5; 39 vdo1-rdma0 = &vdo1_rdma0; 40 vdo1-rdma1 = &vdo1_rdma1; 41 vdo1-rdma2 = &vdo1_rdma2; 42 vdo1-rdma3 = &vdo1_rdma3; 43 vdo1-rdma4 = &vdo1_rdma4; 44 vdo1-rdma5 = &vdo1_rdma5; 45 vdo1-rdma6 = &vdo1_rdma6; 46 vdo1-rdma7 = &vdo1_rdma7; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x000>; 57 enable-method = "psci"; 58 performance-domains = <&performance 0>; 59 clock-frequency = <1701000000>; 60 capacity-dmips-mhz = <308>; 61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 62 i-cache-size = <32768>; 63 i-cache-line-size = <64>; 64 i-cache-sets = <128>; 65 d-cache-size = <32768>; 66 d-cache-line-size = <64>; 67 d-cache-sets = <128>; 68 next-level-cache = <&l2_0>; 69 #cooling-cells = <2>; 70 }; 71 72 cpu1: cpu@100 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x100>; 76 enable-method = "psci"; 77 performance-domains = <&performance 0>; 78 clock-frequency = <1701000000>; 79 capacity-dmips-mhz = <308>; 80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 81 i-cache-size = <32768>; 82 i-cache-line-size = <64>; 83 i-cache-sets = <128>; 84 d-cache-size = <32768>; 85 d-cache-line-size = <64>; 86 d-cache-sets = <128>; 87 next-level-cache = <&l2_0>; 88 #cooling-cells = <2>; 89 }; 90 91 cpu2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x200>; 95 enable-method = "psci"; 96 performance-domains = <&performance 0>; 97 clock-frequency = <1701000000>; 98 capacity-dmips-mhz = <308>; 99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_0>; 107 #cooling-cells = <2>; 108 }; 109 110 cpu3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a55"; 113 reg = <0x300>; 114 enable-method = "psci"; 115 performance-domains = <&performance 0>; 116 clock-frequency = <1701000000>; 117 capacity-dmips-mhz = <308>; 118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 119 i-cache-size = <32768>; 120 i-cache-line-size = <64>; 121 i-cache-sets = <128>; 122 d-cache-size = <32768>; 123 d-cache-line-size = <64>; 124 d-cache-sets = <128>; 125 next-level-cache = <&l2_0>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu4: cpu@400 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a78"; 132 reg = <0x400>; 133 enable-method = "psci"; 134 performance-domains = <&performance 1>; 135 clock-frequency = <2171000000>; 136 capacity-dmips-mhz = <1024>; 137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 138 i-cache-size = <65536>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <256>; 141 d-cache-size = <65536>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <256>; 144 next-level-cache = <&l2_1>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu5: cpu@500 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a78"; 151 reg = <0x500>; 152 enable-method = "psci"; 153 performance-domains = <&performance 1>; 154 clock-frequency = <2171000000>; 155 capacity-dmips-mhz = <1024>; 156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 157 i-cache-size = <65536>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <256>; 160 d-cache-size = <65536>; 161 d-cache-line-size = <64>; 162 d-cache-sets = <256>; 163 next-level-cache = <&l2_1>; 164 #cooling-cells = <2>; 165 }; 166 167 cpu6: cpu@600 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a78"; 170 reg = <0x600>; 171 enable-method = "psci"; 172 performance-domains = <&performance 1>; 173 clock-frequency = <2171000000>; 174 capacity-dmips-mhz = <1024>; 175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 176 i-cache-size = <65536>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <65536>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&l2_1>; 183 #cooling-cells = <2>; 184 }; 185 186 cpu7: cpu@700 { 187 device_type = "cpu"; 188 compatible = "arm,cortex-a78"; 189 reg = <0x700>; 190 enable-method = "psci"; 191 performance-domains = <&performance 1>; 192 clock-frequency = <2171000000>; 193 capacity-dmips-mhz = <1024>; 194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 195 i-cache-size = <65536>; 196 i-cache-line-size = <64>; 197 i-cache-sets = <256>; 198 d-cache-size = <65536>; 199 d-cache-line-size = <64>; 200 d-cache-sets = <256>; 201 next-level-cache = <&l2_1>; 202 #cooling-cells = <2>; 203 }; 204 205 cpu-map { 206 cluster0 { 207 core0 { 208 cpu = <&cpu0>; 209 }; 210 211 core1 { 212 cpu = <&cpu1>; 213 }; 214 215 core2 { 216 cpu = <&cpu2>; 217 }; 218 219 core3 { 220 cpu = <&cpu3>; 221 }; 222 223 core4 { 224 cpu = <&cpu4>; 225 }; 226 227 core5 { 228 cpu = <&cpu5>; 229 }; 230 231 core6 { 232 cpu = <&cpu6>; 233 }; 234 235 core7 { 236 cpu = <&cpu7>; 237 }; 238 }; 239 }; 240 241 idle-states { 242 entry-method = "psci"; 243 244 cpu_ret_l: cpu-retention-l { 245 compatible = "arm,idle-state"; 246 arm,psci-suspend-param = <0x00010001>; 247 local-timer-stop; 248 entry-latency-us = <50>; 249 exit-latency-us = <95>; 250 min-residency-us = <580>; 251 }; 252 253 cpu_ret_b: cpu-retention-b { 254 compatible = "arm,idle-state"; 255 arm,psci-suspend-param = <0x00010001>; 256 local-timer-stop; 257 entry-latency-us = <45>; 258 exit-latency-us = <140>; 259 min-residency-us = <740>; 260 }; 261 262 cpu_off_l: cpu-off-l { 263 compatible = "arm,idle-state"; 264 arm,psci-suspend-param = <0x01010002>; 265 local-timer-stop; 266 entry-latency-us = <55>; 267 exit-latency-us = <155>; 268 min-residency-us = <840>; 269 }; 270 271 cpu_off_b: cpu-off-b { 272 compatible = "arm,idle-state"; 273 arm,psci-suspend-param = <0x01010002>; 274 local-timer-stop; 275 entry-latency-us = <50>; 276 exit-latency-us = <200>; 277 min-residency-us = <1000>; 278 }; 279 }; 280 281 l2_0: l2-cache0 { 282 compatible = "cache"; 283 cache-level = <2>; 284 cache-size = <131072>; 285 cache-line-size = <64>; 286 cache-sets = <512>; 287 next-level-cache = <&l3_0>; 288 cache-unified; 289 }; 290 291 l2_1: l2-cache1 { 292 compatible = "cache"; 293 cache-level = <2>; 294 cache-size = <262144>; 295 cache-line-size = <64>; 296 cache-sets = <512>; 297 next-level-cache = <&l3_0>; 298 cache-unified; 299 }; 300 301 l3_0: l3-cache { 302 compatible = "cache"; 303 cache-level = <3>; 304 cache-size = <2097152>; 305 cache-line-size = <64>; 306 cache-sets = <2048>; 307 cache-unified; 308 }; 309 }; 310 311 dsu-pmu { 312 compatible = "arm,dsu-pmu"; 313 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 314 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 315 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 316 status = "fail"; 317 }; 318 319 dmic_codec: dmic-codec { 320 compatible = "dmic-codec"; 321 num-channels = <2>; 322 wakeup-delay-ms = <50>; 323 }; 324 325 sound: mt8195-sound { 326 mediatek,platform = <&afe>; 327 status = "disabled"; 328 }; 329 330 clk13m: fixed-factor-clock-13m { 331 compatible = "fixed-factor-clock"; 332 #clock-cells = <0>; 333 clocks = <&clk26m>; 334 clock-div = <2>; 335 clock-mult = <1>; 336 clock-output-names = "clk13m"; 337 }; 338 339 clk26m: oscillator-26m { 340 compatible = "fixed-clock"; 341 #clock-cells = <0>; 342 clock-frequency = <26000000>; 343 clock-output-names = "clk26m"; 344 }; 345 346 clk32k: oscillator-32k { 347 compatible = "fixed-clock"; 348 #clock-cells = <0>; 349 clock-frequency = <32768>; 350 clock-output-names = "clk32k"; 351 }; 352 353 performance: performance-controller@11bc10 { 354 compatible = "mediatek,cpufreq-hw"; 355 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 356 #performance-domain-cells = <1>; 357 }; 358 359 gpu_opp_table: opp-table-gpu { 360 compatible = "operating-points-v2"; 361 opp-shared; 362 363 opp-390000000 { 364 opp-hz = /bits/ 64 <390000000>; 365 opp-microvolt = <625000>; 366 }; 367 opp-410000000 { 368 opp-hz = /bits/ 64 <410000000>; 369 opp-microvolt = <631250>; 370 }; 371 opp-431000000 { 372 opp-hz = /bits/ 64 <431000000>; 373 opp-microvolt = <631250>; 374 }; 375 opp-473000000 { 376 opp-hz = /bits/ 64 <473000000>; 377 opp-microvolt = <637500>; 378 }; 379 opp-515000000 { 380 opp-hz = /bits/ 64 <515000000>; 381 opp-microvolt = <637500>; 382 }; 383 opp-556000000 { 384 opp-hz = /bits/ 64 <556000000>; 385 opp-microvolt = <643750>; 386 }; 387 opp-598000000 { 388 opp-hz = /bits/ 64 <598000000>; 389 opp-microvolt = <650000>; 390 }; 391 opp-640000000 { 392 opp-hz = /bits/ 64 <640000000>; 393 opp-microvolt = <650000>; 394 }; 395 opp-670000000 { 396 opp-hz = /bits/ 64 <670000000>; 397 opp-microvolt = <662500>; 398 }; 399 opp-700000000 { 400 opp-hz = /bits/ 64 <700000000>; 401 opp-microvolt = <675000>; 402 }; 403 opp-730000000 { 404 opp-hz = /bits/ 64 <730000000>; 405 opp-microvolt = <687500>; 406 }; 407 opp-760000000 { 408 opp-hz = /bits/ 64 <760000000>; 409 opp-microvolt = <700000>; 410 }; 411 opp-790000000 { 412 opp-hz = /bits/ 64 <790000000>; 413 opp-microvolt = <712500>; 414 }; 415 opp-820000000 { 416 opp-hz = /bits/ 64 <820000000>; 417 opp-microvolt = <725000>; 418 }; 419 opp-850000000 { 420 opp-hz = /bits/ 64 <850000000>; 421 opp-microvolt = <737500>; 422 }; 423 opp-880000000 { 424 opp-hz = /bits/ 64 <880000000>; 425 opp-microvolt = <750000>; 426 }; 427 }; 428 429 pmu-a55 { 430 compatible = "arm,cortex-a55-pmu"; 431 interrupt-parent = <&gic>; 432 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 433 }; 434 435 pmu-a78 { 436 compatible = "arm,cortex-a78-pmu"; 437 interrupt-parent = <&gic>; 438 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 439 }; 440 441 psci { 442 compatible = "arm,psci-1.0"; 443 method = "smc"; 444 }; 445 446 timer: timer { 447 compatible = "arm,armv8-timer"; 448 interrupt-parent = <&gic>; 449 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 450 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 451 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 452 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 453 }; 454 455 soc { 456 #address-cells = <2>; 457 #size-cells = <2>; 458 compatible = "simple-bus"; 459 ranges; 460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 461 462 gic: interrupt-controller@c000000 { 463 compatible = "arm,gic-v3"; 464 #interrupt-cells = <4>; 465 #redistributor-regions = <1>; 466 interrupt-parent = <&gic>; 467 interrupt-controller; 468 reg = <0 0x0c000000 0 0x40000>, 469 <0 0x0c040000 0 0x200000>; 470 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 471 472 ppi-partitions { 473 ppi_cluster0: interrupt-partition-0 { 474 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 475 }; 476 477 ppi_cluster1: interrupt-partition-1 { 478 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 479 }; 480 }; 481 }; 482 483 topckgen: syscon@10000000 { 484 compatible = "mediatek,mt8195-topckgen", "syscon"; 485 reg = <0 0x10000000 0 0x1000>; 486 #clock-cells = <1>; 487 }; 488 489 infracfg_ao: syscon@10001000 { 490 compatible = "mediatek,mt8195-infracfg_ao", "syscon"; 491 reg = <0 0x10001000 0 0x1000>; 492 #clock-cells = <1>; 493 #reset-cells = <1>; 494 }; 495 496 pericfg: syscon@10003000 { 497 compatible = "mediatek,mt8195-pericfg", "syscon"; 498 reg = <0 0x10003000 0 0x1000>; 499 #clock-cells = <1>; 500 }; 501 502 pio: pinctrl@10005000 { 503 compatible = "mediatek,mt8195-pinctrl"; 504 reg = <0 0x10005000 0 0x1000>, 505 <0 0x11d10000 0 0x1000>, 506 <0 0x11d30000 0 0x1000>, 507 <0 0x11d40000 0 0x1000>, 508 <0 0x11e20000 0 0x1000>, 509 <0 0x11eb0000 0 0x1000>, 510 <0 0x11f40000 0 0x1000>, 511 <0 0x1000b000 0 0x1000>; 512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 513 "iocfg_br", "iocfg_lm", "iocfg_rb", 514 "iocfg_tl", "eint"; 515 gpio-controller; 516 #gpio-cells = <2>; 517 gpio-ranges = <&pio 0 0 144>; 518 interrupt-controller; 519 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 520 #interrupt-cells = <2>; 521 }; 522 523 scpsys: syscon@10006000 { 524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 525 reg = <0 0x10006000 0 0x1000>; 526 527 /* System Power Manager */ 528 spm: power-controller { 529 compatible = "mediatek,mt8195-power-controller"; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 #power-domain-cells = <1>; 533 534 /* power domain of the SoC */ 535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 536 reg = <MT8195_POWER_DOMAIN_MFG0>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 #power-domain-cells = <1>; 540 541 power-domain@MT8195_POWER_DOMAIN_MFG1 { 542 reg = <MT8195_POWER_DOMAIN_MFG1>; 543 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, 544 <&topckgen CLK_TOP_MFG_CORE_TMP>; 545 clock-names = "mfg", "alt"; 546 mediatek,infracfg = <&infracfg_ao>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 #power-domain-cells = <1>; 550 551 power-domain@MT8195_POWER_DOMAIN_MFG2 { 552 reg = <MT8195_POWER_DOMAIN_MFG2>; 553 #power-domain-cells = <0>; 554 }; 555 556 power-domain@MT8195_POWER_DOMAIN_MFG3 { 557 reg = <MT8195_POWER_DOMAIN_MFG3>; 558 #power-domain-cells = <0>; 559 }; 560 561 power-domain@MT8195_POWER_DOMAIN_MFG4 { 562 reg = <MT8195_POWER_DOMAIN_MFG4>; 563 #power-domain-cells = <0>; 564 }; 565 566 power-domain@MT8195_POWER_DOMAIN_MFG5 { 567 reg = <MT8195_POWER_DOMAIN_MFG5>; 568 #power-domain-cells = <0>; 569 }; 570 571 power-domain@MT8195_POWER_DOMAIN_MFG6 { 572 reg = <MT8195_POWER_DOMAIN_MFG6>; 573 #power-domain-cells = <0>; 574 }; 575 }; 576 }; 577 578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 579 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 580 clocks = <&topckgen CLK_TOP_VPP>, 581 <&topckgen CLK_TOP_CAM>, 582 <&topckgen CLK_TOP_CCU>, 583 <&topckgen CLK_TOP_IMG>, 584 <&topckgen CLK_TOP_VENC>, 585 <&topckgen CLK_TOP_VDEC>, 586 <&topckgen CLK_TOP_WPE_VPP>, 587 <&topckgen CLK_TOP_CFG_VPP0>, 588 <&vppsys0 CLK_VPP0_SMI_COMMON>, 589 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 590 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 591 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 592 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 593 <&vppsys0 CLK_VPP0_GALS_INFRA>, 594 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 595 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 596 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 597 <&vppsys0 CLK_VPP0_SMI_REORDER>, 598 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 599 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 600 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 601 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 602 <&vppsys0 CLK_VPP0_SMI_RSI>, 603 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 604 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 605 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 606 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 608 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 612 "vppsys0-12", "vppsys0-13", "vppsys0-14", 613 "vppsys0-15", "vppsys0-16", "vppsys0-17", 614 "vppsys0-18"; 615 mediatek,infracfg = <&infracfg_ao>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 #power-domain-cells = <1>; 619 620 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 621 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 622 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 623 <&vdosys0 CLK_VDO0_SMI_GALS>, 624 <&vdosys0 CLK_VDO0_SMI_COMMON>, 625 <&vdosys0 CLK_VDO0_SMI_EMI>, 626 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 627 <&vdosys0 CLK_VDO0_SMI_LARB>, 628 <&vdosys0 CLK_VDO0_SMI_RSI>; 629 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 630 "vdosys0-2", "vdosys0-3", 631 "vdosys0-4", "vdosys0-5"; 632 mediatek,infracfg = <&infracfg_ao>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 #power-domain-cells = <1>; 636 637 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 638 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 639 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 640 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 641 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 642 clock-names = "vppsys1", "vppsys1-0", 643 "vppsys1-1"; 644 mediatek,infracfg = <&infracfg_ao>; 645 #power-domain-cells = <0>; 646 }; 647 648 power-domain@MT8195_POWER_DOMAIN_WPESYS { 649 reg = <MT8195_POWER_DOMAIN_WPESYS>; 650 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 651 <&wpesys CLK_WPE_SMI_LARB8>, 652 <&wpesys CLK_WPE_SMI_LARB7_P>, 653 <&wpesys CLK_WPE_SMI_LARB8_P>; 654 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 655 "wepsys-3"; 656 mediatek,infracfg = <&infracfg_ao>; 657 #power-domain-cells = <0>; 658 }; 659 660 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 661 reg = <MT8195_POWER_DOMAIN_VDEC0>; 662 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 663 clock-names = "vdec0-0"; 664 mediatek,infracfg = <&infracfg_ao>; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 #power-domain-cells = <0>; 668 669 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 670 reg = <MT8195_POWER_DOMAIN_VDEC1>; 671 clocks = <&vdecsys CLK_VDEC_LARB1>; 672 clock-names = "vdec1-0"; 673 mediatek,infracfg = <&infracfg_ao>; 674 #power-domain-cells = <0>; 675 }; 676 677 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 678 reg = <MT8195_POWER_DOMAIN_VDEC2>; 679 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 680 clock-names = "vdec2-0"; 681 mediatek,infracfg = <&infracfg_ao>; 682 #power-domain-cells = <0>; 683 }; 684 }; 685 686 power-domain@MT8195_POWER_DOMAIN_VENC { 687 reg = <MT8195_POWER_DOMAIN_VENC>; 688 clocks = <&vencsys CLK_VENC_LARB>; 689 clock-names = "venc0-larb"; 690 mediatek,infracfg = <&infracfg_ao>; 691 #address-cells = <1>; 692 #size-cells = <0>; 693 #power-domain-cells = <0>; 694 695 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 696 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 697 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>; 698 clock-names = "venc1-larb"; 699 mediatek,infracfg = <&infracfg_ao>; 700 #power-domain-cells = <0>; 701 }; 702 }; 703 704 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 705 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 706 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 707 <&vdosys1 CLK_VDO1_SMI_LARB2>, 708 <&vdosys1 CLK_VDO1_SMI_LARB3>, 709 <&vdosys1 CLK_VDO1_GALS>; 710 clock-names = "vdosys1", "vdosys1-0", 711 "vdosys1-1", "vdosys1-2"; 712 mediatek,infracfg = <&infracfg_ao>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 #power-domain-cells = <1>; 716 717 power-domain@MT8195_POWER_DOMAIN_DP_TX { 718 reg = <MT8195_POWER_DOMAIN_DP_TX>; 719 mediatek,infracfg = <&infracfg_ao>; 720 #power-domain-cells = <0>; 721 }; 722 723 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 724 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 725 mediatek,infracfg = <&infracfg_ao>; 726 #power-domain-cells = <0>; 727 }; 728 729 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 730 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 731 clocks = <&topckgen CLK_TOP_HDMI_APB>; 732 clock-names = "hdmi_tx"; 733 #power-domain-cells = <0>; 734 }; 735 }; 736 737 power-domain@MT8195_POWER_DOMAIN_IMG { 738 reg = <MT8195_POWER_DOMAIN_IMG>; 739 clocks = <&imgsys CLK_IMG_LARB9>, 740 <&imgsys CLK_IMG_GALS>; 741 clock-names = "img-0", "img-1"; 742 mediatek,infracfg = <&infracfg_ao>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 #power-domain-cells = <1>; 746 747 power-domain@MT8195_POWER_DOMAIN_DIP { 748 reg = <MT8195_POWER_DOMAIN_DIP>; 749 #power-domain-cells = <0>; 750 }; 751 752 power-domain@MT8195_POWER_DOMAIN_IPE { 753 reg = <MT8195_POWER_DOMAIN_IPE>; 754 clocks = <&topckgen CLK_TOP_IPE>, 755 <&imgsys CLK_IMG_IPE>, 756 <&ipesys CLK_IPE_SMI_LARB12>; 757 clock-names = "ipe", "ipe-0", "ipe-1"; 758 mediatek,infracfg = <&infracfg_ao>; 759 #power-domain-cells = <0>; 760 }; 761 }; 762 763 power-domain@MT8195_POWER_DOMAIN_CAM { 764 reg = <MT8195_POWER_DOMAIN_CAM>; 765 clocks = <&camsys CLK_CAM_LARB13>, 766 <&camsys CLK_CAM_LARB14>, 767 <&camsys CLK_CAM_CAM2MM0_GALS>, 768 <&camsys CLK_CAM_CAM2MM1_GALS>, 769 <&camsys CLK_CAM_CAM2SYS_GALS>; 770 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 771 "cam-4"; 772 mediatek,infracfg = <&infracfg_ao>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 #power-domain-cells = <1>; 776 777 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 778 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 779 #power-domain-cells = <0>; 780 }; 781 782 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 783 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 784 #power-domain-cells = <0>; 785 }; 786 787 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 788 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 789 #power-domain-cells = <0>; 790 }; 791 }; 792 }; 793 }; 794 795 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 796 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 797 mediatek,infracfg = <&infracfg_ao>; 798 #power-domain-cells = <0>; 799 }; 800 801 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 802 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 803 mediatek,infracfg = <&infracfg_ao>; 804 #power-domain-cells = <0>; 805 }; 806 807 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 808 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 809 #power-domain-cells = <0>; 810 }; 811 812 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 813 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 814 #power-domain-cells = <0>; 815 }; 816 817 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 818 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 819 clocks = <&topckgen CLK_TOP_SENINF>, 820 <&topckgen CLK_TOP_SENINF2>; 821 clock-names = "csi_rx_top", "csi_rx_top1"; 822 #power-domain-cells = <0>; 823 }; 824 825 power-domain@MT8195_POWER_DOMAIN_ETHER { 826 reg = <MT8195_POWER_DOMAIN_ETHER>; 827 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 828 clock-names = "ether"; 829 #power-domain-cells = <0>; 830 }; 831 832 power-domain@MT8195_POWER_DOMAIN_ADSP { 833 reg = <MT8195_POWER_DOMAIN_ADSP>; 834 clocks = <&topckgen CLK_TOP_ADSP>, 835 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 836 clock-names = "adsp", "adsp1"; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 mediatek,infracfg = <&infracfg_ao>; 840 #power-domain-cells = <1>; 841 842 power-domain@MT8195_POWER_DOMAIN_AUDIO { 843 reg = <MT8195_POWER_DOMAIN_AUDIO>; 844 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 845 <&topckgen CLK_TOP_AUD_INTBUS>, 846 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 847 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 848 clock-names = "audio", "audio1", "audio2", 849 "audio3"; 850 mediatek,infracfg = <&infracfg_ao>; 851 #power-domain-cells = <0>; 852 }; 853 }; 854 }; 855 }; 856 857 watchdog: watchdog@10007000 { 858 compatible = "mediatek,mt8195-wdt"; 859 mediatek,disable-extrst; 860 reg = <0 0x10007000 0 0x100>; 861 #reset-cells = <1>; 862 }; 863 864 apmixedsys: syscon@1000c000 { 865 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 866 reg = <0 0x1000c000 0 0x1000>; 867 #clock-cells = <1>; 868 }; 869 870 systimer: timer@10017000 { 871 compatible = "mediatek,mt8195-timer", 872 "mediatek,mt6765-timer"; 873 reg = <0 0x10017000 0 0x1000>; 874 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 875 clocks = <&clk13m>; 876 }; 877 878 pwrap: pwrap@10024000 { 879 compatible = "mediatek,mt8195-pwrap", "syscon"; 880 reg = <0 0x10024000 0 0x1000>; 881 reg-names = "pwrap"; 882 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 883 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 884 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 885 clock-names = "spi", "wrap"; 886 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 887 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 888 }; 889 890 spmi: spmi@10027000 { 891 compatible = "mediatek,mt8195-spmi"; 892 reg = <0 0x10027000 0 0x000e00>, 893 <0 0x10029000 0 0x000100>; 894 reg-names = "pmif", "spmimst"; 895 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 896 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 897 <&topckgen CLK_TOP_SPMI_M_MST>; 898 clock-names = "pmif_sys_ck", 899 "pmif_tmr_ck", 900 "spmimst_clk_mux"; 901 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 902 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 903 }; 904 905 iommu_infra: infra-iommu@10315000 { 906 compatible = "mediatek,mt8195-iommu-infra"; 907 reg = <0 0x10315000 0 0x5000>; 908 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 909 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 910 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 911 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 912 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 913 #iommu-cells = <1>; 914 }; 915 916 gce0: mailbox@10320000 { 917 compatible = "mediatek,mt8195-gce"; 918 reg = <0 0x10320000 0 0x4000>; 919 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 920 #mbox-cells = <2>; 921 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 922 }; 923 924 gce1: mailbox@10330000 { 925 compatible = "mediatek,mt8195-gce"; 926 reg = <0 0x10330000 0 0x4000>; 927 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 928 #mbox-cells = <2>; 929 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 930 }; 931 932 scp: scp@10500000 { 933 compatible = "mediatek,mt8195-scp"; 934 reg = <0 0x10500000 0 0x100000>, 935 <0 0x10720000 0 0xe0000>, 936 <0 0x10700000 0 0x8000>; 937 reg-names = "sram", "cfg", "l1tcm"; 938 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 939 status = "disabled"; 940 }; 941 942 scp_adsp: clock-controller@10720000 { 943 compatible = "mediatek,mt8195-scp_adsp"; 944 reg = <0 0x10720000 0 0x1000>; 945 #clock-cells = <1>; 946 }; 947 948 adsp: dsp@10803000 { 949 compatible = "mediatek,mt8195-dsp"; 950 reg = <0 0x10803000 0 0x1000>, 951 <0 0x10840000 0 0x40000>; 952 reg-names = "cfg", "sram"; 953 clocks = <&topckgen CLK_TOP_ADSP>, 954 <&clk26m>, 955 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 956 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 957 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 958 <&topckgen CLK_TOP_AUDIO_H>; 959 clock-names = "adsp_sel", 960 "clk26m_ck", 961 "audio_local_bus", 962 "mainpll_d7_d2", 963 "scp_adsp_audiodsp", 964 "audio_h"; 965 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 966 mbox-names = "rx", "tx"; 967 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 968 status = "disabled"; 969 }; 970 971 adsp_mailbox0: mailbox@10816000 { 972 compatible = "mediatek,mt8195-adsp-mbox"; 973 #mbox-cells = <0>; 974 reg = <0 0x10816000 0 0x1000>; 975 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 976 }; 977 978 adsp_mailbox1: mailbox@10817000 { 979 compatible = "mediatek,mt8195-adsp-mbox"; 980 #mbox-cells = <0>; 981 reg = <0 0x10817000 0 0x1000>; 982 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 983 }; 984 985 afe: mt8195-afe-pcm@10890000 { 986 compatible = "mediatek,mt8195-audio"; 987 reg = <0 0x10890000 0 0x10000>; 988 mediatek,topckgen = <&topckgen>; 989 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 990 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 991 resets = <&watchdog 14>; 992 reset-names = "audiosys"; 993 clocks = <&clk26m>, 994 <&apmixedsys CLK_APMIXED_APLL1>, 995 <&apmixedsys CLK_APMIXED_APLL2>, 996 <&topckgen CLK_TOP_APLL12_DIV0>, 997 <&topckgen CLK_TOP_APLL12_DIV1>, 998 <&topckgen CLK_TOP_APLL12_DIV2>, 999 <&topckgen CLK_TOP_APLL12_DIV3>, 1000 <&topckgen CLK_TOP_APLL12_DIV9>, 1001 <&topckgen CLK_TOP_A1SYS_HP>, 1002 <&topckgen CLK_TOP_AUD_INTBUS>, 1003 <&topckgen CLK_TOP_AUDIO_H>, 1004 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 1005 <&topckgen CLK_TOP_DPTX_MCK>, 1006 <&topckgen CLK_TOP_I2SO1_MCK>, 1007 <&topckgen CLK_TOP_I2SO2_MCK>, 1008 <&topckgen CLK_TOP_I2SI1_MCK>, 1009 <&topckgen CLK_TOP_I2SI2_MCK>, 1010 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 1011 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 1012 clock-names = "clk26m", 1013 "apll1_ck", 1014 "apll2_ck", 1015 "apll12_div0", 1016 "apll12_div1", 1017 "apll12_div2", 1018 "apll12_div3", 1019 "apll12_div9", 1020 "a1sys_hp_sel", 1021 "aud_intbus_sel", 1022 "audio_h_sel", 1023 "audio_local_bus_sel", 1024 "dptx_m_sel", 1025 "i2so1_m_sel", 1026 "i2so2_m_sel", 1027 "i2si1_m_sel", 1028 "i2si2_m_sel", 1029 "infra_ao_audio_26m_b", 1030 "scp_adsp_audiodsp"; 1031 status = "disabled"; 1032 }; 1033 1034 uart0: serial@11001100 { 1035 compatible = "mediatek,mt8195-uart", 1036 "mediatek,mt6577-uart"; 1037 reg = <0 0x11001100 0 0x100>; 1038 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 1039 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1040 clock-names = "baud", "bus"; 1041 status = "disabled"; 1042 }; 1043 1044 uart1: serial@11001200 { 1045 compatible = "mediatek,mt8195-uart", 1046 "mediatek,mt6577-uart"; 1047 reg = <0 0x11001200 0 0x100>; 1048 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1049 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1050 clock-names = "baud", "bus"; 1051 status = "disabled"; 1052 }; 1053 1054 uart2: serial@11001300 { 1055 compatible = "mediatek,mt8195-uart", 1056 "mediatek,mt6577-uart"; 1057 reg = <0 0x11001300 0 0x100>; 1058 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1059 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1060 clock-names = "baud", "bus"; 1061 status = "disabled"; 1062 }; 1063 1064 uart3: serial@11001400 { 1065 compatible = "mediatek,mt8195-uart", 1066 "mediatek,mt6577-uart"; 1067 reg = <0 0x11001400 0 0x100>; 1068 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 1069 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 1070 clock-names = "baud", "bus"; 1071 status = "disabled"; 1072 }; 1073 1074 uart4: serial@11001500 { 1075 compatible = "mediatek,mt8195-uart", 1076 "mediatek,mt6577-uart"; 1077 reg = <0 0x11001500 0 0x100>; 1078 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 1079 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 1080 clock-names = "baud", "bus"; 1081 status = "disabled"; 1082 }; 1083 1084 uart5: serial@11001600 { 1085 compatible = "mediatek,mt8195-uart", 1086 "mediatek,mt6577-uart"; 1087 reg = <0 0x11001600 0 0x100>; 1088 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 1089 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 1090 clock-names = "baud", "bus"; 1091 status = "disabled"; 1092 }; 1093 1094 auxadc: auxadc@11002000 { 1095 compatible = "mediatek,mt8195-auxadc", 1096 "mediatek,mt8173-auxadc"; 1097 reg = <0 0x11002000 0 0x1000>; 1098 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1099 clock-names = "main"; 1100 #io-channel-cells = <1>; 1101 status = "disabled"; 1102 }; 1103 1104 pericfg_ao: syscon@11003000 { 1105 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 1106 reg = <0 0x11003000 0 0x1000>; 1107 #clock-cells = <1>; 1108 }; 1109 1110 spi0: spi@1100a000 { 1111 compatible = "mediatek,mt8195-spi", 1112 "mediatek,mt6765-spi"; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 reg = <0 0x1100a000 0 0x1000>; 1116 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1117 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1118 <&topckgen CLK_TOP_SPI>, 1119 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1120 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1121 status = "disabled"; 1122 }; 1123 1124 lvts_ap: thermal-sensor@1100b000 { 1125 compatible = "mediatek,mt8195-lvts-ap"; 1126 reg = <0 0x1100b000 0 0x1000>; 1127 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1128 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1129 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; 1130 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1131 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1132 #thermal-sensor-cells = <1>; 1133 }; 1134 1135 disp_pwm0: pwm@1100e000 { 1136 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1137 reg = <0 0x1100e000 0 0x1000>; 1138 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>; 1139 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 1140 #pwm-cells = <2>; 1141 clocks = <&topckgen CLK_TOP_DISP_PWM0>, 1142 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1143 clock-names = "main", "mm"; 1144 status = "disabled"; 1145 }; 1146 1147 disp_pwm1: pwm@1100f000 { 1148 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1149 reg = <0 0x1100f000 0 0x1000>; 1150 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>; 1151 #pwm-cells = <2>; 1152 clocks = <&topckgen CLK_TOP_DISP_PWM1>, 1153 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; 1154 clock-names = "main", "mm"; 1155 status = "disabled"; 1156 }; 1157 1158 spi1: spi@11010000 { 1159 compatible = "mediatek,mt8195-spi", 1160 "mediatek,mt6765-spi"; 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 reg = <0 0x11010000 0 0x1000>; 1164 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1165 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1166 <&topckgen CLK_TOP_SPI>, 1167 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1168 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1169 status = "disabled"; 1170 }; 1171 1172 spi2: spi@11012000 { 1173 compatible = "mediatek,mt8195-spi", 1174 "mediatek,mt6765-spi"; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 reg = <0 0x11012000 0 0x1000>; 1178 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1179 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1180 <&topckgen CLK_TOP_SPI>, 1181 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1182 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1183 status = "disabled"; 1184 }; 1185 1186 spi3: spi@11013000 { 1187 compatible = "mediatek,mt8195-spi", 1188 "mediatek,mt6765-spi"; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 reg = <0 0x11013000 0 0x1000>; 1192 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1193 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1194 <&topckgen CLK_TOP_SPI>, 1195 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1196 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1197 status = "disabled"; 1198 }; 1199 1200 spi4: spi@11018000 { 1201 compatible = "mediatek,mt8195-spi", 1202 "mediatek,mt6765-spi"; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 reg = <0 0x11018000 0 0x1000>; 1206 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1207 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1208 <&topckgen CLK_TOP_SPI>, 1209 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1210 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1211 status = "disabled"; 1212 }; 1213 1214 spi5: spi@11019000 { 1215 compatible = "mediatek,mt8195-spi", 1216 "mediatek,mt6765-spi"; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 reg = <0 0x11019000 0 0x1000>; 1220 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1221 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1222 <&topckgen CLK_TOP_SPI>, 1223 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1224 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1225 status = "disabled"; 1226 }; 1227 1228 spis0: spi@1101d000 { 1229 compatible = "mediatek,mt8195-spi-slave"; 1230 reg = <0 0x1101d000 0 0x1000>; 1231 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1232 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1233 clock-names = "spi"; 1234 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1235 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1236 status = "disabled"; 1237 }; 1238 1239 spis1: spi@1101e000 { 1240 compatible = "mediatek,mt8195-spi-slave"; 1241 reg = <0 0x1101e000 0 0x1000>; 1242 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1243 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1244 clock-names = "spi"; 1245 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1246 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1247 status = "disabled"; 1248 }; 1249 1250 eth: ethernet@11021000 { 1251 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; 1252 reg = <0 0x11021000 0 0x4000>; 1253 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1254 interrupt-names = "macirq"; 1255 clock-names = "axi", 1256 "apb", 1257 "mac_main", 1258 "ptp_ref", 1259 "rmii_internal", 1260 "mac_cg"; 1261 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1262 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1263 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1264 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1265 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1266 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1267 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1268 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1269 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1270 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1271 <&topckgen CLK_TOP_ETHPLL_D8>, 1272 <&topckgen CLK_TOP_ETHPLL_D10>; 1273 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; 1274 mediatek,pericfg = <&infracfg_ao>; 1275 snps,axi-config = <&stmmac_axi_setup>; 1276 snps,mtl-rx-config = <&mtl_rx_setup>; 1277 snps,mtl-tx-config = <&mtl_tx_setup>; 1278 snps,txpbl = <16>; 1279 snps,rxpbl = <16>; 1280 snps,clk-csr = <0>; 1281 status = "disabled"; 1282 1283 mdio { 1284 compatible = "snps,dwmac-mdio"; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 }; 1288 1289 stmmac_axi_setup: stmmac-axi-config { 1290 snps,wr_osr_lmt = <0x7>; 1291 snps,rd_osr_lmt = <0x7>; 1292 snps,blen = <0 0 0 0 16 8 4>; 1293 }; 1294 1295 mtl_rx_setup: rx-queues-config { 1296 snps,rx-queues-to-use = <4>; 1297 snps,rx-sched-sp; 1298 queue0 { 1299 snps,dcb-algorithm; 1300 snps,map-to-dma-channel = <0x0>; 1301 }; 1302 queue1 { 1303 snps,dcb-algorithm; 1304 snps,map-to-dma-channel = <0x0>; 1305 }; 1306 queue2 { 1307 snps,dcb-algorithm; 1308 snps,map-to-dma-channel = <0x0>; 1309 }; 1310 queue3 { 1311 snps,dcb-algorithm; 1312 snps,map-to-dma-channel = <0x0>; 1313 }; 1314 }; 1315 1316 mtl_tx_setup: tx-queues-config { 1317 snps,tx-queues-to-use = <4>; 1318 snps,tx-sched-wrr; 1319 queue0 { 1320 snps,weight = <0x10>; 1321 snps,dcb-algorithm; 1322 snps,priority = <0x0>; 1323 }; 1324 queue1 { 1325 snps,weight = <0x11>; 1326 snps,dcb-algorithm; 1327 snps,priority = <0x1>; 1328 }; 1329 queue2 { 1330 snps,weight = <0x12>; 1331 snps,dcb-algorithm; 1332 snps,priority = <0x2>; 1333 }; 1334 queue3 { 1335 snps,weight = <0x13>; 1336 snps,dcb-algorithm; 1337 snps,priority = <0x3>; 1338 }; 1339 }; 1340 }; 1341 1342 xhci0: usb@11200000 { 1343 compatible = "mediatek,mt8195-xhci", 1344 "mediatek,mtk-xhci"; 1345 reg = <0 0x11200000 0 0x1000>, 1346 <0 0x11203e00 0 0x0100>; 1347 reg-names = "mac", "ippc"; 1348 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1349 phys = <&u2port0 PHY_TYPE_USB2>, 1350 <&u3port0 PHY_TYPE_USB3>; 1351 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1352 <&topckgen CLK_TOP_SSUSB_XHCI>; 1353 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1354 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1355 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1356 <&topckgen CLK_TOP_SSUSB_REF>, 1357 <&apmixedsys CLK_APMIXED_USB1PLL>, 1358 <&clk26m>, 1359 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1360 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1361 "xhci_ck"; 1362 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1363 wakeup-source; 1364 status = "disabled"; 1365 }; 1366 1367 mmc0: mmc@11230000 { 1368 compatible = "mediatek,mt8195-mmc", 1369 "mediatek,mt8183-mmc"; 1370 reg = <0 0x11230000 0 0x10000>, 1371 <0 0x11f50000 0 0x1000>; 1372 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1373 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1374 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1375 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1376 clock-names = "source", "hclk", "source_cg"; 1377 status = "disabled"; 1378 }; 1379 1380 mmc1: mmc@11240000 { 1381 compatible = "mediatek,mt8195-mmc", 1382 "mediatek,mt8183-mmc"; 1383 reg = <0 0x11240000 0 0x1000>, 1384 <0 0x11c70000 0 0x1000>; 1385 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1386 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1387 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1388 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1389 clock-names = "source", "hclk", "source_cg"; 1390 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1391 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1392 status = "disabled"; 1393 }; 1394 1395 mmc2: mmc@11250000 { 1396 compatible = "mediatek,mt8195-mmc", 1397 "mediatek,mt8183-mmc"; 1398 reg = <0 0x11250000 0 0x1000>, 1399 <0 0x11e60000 0 0x1000>; 1400 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1401 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1402 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1403 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1404 clock-names = "source", "hclk", "source_cg"; 1405 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1406 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1407 status = "disabled"; 1408 }; 1409 1410 lvts_mcu: thermal-sensor@11278000 { 1411 compatible = "mediatek,mt8195-lvts-mcu"; 1412 reg = <0 0x11278000 0 0x1000>; 1413 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 1414 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1415 resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; 1416 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1417 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1418 #thermal-sensor-cells = <1>; 1419 }; 1420 1421 xhci1: usb@11290000 { 1422 compatible = "mediatek,mt8195-xhci", 1423 "mediatek,mtk-xhci"; 1424 reg = <0 0x11290000 0 0x1000>, 1425 <0 0x11293e00 0 0x0100>; 1426 reg-names = "mac", "ippc"; 1427 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1428 phys = <&u2port1 PHY_TYPE_USB2>; 1429 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1430 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1431 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1432 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1433 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1434 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1435 <&apmixedsys CLK_APMIXED_USB1PLL>, 1436 <&clk26m>, 1437 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1438 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1439 "xhci_ck"; 1440 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1441 wakeup-source; 1442 status = "disabled"; 1443 }; 1444 1445 xhci2: usb@112a0000 { 1446 compatible = "mediatek,mt8195-xhci", 1447 "mediatek,mtk-xhci"; 1448 reg = <0 0x112a0000 0 0x1000>, 1449 <0 0x112a3e00 0 0x0100>; 1450 reg-names = "mac", "ippc"; 1451 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1452 phys = <&u2port2 PHY_TYPE_USB2>; 1453 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 1454 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1455 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1456 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1457 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1458 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1459 <&clk26m>, 1460 <&clk26m>, 1461 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1462 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1463 "xhci_ck"; 1464 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1465 wakeup-source; 1466 status = "disabled"; 1467 }; 1468 1469 xhci3: usb@112b0000 { 1470 compatible = "mediatek,mt8195-xhci", 1471 "mediatek,mtk-xhci"; 1472 reg = <0 0x112b0000 0 0x1000>, 1473 <0 0x112b3e00 0 0x0100>; 1474 reg-names = "mac", "ippc"; 1475 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1476 phys = <&u2port3 PHY_TYPE_USB2>; 1477 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1478 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1479 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1480 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1481 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1482 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1483 <&clk26m>, 1484 <&clk26m>, 1485 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1486 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1487 "xhci_ck"; 1488 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1489 wakeup-source; 1490 status = "disabled"; 1491 }; 1492 1493 pcie0: pcie@112f0000 { 1494 compatible = "mediatek,mt8195-pcie", 1495 "mediatek,mt8192-pcie"; 1496 device_type = "pci"; 1497 #address-cells = <3>; 1498 #size-cells = <2>; 1499 reg = <0 0x112f0000 0 0x4000>; 1500 reg-names = "pcie-mac"; 1501 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1502 bus-range = <0x00 0xff>; 1503 ranges = <0x81000000 0 0x20000000 1504 0x0 0x20000000 0 0x200000>, 1505 <0x82000000 0 0x20200000 1506 0x0 0x20200000 0 0x3e00000>; 1507 1508 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1509 iommu-map-mask = <0x0>; 1510 1511 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1512 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1513 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1514 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1515 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1516 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1517 clock-names = "pl_250m", "tl_26m", "tl_96m", 1518 "tl_32k", "peri_26m", "peri_mem"; 1519 assigned-clocks = <&topckgen CLK_TOP_TL>; 1520 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1521 1522 phys = <&pciephy>; 1523 phy-names = "pcie-phy"; 1524 1525 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1526 1527 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; 1528 reset-names = "mac"; 1529 1530 #interrupt-cells = <1>; 1531 interrupt-map-mask = <0 0 0 7>; 1532 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1533 <0 0 0 2 &pcie_intc0 1>, 1534 <0 0 0 3 &pcie_intc0 2>, 1535 <0 0 0 4 &pcie_intc0 3>; 1536 status = "disabled"; 1537 1538 pcie_intc0: interrupt-controller { 1539 interrupt-controller; 1540 #address-cells = <0>; 1541 #interrupt-cells = <1>; 1542 }; 1543 }; 1544 1545 pcie1: pcie@112f8000 { 1546 compatible = "mediatek,mt8195-pcie", 1547 "mediatek,mt8192-pcie"; 1548 device_type = "pci"; 1549 #address-cells = <3>; 1550 #size-cells = <2>; 1551 reg = <0 0x112f8000 0 0x4000>; 1552 reg-names = "pcie-mac"; 1553 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1554 bus-range = <0x00 0xff>; 1555 ranges = <0x81000000 0 0x24000000 1556 0x0 0x24000000 0 0x200000>, 1557 <0x82000000 0 0x24200000 1558 0x0 0x24200000 0 0x3e00000>; 1559 1560 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1561 iommu-map-mask = <0x0>; 1562 1563 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1564 <&clk26m>, 1565 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, 1566 <&clk26m>, 1567 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, 1568 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1569 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1570 clock-names = "pl_250m", "tl_26m", "tl_96m", 1571 "tl_32k", "peri_26m", "peri_mem"; 1572 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1573 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1574 1575 phys = <&u3port1 PHY_TYPE_PCIE>; 1576 phy-names = "pcie-phy"; 1577 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1578 1579 #interrupt-cells = <1>; 1580 interrupt-map-mask = <0 0 0 7>; 1581 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1582 <0 0 0 2 &pcie_intc1 1>, 1583 <0 0 0 3 &pcie_intc1 2>, 1584 <0 0 0 4 &pcie_intc1 3>; 1585 status = "disabled"; 1586 1587 pcie_intc1: interrupt-controller { 1588 interrupt-controller; 1589 #address-cells = <0>; 1590 #interrupt-cells = <1>; 1591 }; 1592 }; 1593 1594 nor_flash: spi@1132c000 { 1595 compatible = "mediatek,mt8195-nor", 1596 "mediatek,mt8173-nor"; 1597 reg = <0 0x1132c000 0 0x1000>; 1598 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1599 clocks = <&topckgen CLK_TOP_SPINOR>, 1600 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1601 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1602 clock-names = "spi", "sf", "axi"; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 status = "disabled"; 1606 }; 1607 1608 efuse: efuse@11c10000 { 1609 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1610 reg = <0 0x11c10000 0 0x1000>; 1611 #address-cells = <1>; 1612 #size-cells = <1>; 1613 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1614 reg = <0x184 0x1>; 1615 bits = <0 5>; 1616 }; 1617 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1618 reg = <0x184 0x2>; 1619 bits = <5 5>; 1620 }; 1621 u3_intr_p0: usb3-intr@185 { 1622 reg = <0x185 0x1>; 1623 bits = <2 6>; 1624 }; 1625 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1626 reg = <0x186 0x1>; 1627 bits = <0 5>; 1628 }; 1629 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1630 reg = <0x186 0x2>; 1631 bits = <5 5>; 1632 }; 1633 comb_intr_p1: usb3-intr@187 { 1634 reg = <0x187 0x1>; 1635 bits = <2 6>; 1636 }; 1637 u2_intr_p0: usb2-intr-p0@188,1 { 1638 reg = <0x188 0x1>; 1639 bits = <0 5>; 1640 }; 1641 u2_intr_p1: usb2-intr-p1@188,2 { 1642 reg = <0x188 0x2>; 1643 bits = <5 5>; 1644 }; 1645 u2_intr_p2: usb2-intr-p2@189,1 { 1646 reg = <0x189 0x1>; 1647 bits = <2 5>; 1648 }; 1649 u2_intr_p3: usb2-intr-p3@189,2 { 1650 reg = <0x189 0x2>; 1651 bits = <7 5>; 1652 }; 1653 pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1654 reg = <0x190 0x1>; 1655 bits = <0 4>; 1656 }; 1657 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1658 reg = <0x190 0x1>; 1659 bits = <4 4>; 1660 }; 1661 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1662 reg = <0x191 0x1>; 1663 bits = <0 4>; 1664 }; 1665 pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1666 reg = <0x191 0x1>; 1667 bits = <4 4>; 1668 }; 1669 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1670 reg = <0x192 0x1>; 1671 bits = <0 4>; 1672 }; 1673 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1674 reg = <0x192 0x1>; 1675 bits = <4 4>; 1676 }; 1677 pciephy_glb_intr: pciephy-glb-intr@193 { 1678 reg = <0x193 0x1>; 1679 bits = <0 4>; 1680 }; 1681 dp_calibration: dp-data@1ac { 1682 reg = <0x1ac 0x10>; 1683 }; 1684 lvts_efuse_data1: lvts1-calib@1bc { 1685 reg = <0x1bc 0x14>; 1686 }; 1687 lvts_efuse_data2: lvts2-calib@1d0 { 1688 reg = <0x1d0 0x38>; 1689 }; 1690 }; 1691 1692 u3phy2: t-phy@11c40000 { 1693 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1694 #address-cells = <1>; 1695 #size-cells = <1>; 1696 ranges = <0 0 0x11c40000 0x700>; 1697 status = "disabled"; 1698 1699 u2port2: usb-phy@0 { 1700 reg = <0x0 0x700>; 1701 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1702 clock-names = "ref"; 1703 #phy-cells = <1>; 1704 }; 1705 }; 1706 1707 u3phy3: t-phy@11c50000 { 1708 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1709 #address-cells = <1>; 1710 #size-cells = <1>; 1711 ranges = <0 0 0x11c50000 0x700>; 1712 status = "disabled"; 1713 1714 u2port3: usb-phy@0 { 1715 reg = <0x0 0x700>; 1716 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1717 clock-names = "ref"; 1718 #phy-cells = <1>; 1719 }; 1720 }; 1721 1722 i2c5: i2c@11d00000 { 1723 compatible = "mediatek,mt8195-i2c", 1724 "mediatek,mt8192-i2c"; 1725 reg = <0 0x11d00000 0 0x1000>, 1726 <0 0x10220580 0 0x80>; 1727 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1728 clock-div = <1>; 1729 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1730 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1731 clock-names = "main", "dma"; 1732 #address-cells = <1>; 1733 #size-cells = <0>; 1734 status = "disabled"; 1735 }; 1736 1737 i2c6: i2c@11d01000 { 1738 compatible = "mediatek,mt8195-i2c", 1739 "mediatek,mt8192-i2c"; 1740 reg = <0 0x11d01000 0 0x1000>, 1741 <0 0x10220600 0 0x80>; 1742 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1743 clock-div = <1>; 1744 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1745 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1746 clock-names = "main", "dma"; 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 status = "disabled"; 1750 }; 1751 1752 i2c7: i2c@11d02000 { 1753 compatible = "mediatek,mt8195-i2c", 1754 "mediatek,mt8192-i2c"; 1755 reg = <0 0x11d02000 0 0x1000>, 1756 <0 0x10220680 0 0x80>; 1757 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1758 clock-div = <1>; 1759 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1760 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1761 clock-names = "main", "dma"; 1762 #address-cells = <1>; 1763 #size-cells = <0>; 1764 status = "disabled"; 1765 }; 1766 1767 imp_iic_wrap_s: clock-controller@11d03000 { 1768 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1769 reg = <0 0x11d03000 0 0x1000>; 1770 #clock-cells = <1>; 1771 }; 1772 1773 i2c0: i2c@11e00000 { 1774 compatible = "mediatek,mt8195-i2c", 1775 "mediatek,mt8192-i2c"; 1776 reg = <0 0x11e00000 0 0x1000>, 1777 <0 0x10220080 0 0x80>; 1778 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1779 clock-div = <1>; 1780 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1781 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1782 clock-names = "main", "dma"; 1783 #address-cells = <1>; 1784 #size-cells = <0>; 1785 status = "disabled"; 1786 }; 1787 1788 i2c1: i2c@11e01000 { 1789 compatible = "mediatek,mt8195-i2c", 1790 "mediatek,mt8192-i2c"; 1791 reg = <0 0x11e01000 0 0x1000>, 1792 <0 0x10220200 0 0x80>; 1793 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1794 clock-div = <1>; 1795 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1796 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1797 clock-names = "main", "dma"; 1798 #address-cells = <1>; 1799 #size-cells = <0>; 1800 status = "disabled"; 1801 }; 1802 1803 i2c2: i2c@11e02000 { 1804 compatible = "mediatek,mt8195-i2c", 1805 "mediatek,mt8192-i2c"; 1806 reg = <0 0x11e02000 0 0x1000>, 1807 <0 0x10220380 0 0x80>; 1808 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1809 clock-div = <1>; 1810 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1811 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1812 clock-names = "main", "dma"; 1813 #address-cells = <1>; 1814 #size-cells = <0>; 1815 status = "disabled"; 1816 }; 1817 1818 i2c3: i2c@11e03000 { 1819 compatible = "mediatek,mt8195-i2c", 1820 "mediatek,mt8192-i2c"; 1821 reg = <0 0x11e03000 0 0x1000>, 1822 <0 0x10220480 0 0x80>; 1823 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1824 clock-div = <1>; 1825 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1826 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1827 clock-names = "main", "dma"; 1828 #address-cells = <1>; 1829 #size-cells = <0>; 1830 status = "disabled"; 1831 }; 1832 1833 i2c4: i2c@11e04000 { 1834 compatible = "mediatek,mt8195-i2c", 1835 "mediatek,mt8192-i2c"; 1836 reg = <0 0x11e04000 0 0x1000>, 1837 <0 0x10220500 0 0x80>; 1838 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1839 clock-div = <1>; 1840 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1841 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1842 clock-names = "main", "dma"; 1843 #address-cells = <1>; 1844 #size-cells = <0>; 1845 status = "disabled"; 1846 }; 1847 1848 imp_iic_wrap_w: clock-controller@11e05000 { 1849 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1850 reg = <0 0x11e05000 0 0x1000>; 1851 #clock-cells = <1>; 1852 }; 1853 1854 u3phy1: t-phy@11e30000 { 1855 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1856 #address-cells = <1>; 1857 #size-cells = <1>; 1858 ranges = <0 0 0x11e30000 0xe00>; 1859 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 1860 status = "disabled"; 1861 1862 u2port1: usb-phy@0 { 1863 reg = <0x0 0x700>; 1864 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1865 <&clk26m>; 1866 clock-names = "ref", "da_ref"; 1867 #phy-cells = <1>; 1868 }; 1869 1870 u3port1: usb-phy@700 { 1871 reg = <0x700 0x700>; 1872 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1873 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1874 clock-names = "ref", "da_ref"; 1875 nvmem-cells = <&comb_intr_p1>, 1876 <&comb_rx_imp_p1>, 1877 <&comb_tx_imp_p1>; 1878 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1879 #phy-cells = <1>; 1880 }; 1881 }; 1882 1883 u3phy0: t-phy@11e40000 { 1884 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1885 #address-cells = <1>; 1886 #size-cells = <1>; 1887 ranges = <0 0 0x11e40000 0xe00>; 1888 status = "disabled"; 1889 1890 u2port0: usb-phy@0 { 1891 reg = <0x0 0x700>; 1892 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1893 <&clk26m>; 1894 clock-names = "ref", "da_ref"; 1895 #phy-cells = <1>; 1896 }; 1897 1898 u3port0: usb-phy@700 { 1899 reg = <0x700 0x700>; 1900 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1901 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1902 clock-names = "ref", "da_ref"; 1903 nvmem-cells = <&u3_intr_p0>, 1904 <&u3_rx_imp_p0>, 1905 <&u3_tx_imp_p0>; 1906 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1907 #phy-cells = <1>; 1908 }; 1909 }; 1910 1911 pciephy: phy@11e80000 { 1912 compatible = "mediatek,mt8195-pcie-phy"; 1913 reg = <0 0x11e80000 0 0x10000>; 1914 reg-names = "sif"; 1915 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 1916 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 1917 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 1918 <&pciephy_rx_ln1>; 1919 nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 1920 "tx_ln0_nmos", "rx_ln0", 1921 "tx_ln1_pmos", "tx_ln1_nmos", 1922 "rx_ln1"; 1923 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 1924 #phy-cells = <0>; 1925 status = "disabled"; 1926 }; 1927 1928 ufsphy: ufs-phy@11fa0000 { 1929 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1930 reg = <0 0x11fa0000 0 0xc000>; 1931 clocks = <&clk26m>, <&clk26m>; 1932 clock-names = "unipro", "mp"; 1933 #phy-cells = <0>; 1934 status = "disabled"; 1935 }; 1936 1937 gpu: gpu@13000000 { 1938 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali", 1939 "arm,mali-valhall-jm"; 1940 reg = <0 0x13000000 0 0x4000>; 1941 1942 clocks = <&mfgcfg CLK_MFG_BG3D>; 1943 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 1944 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 1945 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>; 1946 interrupt-names = "job", "mmu", "gpu"; 1947 operating-points-v2 = <&gpu_opp_table>; 1948 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>, 1949 <&spm MT8195_POWER_DOMAIN_MFG3>, 1950 <&spm MT8195_POWER_DOMAIN_MFG4>, 1951 <&spm MT8195_POWER_DOMAIN_MFG5>, 1952 <&spm MT8195_POWER_DOMAIN_MFG6>; 1953 power-domain-names = "core0", "core1", "core2", "core3", "core4"; 1954 status = "disabled"; 1955 }; 1956 1957 mfgcfg: clock-controller@13fbf000 { 1958 compatible = "mediatek,mt8195-mfgcfg"; 1959 reg = <0 0x13fbf000 0 0x1000>; 1960 #clock-cells = <1>; 1961 }; 1962 1963 vppsys0: syscon@14000000 { 1964 compatible = "mediatek,mt8195-vppsys0", "syscon"; 1965 reg = <0 0x14000000 0 0x1000>; 1966 #clock-cells = <1>; 1967 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>; 1968 }; 1969 1970 mutex@1400f000 { 1971 compatible = "mediatek,mt8195-vpp-mutex"; 1972 reg = <0 0x1400f000 0 0x1000>; 1973 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>; 1974 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; 1975 clocks = <&vppsys0 CLK_VPP0_MUTEX>; 1976 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1977 }; 1978 1979 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 1980 compatible = "mediatek,mt8195-smi-sub-common"; 1981 reg = <0 0x14010000 0 0x1000>; 1982 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1983 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1984 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1985 clock-names = "apb", "smi", "gals0"; 1986 mediatek,smi = <&smi_common_vpp>; 1987 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1988 }; 1989 1990 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 1991 compatible = "mediatek,mt8195-smi-sub-common"; 1992 reg = <0 0x14011000 0 0x1000>; 1993 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1994 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1995 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 1996 clock-names = "apb", "smi", "gals0"; 1997 mediatek,smi = <&smi_common_vpp>; 1998 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1999 }; 2000 2001 smi_common_vpp: smi@14012000 { 2002 compatible = "mediatek,mt8195-smi-common-vpp"; 2003 reg = <0 0x14012000 0 0x1000>; 2004 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2005 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2006 <&vppsys0 CLK_VPP0_SMI_RSI>, 2007 <&vppsys0 CLK_VPP0_SMI_RSI>; 2008 clock-names = "apb", "smi", "gals0", "gals1"; 2009 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2010 }; 2011 2012 larb4: larb@14013000 { 2013 compatible = "mediatek,mt8195-smi-larb"; 2014 reg = <0 0x14013000 0 0x1000>; 2015 mediatek,larb-id = <4>; 2016 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2017 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2018 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 2019 clock-names = "apb", "smi"; 2020 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2021 }; 2022 2023 iommu_vpp: iommu@14018000 { 2024 compatible = "mediatek,mt8195-iommu-vpp"; 2025 reg = <0 0x14018000 0 0x1000>; 2026 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 2027 &larb12 &larb14 &larb16 &larb18 2028 &larb20 &larb22 &larb23 &larb26 2029 &larb27>; 2030 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 2031 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 2032 clock-names = "bclk"; 2033 #iommu-cells = <1>; 2034 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2035 }; 2036 2037 wpesys: clock-controller@14e00000 { 2038 compatible = "mediatek,mt8195-wpesys"; 2039 reg = <0 0x14e00000 0 0x1000>; 2040 #clock-cells = <1>; 2041 }; 2042 2043 wpesys_vpp0: clock-controller@14e02000 { 2044 compatible = "mediatek,mt8195-wpesys_vpp0"; 2045 reg = <0 0x14e02000 0 0x1000>; 2046 #clock-cells = <1>; 2047 }; 2048 2049 wpesys_vpp1: clock-controller@14e03000 { 2050 compatible = "mediatek,mt8195-wpesys_vpp1"; 2051 reg = <0 0x14e03000 0 0x1000>; 2052 #clock-cells = <1>; 2053 }; 2054 2055 larb7: larb@14e04000 { 2056 compatible = "mediatek,mt8195-smi-larb"; 2057 reg = <0 0x14e04000 0 0x1000>; 2058 mediatek,larb-id = <7>; 2059 mediatek,smi = <&smi_common_vdo>; 2060 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 2061 <&wpesys CLK_WPE_SMI_LARB7>; 2062 clock-names = "apb", "smi"; 2063 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2064 }; 2065 2066 larb8: larb@14e05000 { 2067 compatible = "mediatek,mt8195-smi-larb"; 2068 reg = <0 0x14e05000 0 0x1000>; 2069 mediatek,larb-id = <8>; 2070 mediatek,smi = <&smi_common_vpp>; 2071 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 2072 <&wpesys CLK_WPE_SMI_LARB8>, 2073 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2074 clock-names = "apb", "smi", "gals"; 2075 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2076 }; 2077 2078 vppsys1: syscon@14f00000 { 2079 compatible = "mediatek,mt8195-vppsys1", "syscon"; 2080 reg = <0 0x14f00000 0 0x1000>; 2081 #clock-cells = <1>; 2082 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>; 2083 }; 2084 2085 mutex@14f01000 { 2086 compatible = "mediatek,mt8195-vpp-mutex"; 2087 reg = <0 0x14f01000 0 0x1000>; 2088 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 2089 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; 2090 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; 2091 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2092 }; 2093 2094 larb5: larb@14f02000 { 2095 compatible = "mediatek,mt8195-smi-larb"; 2096 reg = <0 0x14f02000 0 0x1000>; 2097 mediatek,larb-id = <5>; 2098 mediatek,smi = <&smi_common_vdo>; 2099 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2100 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2101 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 2102 clock-names = "apb", "smi", "gals"; 2103 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2104 }; 2105 2106 larb6: larb@14f03000 { 2107 compatible = "mediatek,mt8195-smi-larb"; 2108 reg = <0 0x14f03000 0 0x1000>; 2109 mediatek,larb-id = <6>; 2110 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2111 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2112 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2113 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 2114 clock-names = "apb", "smi", "gals"; 2115 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2116 }; 2117 2118 imgsys: clock-controller@15000000 { 2119 compatible = "mediatek,mt8195-imgsys"; 2120 reg = <0 0x15000000 0 0x1000>; 2121 #clock-cells = <1>; 2122 }; 2123 2124 larb9: larb@15001000 { 2125 compatible = "mediatek,mt8195-smi-larb"; 2126 reg = <0 0x15001000 0 0x1000>; 2127 mediatek,larb-id = <9>; 2128 mediatek,smi = <&smi_sub_common_img1_3x1>; 2129 clocks = <&imgsys CLK_IMG_LARB9>, 2130 <&imgsys CLK_IMG_LARB9>, 2131 <&imgsys CLK_IMG_GALS>; 2132 clock-names = "apb", "smi", "gals"; 2133 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2134 }; 2135 2136 smi_sub_common_img0_3x1: smi@15002000 { 2137 compatible = "mediatek,mt8195-smi-sub-common"; 2138 reg = <0 0x15002000 0 0x1000>; 2139 clocks = <&imgsys CLK_IMG_IPE>, 2140 <&imgsys CLK_IMG_IPE>, 2141 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2142 clock-names = "apb", "smi", "gals0"; 2143 mediatek,smi = <&smi_common_vpp>; 2144 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2145 }; 2146 2147 smi_sub_common_img1_3x1: smi@15003000 { 2148 compatible = "mediatek,mt8195-smi-sub-common"; 2149 reg = <0 0x15003000 0 0x1000>; 2150 clocks = <&imgsys CLK_IMG_LARB9>, 2151 <&imgsys CLK_IMG_LARB9>, 2152 <&imgsys CLK_IMG_GALS>; 2153 clock-names = "apb", "smi", "gals0"; 2154 mediatek,smi = <&smi_common_vdo>; 2155 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2156 }; 2157 2158 imgsys1_dip_top: clock-controller@15110000 { 2159 compatible = "mediatek,mt8195-imgsys1_dip_top"; 2160 reg = <0 0x15110000 0 0x1000>; 2161 #clock-cells = <1>; 2162 }; 2163 2164 larb10: larb@15120000 { 2165 compatible = "mediatek,mt8195-smi-larb"; 2166 reg = <0 0x15120000 0 0x1000>; 2167 mediatek,larb-id = <10>; 2168 mediatek,smi = <&smi_sub_common_img1_3x1>; 2169 clocks = <&imgsys CLK_IMG_DIP0>, 2170 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 2171 clock-names = "apb", "smi"; 2172 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2173 }; 2174 2175 imgsys1_dip_nr: clock-controller@15130000 { 2176 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 2177 reg = <0 0x15130000 0 0x1000>; 2178 #clock-cells = <1>; 2179 }; 2180 2181 imgsys1_wpe: clock-controller@15220000 { 2182 compatible = "mediatek,mt8195-imgsys1_wpe"; 2183 reg = <0 0x15220000 0 0x1000>; 2184 #clock-cells = <1>; 2185 }; 2186 2187 larb11: larb@15230000 { 2188 compatible = "mediatek,mt8195-smi-larb"; 2189 reg = <0 0x15230000 0 0x1000>; 2190 mediatek,larb-id = <11>; 2191 mediatek,smi = <&smi_sub_common_img1_3x1>; 2192 clocks = <&imgsys CLK_IMG_WPE0>, 2193 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 2194 clock-names = "apb", "smi"; 2195 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2196 }; 2197 2198 ipesys: clock-controller@15330000 { 2199 compatible = "mediatek,mt8195-ipesys"; 2200 reg = <0 0x15330000 0 0x1000>; 2201 #clock-cells = <1>; 2202 }; 2203 2204 larb12: larb@15340000 { 2205 compatible = "mediatek,mt8195-smi-larb"; 2206 reg = <0 0x15340000 0 0x1000>; 2207 mediatek,larb-id = <12>; 2208 mediatek,smi = <&smi_sub_common_img0_3x1>; 2209 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 2210 <&ipesys CLK_IPE_SMI_LARB12>; 2211 clock-names = "apb", "smi"; 2212 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 2213 }; 2214 2215 camsys: clock-controller@16000000 { 2216 compatible = "mediatek,mt8195-camsys"; 2217 reg = <0 0x16000000 0 0x1000>; 2218 #clock-cells = <1>; 2219 }; 2220 2221 larb13: larb@16001000 { 2222 compatible = "mediatek,mt8195-smi-larb"; 2223 reg = <0 0x16001000 0 0x1000>; 2224 mediatek,larb-id = <13>; 2225 mediatek,smi = <&smi_sub_common_cam_4x1>; 2226 clocks = <&camsys CLK_CAM_LARB13>, 2227 <&camsys CLK_CAM_LARB13>, 2228 <&camsys CLK_CAM_CAM2MM0_GALS>; 2229 clock-names = "apb", "smi", "gals"; 2230 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2231 }; 2232 2233 larb14: larb@16002000 { 2234 compatible = "mediatek,mt8195-smi-larb"; 2235 reg = <0 0x16002000 0 0x1000>; 2236 mediatek,larb-id = <14>; 2237 mediatek,smi = <&smi_sub_common_cam_7x1>; 2238 clocks = <&camsys CLK_CAM_LARB14>, 2239 <&camsys CLK_CAM_LARB14>; 2240 clock-names = "apb", "smi"; 2241 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2242 }; 2243 2244 smi_sub_common_cam_4x1: smi@16004000 { 2245 compatible = "mediatek,mt8195-smi-sub-common"; 2246 reg = <0 0x16004000 0 0x1000>; 2247 clocks = <&camsys CLK_CAM_LARB13>, 2248 <&camsys CLK_CAM_LARB13>, 2249 <&camsys CLK_CAM_CAM2MM0_GALS>; 2250 clock-names = "apb", "smi", "gals0"; 2251 mediatek,smi = <&smi_common_vdo>; 2252 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2253 }; 2254 2255 smi_sub_common_cam_7x1: smi@16005000 { 2256 compatible = "mediatek,mt8195-smi-sub-common"; 2257 reg = <0 0x16005000 0 0x1000>; 2258 clocks = <&camsys CLK_CAM_LARB14>, 2259 <&camsys CLK_CAM_CAM2MM1_GALS>, 2260 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2261 clock-names = "apb", "smi", "gals0"; 2262 mediatek,smi = <&smi_common_vpp>; 2263 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2264 }; 2265 2266 larb16: larb@16012000 { 2267 compatible = "mediatek,mt8195-smi-larb"; 2268 reg = <0 0x16012000 0 0x1000>; 2269 mediatek,larb-id = <16>; 2270 mediatek,smi = <&smi_sub_common_cam_7x1>; 2271 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 2272 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 2273 clock-names = "apb", "smi"; 2274 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2275 }; 2276 2277 larb17: larb@16013000 { 2278 compatible = "mediatek,mt8195-smi-larb"; 2279 reg = <0 0x16013000 0 0x1000>; 2280 mediatek,larb-id = <17>; 2281 mediatek,smi = <&smi_sub_common_cam_4x1>; 2282 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 2283 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 2284 clock-names = "apb", "smi"; 2285 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2286 }; 2287 2288 larb27: larb@16014000 { 2289 compatible = "mediatek,mt8195-smi-larb"; 2290 reg = <0 0x16014000 0 0x1000>; 2291 mediatek,larb-id = <27>; 2292 mediatek,smi = <&smi_sub_common_cam_7x1>; 2293 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 2294 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 2295 clock-names = "apb", "smi"; 2296 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2297 }; 2298 2299 larb28: larb@16015000 { 2300 compatible = "mediatek,mt8195-smi-larb"; 2301 reg = <0 0x16015000 0 0x1000>; 2302 mediatek,larb-id = <28>; 2303 mediatek,smi = <&smi_sub_common_cam_4x1>; 2304 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 2305 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 2306 clock-names = "apb", "smi"; 2307 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2308 }; 2309 2310 camsys_rawa: clock-controller@1604f000 { 2311 compatible = "mediatek,mt8195-camsys_rawa"; 2312 reg = <0 0x1604f000 0 0x1000>; 2313 #clock-cells = <1>; 2314 }; 2315 2316 camsys_yuva: clock-controller@1606f000 { 2317 compatible = "mediatek,mt8195-camsys_yuva"; 2318 reg = <0 0x1606f000 0 0x1000>; 2319 #clock-cells = <1>; 2320 }; 2321 2322 camsys_rawb: clock-controller@1608f000 { 2323 compatible = "mediatek,mt8195-camsys_rawb"; 2324 reg = <0 0x1608f000 0 0x1000>; 2325 #clock-cells = <1>; 2326 }; 2327 2328 camsys_yuvb: clock-controller@160af000 { 2329 compatible = "mediatek,mt8195-camsys_yuvb"; 2330 reg = <0 0x160af000 0 0x1000>; 2331 #clock-cells = <1>; 2332 }; 2333 2334 camsys_mraw: clock-controller@16140000 { 2335 compatible = "mediatek,mt8195-camsys_mraw"; 2336 reg = <0 0x16140000 0 0x1000>; 2337 #clock-cells = <1>; 2338 }; 2339 2340 larb25: larb@16141000 { 2341 compatible = "mediatek,mt8195-smi-larb"; 2342 reg = <0 0x16141000 0 0x1000>; 2343 mediatek,larb-id = <25>; 2344 mediatek,smi = <&smi_sub_common_cam_4x1>; 2345 clocks = <&camsys CLK_CAM_LARB13>, 2346 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2347 <&camsys CLK_CAM_CAM2MM0_GALS>; 2348 clock-names = "apb", "smi", "gals"; 2349 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2350 }; 2351 2352 larb26: larb@16142000 { 2353 compatible = "mediatek,mt8195-smi-larb"; 2354 reg = <0 0x16142000 0 0x1000>; 2355 mediatek,larb-id = <26>; 2356 mediatek,smi = <&smi_sub_common_cam_7x1>; 2357 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2358 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 2359 clock-names = "apb", "smi"; 2360 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2361 2362 }; 2363 2364 ccusys: clock-controller@17200000 { 2365 compatible = "mediatek,mt8195-ccusys"; 2366 reg = <0 0x17200000 0 0x1000>; 2367 #clock-cells = <1>; 2368 }; 2369 2370 larb18: larb@17201000 { 2371 compatible = "mediatek,mt8195-smi-larb"; 2372 reg = <0 0x17201000 0 0x1000>; 2373 mediatek,larb-id = <18>; 2374 mediatek,smi = <&smi_sub_common_cam_7x1>; 2375 clocks = <&ccusys CLK_CCU_LARB18>, 2376 <&ccusys CLK_CCU_LARB18>; 2377 clock-names = "apb", "smi"; 2378 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2379 }; 2380 2381 video-codec@18000000 { 2382 compatible = "mediatek,mt8195-vcodec-dec"; 2383 mediatek,scp = <&scp>; 2384 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; 2385 #address-cells = <2>; 2386 #size-cells = <2>; 2387 reg = <0 0x18000000 0 0x1000>, 2388 <0 0x18004000 0 0x1000>; 2389 ranges = <0 0 0 0x18000000 0 0x26000>; 2390 2391 video-codec@2000 { 2392 compatible = "mediatek,mtk-vcodec-lat-soc"; 2393 reg = <0 0x2000 0 0x800>; 2394 iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, 2395 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; 2396 clocks = <&topckgen CLK_TOP_VDEC>, 2397 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2398 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2399 <&topckgen CLK_TOP_UNIVPLL_D4>; 2400 clock-names = "sel", "vdec", "lat", "top"; 2401 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2402 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2403 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2404 }; 2405 2406 video-codec@10000 { 2407 compatible = "mediatek,mtk-vcodec-lat"; 2408 reg = <0 0x10000 0 0x800>; 2409 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; 2410 iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, 2411 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, 2412 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, 2413 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, 2414 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, 2415 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; 2416 clocks = <&topckgen CLK_TOP_VDEC>, 2417 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2418 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2419 <&topckgen CLK_TOP_UNIVPLL_D4>; 2420 clock-names = "sel", "vdec", "lat", "top"; 2421 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2422 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2423 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2424 }; 2425 2426 video-codec@25000 { 2427 compatible = "mediatek,mtk-vcodec-core"; 2428 reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ 2429 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; 2430 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, 2431 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, 2432 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, 2433 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, 2434 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, 2435 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, 2436 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, 2437 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, 2438 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, 2439 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; 2440 clocks = <&topckgen CLK_TOP_VDEC>, 2441 <&vdecsys CLK_VDEC_VDEC>, 2442 <&vdecsys CLK_VDEC_LAT>, 2443 <&topckgen CLK_TOP_UNIVPLL_D4>; 2444 clock-names = "sel", "vdec", "lat", "top"; 2445 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2446 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2447 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2448 }; 2449 }; 2450 2451 larb24: larb@1800d000 { 2452 compatible = "mediatek,mt8195-smi-larb"; 2453 reg = <0 0x1800d000 0 0x1000>; 2454 mediatek,larb-id = <24>; 2455 mediatek,smi = <&smi_common_vdo>; 2456 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 2457 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2458 clock-names = "apb", "smi"; 2459 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2460 }; 2461 2462 larb23: larb@1800e000 { 2463 compatible = "mediatek,mt8195-smi-larb"; 2464 reg = <0 0x1800e000 0 0x1000>; 2465 mediatek,larb-id = <23>; 2466 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2467 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2468 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2469 clock-names = "apb", "smi"; 2470 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2471 }; 2472 2473 vdecsys_soc: clock-controller@1800f000 { 2474 compatible = "mediatek,mt8195-vdecsys_soc"; 2475 reg = <0 0x1800f000 0 0x1000>; 2476 #clock-cells = <1>; 2477 }; 2478 2479 larb21: larb@1802e000 { 2480 compatible = "mediatek,mt8195-smi-larb"; 2481 reg = <0 0x1802e000 0 0x1000>; 2482 mediatek,larb-id = <21>; 2483 mediatek,smi = <&smi_common_vdo>; 2484 clocks = <&vdecsys CLK_VDEC_LARB1>, 2485 <&vdecsys CLK_VDEC_LARB1>; 2486 clock-names = "apb", "smi"; 2487 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2488 }; 2489 2490 vdecsys: clock-controller@1802f000 { 2491 compatible = "mediatek,mt8195-vdecsys"; 2492 reg = <0 0x1802f000 0 0x1000>; 2493 #clock-cells = <1>; 2494 }; 2495 2496 larb22: larb@1803e000 { 2497 compatible = "mediatek,mt8195-smi-larb"; 2498 reg = <0 0x1803e000 0 0x1000>; 2499 mediatek,larb-id = <22>; 2500 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2501 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2502 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 2503 clock-names = "apb", "smi"; 2504 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2505 }; 2506 2507 vdecsys_core1: clock-controller@1803f000 { 2508 compatible = "mediatek,mt8195-vdecsys_core1"; 2509 reg = <0 0x1803f000 0 0x1000>; 2510 #clock-cells = <1>; 2511 }; 2512 2513 apusys_pll: clock-controller@190f3000 { 2514 compatible = "mediatek,mt8195-apusys_pll"; 2515 reg = <0 0x190f3000 0 0x1000>; 2516 #clock-cells = <1>; 2517 }; 2518 2519 vencsys: clock-controller@1a000000 { 2520 compatible = "mediatek,mt8195-vencsys"; 2521 reg = <0 0x1a000000 0 0x1000>; 2522 #clock-cells = <1>; 2523 }; 2524 2525 larb19: larb@1a010000 { 2526 compatible = "mediatek,mt8195-smi-larb"; 2527 reg = <0 0x1a010000 0 0x1000>; 2528 mediatek,larb-id = <19>; 2529 mediatek,smi = <&smi_common_vdo>; 2530 clocks = <&vencsys CLK_VENC_VENC>, 2531 <&vencsys CLK_VENC_GALS>; 2532 clock-names = "apb", "smi"; 2533 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2534 }; 2535 2536 venc: video-codec@1a020000 { 2537 compatible = "mediatek,mt8195-vcodec-enc"; 2538 reg = <0 0x1a020000 0 0x10000>; 2539 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 2540 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 2541 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 2542 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 2543 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 2544 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 2545 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 2546 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 2547 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 2548 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 2549 mediatek,scp = <&scp>; 2550 clocks = <&vencsys CLK_VENC_VENC>; 2551 clock-names = "venc_sel"; 2552 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2553 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2554 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2555 #address-cells = <2>; 2556 #size-cells = <2>; 2557 }; 2558 2559 jpgdec-master { 2560 compatible = "mediatek,mt8195-jpgdec"; 2561 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2562 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2563 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2564 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2565 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2566 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2567 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2568 #address-cells = <2>; 2569 #size-cells = <2>; 2570 ranges; 2571 2572 jpgdec@1a040000 { 2573 compatible = "mediatek,mt8195-jpgdec-hw"; 2574 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ 2575 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2576 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2577 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2578 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2579 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2580 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2581 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; 2582 clocks = <&vencsys CLK_VENC_JPGDEC>; 2583 clock-names = "jpgdec"; 2584 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2585 }; 2586 2587 jpgdec@1a050000 { 2588 compatible = "mediatek,mt8195-jpgdec-hw"; 2589 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ 2590 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2591 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2592 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2593 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2594 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2595 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2596 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; 2597 clocks = <&vencsys CLK_VENC_JPGDEC_C1>; 2598 clock-names = "jpgdec"; 2599 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2600 }; 2601 2602 jpgdec@1b040000 { 2603 compatible = "mediatek,mt8195-jpgdec-hw"; 2604 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ 2605 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, 2606 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, 2607 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, 2608 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, 2609 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, 2610 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; 2611 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; 2612 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; 2613 clock-names = "jpgdec"; 2614 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2615 }; 2616 }; 2617 2618 vencsys_core1: clock-controller@1b000000 { 2619 compatible = "mediatek,mt8195-vencsys_core1"; 2620 reg = <0 0x1b000000 0 0x1000>; 2621 #clock-cells = <1>; 2622 }; 2623 2624 vdosys0: syscon@1c01a000 { 2625 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon"; 2626 reg = <0 0x1c01a000 0 0x1000>; 2627 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 2628 #clock-cells = <1>; 2629 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; 2630 }; 2631 2632 2633 jpgenc-master { 2634 compatible = "mediatek,mt8195-jpgenc"; 2635 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2636 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 2637 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 2638 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 2639 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 2640 #address-cells = <2>; 2641 #size-cells = <2>; 2642 ranges; 2643 2644 jpgenc@1a030000 { 2645 compatible = "mediatek,mt8195-jpgenc-hw"; 2646 reg = <0 0x1a030000 0 0x10000>; 2647 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, 2648 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, 2649 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, 2650 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; 2651 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; 2652 clocks = <&vencsys CLK_VENC_JPGENC>; 2653 clock-names = "jpgenc"; 2654 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2655 }; 2656 2657 jpgenc@1b030000 { 2658 compatible = "mediatek,mt8195-jpgenc-hw"; 2659 reg = <0 0x1b030000 0 0x10000>; 2660 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 2661 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 2662 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 2663 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 2664 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; 2665 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; 2666 clock-names = "jpgenc"; 2667 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2668 }; 2669 }; 2670 2671 larb20: larb@1b010000 { 2672 compatible = "mediatek,mt8195-smi-larb"; 2673 reg = <0 0x1b010000 0 0x1000>; 2674 mediatek,larb-id = <20>; 2675 mediatek,smi = <&smi_common_vpp>; 2676 clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>, 2677 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 2678 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2679 clock-names = "apb", "smi", "gals"; 2680 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2681 }; 2682 2683 ovl0: ovl@1c000000 { 2684 compatible = "mediatek,mt8195-disp-ovl"; 2685 reg = <0 0x1c000000 0 0x1000>; 2686 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 2687 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2688 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 2689 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 2690 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 2691 }; 2692 2693 rdma0: rdma@1c002000 { 2694 compatible = "mediatek,mt8195-disp-rdma"; 2695 reg = <0 0x1c002000 0 0x1000>; 2696 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 2697 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2698 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 2699 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 2700 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 2701 }; 2702 2703 color0: color@1c003000 { 2704 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 2705 reg = <0 0x1c003000 0 0x1000>; 2706 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 2707 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2708 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 2709 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 2710 }; 2711 2712 ccorr0: ccorr@1c004000 { 2713 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 2714 reg = <0 0x1c004000 0 0x1000>; 2715 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 2716 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2717 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 2718 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 2719 }; 2720 2721 aal0: aal@1c005000 { 2722 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 2723 reg = <0 0x1c005000 0 0x1000>; 2724 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 2725 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2726 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 2727 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 2728 }; 2729 2730 gamma0: gamma@1c006000 { 2731 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 2732 reg = <0 0x1c006000 0 0x1000>; 2733 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 2734 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2735 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 2736 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 2737 }; 2738 2739 dither0: dither@1c007000 { 2740 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 2741 reg = <0 0x1c007000 0 0x1000>; 2742 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 2743 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2744 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 2745 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 2746 }; 2747 2748 dsc0: dsc@1c009000 { 2749 compatible = "mediatek,mt8195-disp-dsc"; 2750 reg = <0 0x1c009000 0 0x1000>; 2751 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 2752 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2753 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 2754 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 2755 }; 2756 2757 merge0: merge@1c014000 { 2758 compatible = "mediatek,mt8195-disp-merge"; 2759 reg = <0 0x1c014000 0 0x1000>; 2760 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 2761 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2762 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 2763 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 2764 }; 2765 2766 dp_intf0: dp-intf@1c015000 { 2767 compatible = "mediatek,mt8195-dp-intf"; 2768 reg = <0 0x1c015000 0 0x1000>; 2769 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 2770 clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 2771 <&vdosys0 CLK_VDO0_DP_INTF0>, 2772 <&apmixedsys CLK_APMIXED_TVDPLL1>; 2773 clock-names = "pixel", "engine", "pll"; 2774 status = "disabled"; 2775 }; 2776 2777 mutex: mutex@1c016000 { 2778 compatible = "mediatek,mt8195-disp-mutex"; 2779 reg = <0 0x1c016000 0 0x1000>; 2780 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 2781 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2782 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 2783 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; 2784 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 2785 }; 2786 2787 larb0: larb@1c018000 { 2788 compatible = "mediatek,mt8195-smi-larb"; 2789 reg = <0 0x1c018000 0 0x1000>; 2790 mediatek,larb-id = <0>; 2791 mediatek,smi = <&smi_common_vdo>; 2792 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2793 <&vdosys0 CLK_VDO0_SMI_LARB>, 2794 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 2795 clock-names = "apb", "smi", "gals"; 2796 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2797 }; 2798 2799 larb1: larb@1c019000 { 2800 compatible = "mediatek,mt8195-smi-larb"; 2801 reg = <0 0x1c019000 0 0x1000>; 2802 mediatek,larb-id = <1>; 2803 mediatek,smi = <&smi_common_vpp>; 2804 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2805 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 2806 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 2807 clock-names = "apb", "smi", "gals"; 2808 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2809 }; 2810 2811 vdosys1: syscon@1c100000 { 2812 compatible = "mediatek,mt8195-vdosys1", "syscon"; 2813 reg = <0 0x1c100000 0 0x1000>; 2814 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; 2815 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>; 2816 #clock-cells = <1>; 2817 #reset-cells = <1>; 2818 }; 2819 2820 smi_common_vdo: smi@1c01b000 { 2821 compatible = "mediatek,mt8195-smi-common-vdo"; 2822 reg = <0 0x1c01b000 0 0x1000>; 2823 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 2824 <&vdosys0 CLK_VDO0_SMI_EMI>, 2825 <&vdosys0 CLK_VDO0_SMI_RSI>, 2826 <&vdosys0 CLK_VDO0_SMI_GALS>; 2827 clock-names = "apb", "smi", "gals0", "gals1"; 2828 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2829 2830 }; 2831 2832 iommu_vdo: iommu@1c01f000 { 2833 compatible = "mediatek,mt8195-iommu-vdo"; 2834 reg = <0 0x1c01f000 0 0x1000>; 2835 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 2836 &larb10 &larb11 &larb13 &larb17 2837 &larb19 &larb21 &larb24 &larb25 2838 &larb28>; 2839 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 2840 #iommu-cells = <1>; 2841 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 2842 clock-names = "bclk"; 2843 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2844 }; 2845 2846 mutex1: mutex@1c101000 { 2847 compatible = "mediatek,mt8195-disp-mutex"; 2848 reg = <0 0x1c101000 0 0x1000>; 2849 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; 2850 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2851 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; 2852 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; 2853 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; 2854 }; 2855 2856 larb2: larb@1c102000 { 2857 compatible = "mediatek,mt8195-smi-larb"; 2858 reg = <0 0x1c102000 0 0x1000>; 2859 mediatek,larb-id = <2>; 2860 mediatek,smi = <&smi_common_vdo>; 2861 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 2862 <&vdosys1 CLK_VDO1_SMI_LARB2>, 2863 <&vdosys1 CLK_VDO1_GALS>; 2864 clock-names = "apb", "smi", "gals"; 2865 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2866 }; 2867 2868 larb3: larb@1c103000 { 2869 compatible = "mediatek,mt8195-smi-larb"; 2870 reg = <0 0x1c103000 0 0x1000>; 2871 mediatek,larb-id = <3>; 2872 mediatek,smi = <&smi_common_vpp>; 2873 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 2874 <&vdosys1 CLK_VDO1_GALS>, 2875 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2876 clock-names = "apb", "smi", "gals"; 2877 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2878 }; 2879 2880 vdo1_rdma0: dma-controller@1c104000 { 2881 compatible = "mediatek,mt8195-vdo1-rdma"; 2882 reg = <0 0x1c104000 0 0x1000>; 2883 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; 2884 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; 2885 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2886 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; 2887 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; 2888 #dma-cells = <1>; 2889 }; 2890 2891 vdo1_rdma1: dma-controller@1c105000 { 2892 compatible = "mediatek,mt8195-vdo1-rdma"; 2893 reg = <0 0x1c105000 0 0x1000>; 2894 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; 2895 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; 2896 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2897 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>; 2898 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; 2899 #dma-cells = <1>; 2900 }; 2901 2902 vdo1_rdma2: dma-controller@1c106000 { 2903 compatible = "mediatek,mt8195-vdo1-rdma"; 2904 reg = <0 0x1c106000 0 0x1000>; 2905 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; 2906 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; 2907 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2908 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>; 2909 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; 2910 #dma-cells = <1>; 2911 }; 2912 2913 vdo1_rdma3: dma-controller@1c107000 { 2914 compatible = "mediatek,mt8195-vdo1-rdma"; 2915 reg = <0 0x1c107000 0 0x1000>; 2916 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; 2917 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; 2918 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2919 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>; 2920 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; 2921 #dma-cells = <1>; 2922 }; 2923 2924 vdo1_rdma4: dma-controller@1c108000 { 2925 compatible = "mediatek,mt8195-vdo1-rdma"; 2926 reg = <0 0x1c108000 0 0x1000>; 2927 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; 2928 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; 2929 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2930 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>; 2931 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; 2932 #dma-cells = <1>; 2933 }; 2934 2935 vdo1_rdma5: dma-controller@1c109000 { 2936 compatible = "mediatek,mt8195-vdo1-rdma"; 2937 reg = <0 0x1c109000 0 0x1000>; 2938 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; 2939 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; 2940 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2941 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>; 2942 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; 2943 #dma-cells = <1>; 2944 }; 2945 2946 vdo1_rdma6: dma-controller@1c10a000 { 2947 compatible = "mediatek,mt8195-vdo1-rdma"; 2948 reg = <0 0x1c10a000 0 0x1000>; 2949 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; 2950 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; 2951 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2952 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; 2953 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; 2954 #dma-cells = <1>; 2955 }; 2956 2957 vdo1_rdma7: dma-controller@1c10b000 { 2958 compatible = "mediatek,mt8195-vdo1-rdma"; 2959 reg = <0 0x1c10b000 0 0x1000>; 2960 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; 2961 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; 2962 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2963 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; 2964 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; 2965 #dma-cells = <1>; 2966 }; 2967 2968 merge1: vpp-merge@1c10c000 { 2969 compatible = "mediatek,mt8195-disp-merge"; 2970 reg = <0 0x1c10c000 0 0x1000>; 2971 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 2972 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, 2973 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; 2974 clock-names = "merge","merge_async"; 2975 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2976 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; 2977 mediatek,merge-mute; 2978 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>; 2979 }; 2980 2981 merge2: vpp-merge@1c10d000 { 2982 compatible = "mediatek,mt8195-disp-merge"; 2983 reg = <0 0x1c10d000 0 0x1000>; 2984 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; 2985 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, 2986 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; 2987 clock-names = "merge","merge_async"; 2988 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2989 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; 2990 mediatek,merge-mute; 2991 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>; 2992 }; 2993 2994 merge3: vpp-merge@1c10e000 { 2995 compatible = "mediatek,mt8195-disp-merge"; 2996 reg = <0 0x1c10e000 0 0x1000>; 2997 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; 2998 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, 2999 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; 3000 clock-names = "merge","merge_async"; 3001 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3002 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; 3003 mediatek,merge-mute; 3004 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>; 3005 }; 3006 3007 merge4: vpp-merge@1c10f000 { 3008 compatible = "mediatek,mt8195-disp-merge"; 3009 reg = <0 0x1c10f000 0 0x1000>; 3010 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; 3011 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, 3012 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; 3013 clock-names = "merge","merge_async"; 3014 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3015 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; 3016 mediatek,merge-mute; 3017 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>; 3018 }; 3019 3020 merge5: vpp-merge@1c110000 { 3021 compatible = "mediatek,mt8195-disp-merge"; 3022 reg = <0 0x1c110000 0 0x1000>; 3023 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; 3024 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, 3025 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; 3026 clock-names = "merge","merge_async"; 3027 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3028 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; 3029 mediatek,merge-fifo-en; 3030 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; 3031 }; 3032 3033 dp_intf1: dp-intf@1c113000 { 3034 compatible = "mediatek,mt8195-dp-intf"; 3035 reg = <0 0x1c113000 0 0x1000>; 3036 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 3037 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3038 clocks = <&vdosys1 CLK_VDO1_DPINTF>, 3039 <&vdosys1 CLK_VDO1_DP_INTF0_MM>, 3040 <&apmixedsys CLK_APMIXED_TVDPLL2>; 3041 clock-names = "pixel", "engine", "pll"; 3042 status = "disabled"; 3043 }; 3044 3045 ethdr0: hdr-engine@1c114000 { 3046 compatible = "mediatek,mt8195-disp-ethdr"; 3047 reg = <0 0x1c114000 0 0x1000>, 3048 <0 0x1c115000 0 0x1000>, 3049 <0 0x1c117000 0 0x1000>, 3050 <0 0x1c119000 0 0x1000>, 3051 <0 0x1c11a000 0 0x1000>, 3052 <0 0x1c11b000 0 0x1000>, 3053 <0 0x1c11c000 0 0x1000>; 3054 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3055 "vdo_be", "adl_ds"; 3056 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, 3057 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, 3058 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, 3059 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, 3060 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, 3061 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, 3062 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; 3063 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, 3064 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, 3065 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, 3066 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, 3067 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, 3068 <&vdosys1 CLK_VDO1_HDR_VDO_BE>, 3069 <&vdosys1 CLK_VDO1_26M_SLOW>, 3070 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, 3071 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, 3072 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, 3073 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, 3074 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, 3075 <&topckgen CLK_TOP_ETHDR>; 3076 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3077 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", 3078 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", 3079 "ethdr_top"; 3080 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3081 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, 3082 <&iommu_vpp M4U_PORT_L3_HDR_ADL>; 3083 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */ 3084 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, 3085 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, 3086 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, 3087 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, 3088 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; 3089 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", 3090 "gfx_fe1_async", "vdo_be_async"; 3091 }; 3092 3093 edp_tx: edp-tx@1c500000 { 3094 compatible = "mediatek,mt8195-edp-tx"; 3095 reg = <0 0x1c500000 0 0x8000>; 3096 nvmem-cells = <&dp_calibration>; 3097 nvmem-cell-names = "dp_calibration_data"; 3098 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; 3099 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 3100 max-linkrate-mhz = <8100>; 3101 status = "disabled"; 3102 }; 3103 3104 dp_tx: dp-tx@1c600000 { 3105 compatible = "mediatek,mt8195-dp-tx"; 3106 reg = <0 0x1c600000 0 0x8000>; 3107 nvmem-cells = <&dp_calibration>; 3108 nvmem-cell-names = "dp_calibration_data"; 3109 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; 3110 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 3111 max-linkrate-mhz = <8100>; 3112 status = "disabled"; 3113 }; 3114 }; 3115 3116 thermal_zones: thermal-zones { 3117 cpu0-thermal { 3118 polling-delay = <1000>; 3119 polling-delay-passive = <250>; 3120 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; 3121 3122 trips { 3123 cpu0_alert: trip-alert { 3124 temperature = <85000>; 3125 hysteresis = <2000>; 3126 type = "passive"; 3127 }; 3128 3129 cpu0_crit: trip-crit { 3130 temperature = <100000>; 3131 hysteresis = <2000>; 3132 type = "critical"; 3133 }; 3134 }; 3135 3136 cooling-maps { 3137 map0 { 3138 trip = <&cpu0_alert>; 3139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3140 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3141 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3142 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3143 }; 3144 }; 3145 }; 3146 3147 cpu1-thermal { 3148 polling-delay = <1000>; 3149 polling-delay-passive = <250>; 3150 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>; 3151 3152 trips { 3153 cpu1_alert: trip-alert { 3154 temperature = <85000>; 3155 hysteresis = <2000>; 3156 type = "passive"; 3157 }; 3158 3159 cpu1_crit: trip-crit { 3160 temperature = <100000>; 3161 hysteresis = <2000>; 3162 type = "critical"; 3163 }; 3164 }; 3165 3166 cooling-maps { 3167 map0 { 3168 trip = <&cpu1_alert>; 3169 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3170 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3171 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3172 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3173 }; 3174 }; 3175 }; 3176 3177 cpu2-thermal { 3178 polling-delay = <1000>; 3179 polling-delay-passive = <250>; 3180 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>; 3181 3182 trips { 3183 cpu2_alert: trip-alert { 3184 temperature = <85000>; 3185 hysteresis = <2000>; 3186 type = "passive"; 3187 }; 3188 3189 cpu2_crit: trip-crit { 3190 temperature = <100000>; 3191 hysteresis = <2000>; 3192 type = "critical"; 3193 }; 3194 }; 3195 3196 cooling-maps { 3197 map0 { 3198 trip = <&cpu2_alert>; 3199 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3200 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3201 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3202 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3203 }; 3204 }; 3205 }; 3206 3207 cpu3-thermal { 3208 polling-delay = <1000>; 3209 polling-delay-passive = <250>; 3210 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>; 3211 3212 trips { 3213 cpu3_alert: trip-alert { 3214 temperature = <85000>; 3215 hysteresis = <2000>; 3216 type = "passive"; 3217 }; 3218 3219 cpu3_crit: trip-crit { 3220 temperature = <100000>; 3221 hysteresis = <2000>; 3222 type = "critical"; 3223 }; 3224 }; 3225 3226 cooling-maps { 3227 map0 { 3228 trip = <&cpu3_alert>; 3229 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3230 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3231 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3232 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3233 }; 3234 }; 3235 }; 3236 3237 cpu4-thermal { 3238 polling-delay = <1000>; 3239 polling-delay-passive = <250>; 3240 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>; 3241 3242 trips { 3243 cpu4_alert: trip-alert { 3244 temperature = <85000>; 3245 hysteresis = <2000>; 3246 type = "passive"; 3247 }; 3248 3249 cpu4_crit: trip-crit { 3250 temperature = <100000>; 3251 hysteresis = <2000>; 3252 type = "critical"; 3253 }; 3254 }; 3255 3256 cooling-maps { 3257 map0 { 3258 trip = <&cpu4_alert>; 3259 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3260 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3261 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3262 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3263 }; 3264 }; 3265 }; 3266 3267 cpu5-thermal { 3268 polling-delay = <1000>; 3269 polling-delay-passive = <250>; 3270 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>; 3271 3272 trips { 3273 cpu5_alert: trip-alert { 3274 temperature = <85000>; 3275 hysteresis = <2000>; 3276 type = "passive"; 3277 }; 3278 3279 cpu5_crit: trip-crit { 3280 temperature = <100000>; 3281 hysteresis = <2000>; 3282 type = "critical"; 3283 }; 3284 }; 3285 3286 cooling-maps { 3287 map0 { 3288 trip = <&cpu5_alert>; 3289 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3290 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3291 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3292 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3293 }; 3294 }; 3295 }; 3296 3297 cpu6-thermal { 3298 polling-delay = <1000>; 3299 polling-delay-passive = <250>; 3300 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>; 3301 3302 trips { 3303 cpu6_alert: trip-alert { 3304 temperature = <85000>; 3305 hysteresis = <2000>; 3306 type = "passive"; 3307 }; 3308 3309 cpu6_crit: trip-crit { 3310 temperature = <100000>; 3311 hysteresis = <2000>; 3312 type = "critical"; 3313 }; 3314 }; 3315 3316 cooling-maps { 3317 map0 { 3318 trip = <&cpu6_alert>; 3319 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3320 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3321 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3322 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3323 }; 3324 }; 3325 }; 3326 3327 cpu7-thermal { 3328 polling-delay = <1000>; 3329 polling-delay-passive = <250>; 3330 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>; 3331 3332 trips { 3333 cpu7_alert: trip-alert { 3334 temperature = <85000>; 3335 hysteresis = <2000>; 3336 type = "passive"; 3337 }; 3338 3339 cpu7_crit: trip-crit { 3340 temperature = <100000>; 3341 hysteresis = <2000>; 3342 type = "critical"; 3343 }; 3344 }; 3345 3346 cooling-maps { 3347 map0 { 3348 trip = <&cpu7_alert>; 3349 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3350 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3351 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3352 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3353 }; 3354 }; 3355 }; 3356 3357 vpu0-thermal { 3358 polling-delay = <1000>; 3359 polling-delay-passive = <250>; 3360 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>; 3361 3362 trips { 3363 vpu0_alert: trip-alert { 3364 temperature = <85000>; 3365 hysteresis = <2000>; 3366 type = "passive"; 3367 }; 3368 3369 vpu0_crit: trip-crit { 3370 temperature = <100000>; 3371 hysteresis = <2000>; 3372 type = "critical"; 3373 }; 3374 }; 3375 }; 3376 3377 vpu1-thermal { 3378 polling-delay = <1000>; 3379 polling-delay-passive = <250>; 3380 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>; 3381 3382 trips { 3383 vpu1_alert: trip-alert { 3384 temperature = <85000>; 3385 hysteresis = <2000>; 3386 type = "passive"; 3387 }; 3388 3389 vpu1_crit: trip-crit { 3390 temperature = <100000>; 3391 hysteresis = <2000>; 3392 type = "critical"; 3393 }; 3394 }; 3395 }; 3396 3397 gpu-thermal { 3398 polling-delay = <1000>; 3399 polling-delay-passive = <250>; 3400 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>; 3401 3402 trips { 3403 gpu0_alert: trip-alert { 3404 temperature = <85000>; 3405 hysteresis = <2000>; 3406 type = "passive"; 3407 }; 3408 3409 gpu0_crit: trip-crit { 3410 temperature = <100000>; 3411 hysteresis = <2000>; 3412 type = "critical"; 3413 }; 3414 }; 3415 }; 3416 3417 gpu1-thermal { 3418 polling-delay = <1000>; 3419 polling-delay-passive = <250>; 3420 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>; 3421 3422 trips { 3423 gpu1_alert: trip-alert { 3424 temperature = <85000>; 3425 hysteresis = <2000>; 3426 type = "passive"; 3427 }; 3428 3429 gpu1_crit: trip-crit { 3430 temperature = <100000>; 3431 hysteresis = <2000>; 3432 type = "critical"; 3433 }; 3434 }; 3435 }; 3436 3437 vdec-thermal { 3438 polling-delay = <1000>; 3439 polling-delay-passive = <250>; 3440 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>; 3441 3442 trips { 3443 vdec_alert: trip-alert { 3444 temperature = <85000>; 3445 hysteresis = <2000>; 3446 type = "passive"; 3447 }; 3448 3449 vdec_crit: trip-crit { 3450 temperature = <100000>; 3451 hysteresis = <2000>; 3452 type = "critical"; 3453 }; 3454 }; 3455 }; 3456 3457 img-thermal { 3458 polling-delay = <1000>; 3459 polling-delay-passive = <250>; 3460 thermal-sensors = <&lvts_ap MT8195_AP_IMG>; 3461 3462 trips { 3463 img_alert: trip-alert { 3464 temperature = <85000>; 3465 hysteresis = <2000>; 3466 type = "passive"; 3467 }; 3468 3469 img_crit: trip-crit { 3470 temperature = <100000>; 3471 hysteresis = <2000>; 3472 type = "critical"; 3473 }; 3474 }; 3475 }; 3476 3477 infra-thermal { 3478 polling-delay = <1000>; 3479 polling-delay-passive = <250>; 3480 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>; 3481 3482 trips { 3483 infra_alert: trip-alert { 3484 temperature = <85000>; 3485 hysteresis = <2000>; 3486 type = "passive"; 3487 }; 3488 3489 infra_crit: trip-crit { 3490 temperature = <100000>; 3491 hysteresis = <2000>; 3492 type = "critical"; 3493 }; 3494 }; 3495 }; 3496 3497 cam0-thermal { 3498 polling-delay = <1000>; 3499 polling-delay-passive = <250>; 3500 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>; 3501 3502 trips { 3503 cam0_alert: trip-alert { 3504 temperature = <85000>; 3505 hysteresis = <2000>; 3506 type = "passive"; 3507 }; 3508 3509 cam0_crit: trip-crit { 3510 temperature = <100000>; 3511 hysteresis = <2000>; 3512 type = "critical"; 3513 }; 3514 }; 3515 }; 3516 3517 cam1-thermal { 3518 polling-delay = <1000>; 3519 polling-delay-passive = <250>; 3520 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>; 3521 3522 trips { 3523 cam1_alert: trip-alert { 3524 temperature = <85000>; 3525 hysteresis = <2000>; 3526 type = "passive"; 3527 }; 3528 3529 cam1_crit: trip-crit { 3530 temperature = <100000>; 3531 hysteresis = <2000>; 3532 type = "critical"; 3533 }; 3534 }; 3535 }; 3536 }; 3537}; 3538