| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | fsl,cpm1-tsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
[all …]
|
| /kernel/linux/linux-6.6/drivers/soc/fsl/qe/ |
| D | tsa.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <dt-bindings/soc/cpm1-fsl,tsa.h>
33 /* SI mode register (32 bits) */
54 /* SI global mode register (8 bits) */
64 /* SI status register (8 bits) */
67 /* SI command register (8 bits) */
70 /* SI clock route register (32 bits) */
97 /* Serial interface RAM pointer register (32 bits) */
135 return container_of(tsa_serial, struct tsa, serials[tsa_serial->id]); in tsa_serial_get_tsa()
170 switch (tsa_serial->id) { in tsa_serial_connect()
[all …]
|
| /kernel/linux/linux-6.6/drivers/spi/ |
| D | spi-sh-msiof.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2014-2017 Glider bvba
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
86 #define SIMDR1_SYNCMD_MASK GENMASK(29, 28) /* SYNC Mode */
89 #define SIMDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
91 #define SIMDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
92 #define SIMDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
93 #define SIMDR1_FLD_MASK GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
98 #define SITMDR1_SYNCCH_MASK GENMASK(27, 26) /* Sync Signal Channel Select */
[all …]
|
| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-sh-msiof.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2014-2017 Glider bvba
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
87 #define SIMDR1_SYNCMD_MASK GENMASK(29, 28) /* SYNC Mode */
90 #define SIMDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
92 #define SIMDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
93 #define SIMDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
94 #define SIMDR1_FLD_MASK GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
99 #define SITMDR1_SYNCCH_MASK GENMASK(27, 26) /* Sync Signal Channel Select */
[all …]
|
| /kernel/linux/linux-5.10/sound/soc/fsl/ |
| D | fsl_sai.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
8 #include <linux/delay.h>
21 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
24 #include "imx-pcm.h"
41 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
43 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
52 int adir = (dir == TX) ? RX : TX; in fsl_sai_dir_is_synced()
54 /* current dir in async mode while opposite dir in sync mode */ in fsl_sai_dir_is_synced()
55 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
[all …]
|
| D | fsl_ssi.c | 1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
18 // from 48000Hz not every frame has valid receive data, so the ratio
23 // provides us status bits when the read register is updated with *another*
25 // contains the same value) these status bits are not set. We work
26 // around this by not polling these bits but only wait a fixed delay.
35 #include <linux/delay.h>
52 #include "imx-pcm.h"
[all …]
|
| /kernel/linux/linux-5.10/drivers/tty/serial/ |
| D | pmac_zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
74 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
76 return uap->mate; in pmz_get_port_A()
81 * delay on PCI PowerMac hardware, it's dealt in HW by the MacIO chip,
88 writeb(reg, port->control_reg); in read_zsreg()
89 return readb(port->control_reg); in read_zsreg()
95 writeb(reg, port->control_reg); in write_zsreg()
96 writeb(value, port->control_reg); in write_zsreg()
101 return readb(port->data_reg); in read_zsdata()
[all …]
|
| /kernel/linux/linux-6.6/drivers/tty/serial/ |
| D | pmac_zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
71 * delay on PCI PowerMac hardware, it's dealt in HW by the MacIO chip,
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
[all …]
|
| /kernel/linux/linux-6.6/include/linux/ |
| D | pxa2xx_ssp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
17 #include <linux/bits.h>
31 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
42 #define SSTSA (0x30) /* SSP Tx Timeslot Active */
48 /* Common PXA2xx bits first */
50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
51 #define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */
64 #define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */
65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
[all …]
|
| /kernel/linux/linux-6.6/sound/soc/fsl/ |
| D | fsl_ssi.c | 1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
18 // from 48000Hz not every frame has valid receive data, so the ratio
23 // provides us status bits when the read register is updated with *another*
25 // contains the same value) these status bits are not set. We work
26 // around this by not polling these bits but only wait a fixed delay.
35 #include <linux/delay.h>
43 #include <linux/dma/imx-dma.h>
[all …]
|
| D | fsl_sai.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
8 #include <linux/delay.h>
23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
27 #include "imx-pcm.h"
45 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
47 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
56 int adir = (dir == TX) ? RX : TX; in fsl_sai_dir_is_synced()
58 /* current dir in async mode while opposite dir in sync mode */ in fsl_sai_dir_is_synced()
59 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
[all …]
|
| /kernel/linux/linux-5.10/include/linux/ |
| D | pxa2xx_ssp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
17 #include <linux/bits.h>
31 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
43 #define SSTSA (0x30) /* SSP Tx Timeslot Active */
49 /* Common PXA2xx bits first */
51 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
52 #define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */
65 #define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */
66 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/xilinx/ |
| D | xilinx_dma.txt | 11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.00.a"
22 "xlnx,axi-cdma-1.00.a"
23 "xlnx,axi-mcdma-1.00.a"
24 - #dma-cells: Should be <1>, see "dmas" property below
25 - reg: Should contain VDMA registers location and length.
26 - xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
[all …]
|
| /kernel/linux/linux-5.10/sound/soc/bcm/ |
| D | bcm2835-i2s.c | 1 // SPDX-License-Identifier: GPL-2.0-only
23 * Copyright 2007-2010 Freescale Semiconductor, Inc.
28 #include <linux/delay.h>
108 /* Frame length register is 10 bit, maximum length 1024 */
130 unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; in bcm2835_i2s_start_clock()
132 if (dev->clk_prepared) in bcm2835_i2s_start_clock()
138 clk_prepare_enable(dev->clk); in bcm2835_i2s_start_clock()
139 dev->clk_prepared = true; in bcm2835_i2s_start_clock()
148 if (dev->clk_prepared) in bcm2835_i2s_stop_clock()
149 clk_disable_unprepare(dev->clk); in bcm2835_i2s_stop_clock()
[all …]
|
| /kernel/linux/linux-6.6/sound/soc/bcm/ |
| D | bcm2835-i2s.c | 1 // SPDX-License-Identifier: GPL-2.0-only
23 * Copyright 2007-2010 Freescale Semiconductor, Inc.
28 #include <linux/delay.h>
108 /* Frame length register is 10 bit, maximum length 1024 */
130 unsigned int provider = dev->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK; in bcm2835_i2s_start_clock()
132 if (dev->clk_prepared) in bcm2835_i2s_start_clock()
138 clk_prepare_enable(dev->clk); in bcm2835_i2s_start_clock()
139 dev->clk_prepared = true; in bcm2835_i2s_start_clock()
148 if (dev->clk_prepared) in bcm2835_i2s_stop_clock()
149 clk_disable_unprepare(dev->clk); in bcm2835_i2s_stop_clock()
[all …]
|
| /kernel/linux/linux-6.6/Documentation/networking/dsa/ |
| D | sja1105.rst | 8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
[all …]
|
| /kernel/linux/linux-6.6/sound/soc/ti/ |
| D | davinci-mcasp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Multi-channel Audio Serial Port Driver
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
19 #include <linux/delay.h>
39 #include "edma-pcm.h"
40 #include "sdma-pcm.h"
41 #include "udma-pcm.h"
42 #include "davinci-mcasp.h"
136 void __iomem *reg = mcasp->base + offset; in mcasp_set_bits()
143 void __iomem *reg = mcasp->base + offset; in mcasp_clr_bits()
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/wireless/ath/ath5k/ |
| D | reg.h | 2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
42 * AR5210-Specific TXDP registers
46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/wireless/ath/ath5k/ |
| D | reg.h | 2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
42 * AR5210-Specific TXDP registers
46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/intel/igc/ |
| D | igc_defines.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
88 /* Loop limit on how long we wait for auto-negotiation to complete */
161 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
162 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
170 /* 1000BASE-T Control Register */
174 /* 1000BASE-T Status Register */
180 #define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */
189 /* NVM Addressing bits based on type 0=small, 1=large */
204 #define IGC_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
238 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/intel/igc/ |
| D | igc_defines.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
47 /* Loop limit on how long we wait for auto-negotiation to complete */
116 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
117 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
125 /* 1000BASE-T Control Register */
130 /* 1000BASE-T Status Register */
137 #define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */
146 /* NVM Addressing bits based on type 0=small, 1=large */
161 #define IGC_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
195 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
[all …]
|
| /kernel/linux/linux-5.10/sound/soc/ti/ |
| D | davinci-mcasp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Multi-channel Audio Serial Port Driver
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
19 #include <linux/delay.h>
39 #include "edma-pcm.h"
40 #include "sdma-pcm.h"
41 #include "udma-pcm.h"
42 #include "davinci-mcasp.h"
131 void __iomem *reg = mcasp->base + offset; in mcasp_set_bits()
138 void __iomem *reg = mcasp->base + offset; in mcasp_clr_bits()
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/wan/ |
| D | farsync.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
7 * Copyright (C) 2001-2004 FarSite Communications Ltd.
25 #include <linux/delay.h>
37 MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
70 #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
94 * file. Unfortunately various name clashes and the non-portability of the
134 volatile u8 hadr; /* High order address. Low 4 bits only, high 4
135 * bits must be zero
137 volatile u8 bits; /* Status and config */ member
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/wan/ |
| D | farsync.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
6 * Copyright (C) 2001-2004 FarSite Communications Ltd.
24 #include <linux/delay.h>
35 MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
71 #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
94 * file. Unfortunately various name clashes and the non-portability of the
136 volatile u8 hadr; /* High order address. Low 4 bits only, high 4
137 * bits must be zero
139 volatile u8 bits; /* Status and config */ member
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/cadence/ |
| D | macb.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
33 #define MACB_TBQP 0x001c /* TX Q Base Address */
100 #define GEM_TXPTPUNI 0x00D8 /* PTP TX Unicast address */
101 #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
102 #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
103 #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
104 #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
112 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
113 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
[all …]
|