| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/can/ |
| D | sja1000.txt | 5 - compatible : should be one of "nxp,sja1000", "technologic,sja1000".
7 - reg : should specify the chip select, address offset and size required
10 - interrupts: property with a value describing the interrupt source
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
20 - nxp,external-clock-frequency : Frequency of the external oscillator
25 - nxp,tx-output-mode : operation mode of the TX output control logic:
26 <0x0> : bi-phase output mode
27 <0x1> : normal output mode (default)
28 <0x2> : test output mode
29 <0x3> : clock output mode
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | ti,dp83869.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
22 SGMII The DP83869HM supports Media Conversion in Managed mode. In this mode,
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| D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-controller.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 ti,min-output-impedance:
37 MAC Interface Impedance control to set the programmable output impedance
40 ti,max-output-impedance:
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | ti,dp83869.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
22 SGMII The DP83869HM supports Media Conversion in Managed mode. In this mode,
[all …]
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| D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
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| D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
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| D | motorcomm,yt8xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/can/ |
| D | nxp,sja1000.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
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| /kernel/linux/linux-6.6/drivers/net/hamradio/ |
| D | z8530.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
34 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
40 #define TxINT_ENAB 0x2 /* Tx Int Enable */
58 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
60 #define ENT_HM 0x10 /* Enter Hunt Mode */
79 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
80 #define EXTSYNC 0x30 /* External Sync Mode */
82 #define X1CLK 0x0 /* x1 clock mode */
83 #define X16CLK 0x40 /* x16 clock mode */
84 #define X32CLK 0x80 /* x32 clock mode */
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| /kernel/linux/linux-5.10/drivers/net/hamradio/ |
| D | z8530.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
34 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
40 #define TxINT_ENAB 0x2 /* Tx Int Enable */
58 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
60 #define ENT_HM 0x10 /* Enter Hunt Mode */
79 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
80 #define EXTSYNC 0x30 /* External Sync Mode */
82 #define X1CLK 0x0 /* x1 clock mode */
83 #define X16CLK 0x40 /* x16 clock mode */
84 #define X32CLK 0x80 /* x32 clock mode */
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| /kernel/linux/linux-5.10/tools/spi/ |
| D | spidev_test.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
39 static uint32_t mode; variable
71 while (length-- > 0) { in hex_dump()
91 * Unescape - process hexadecimal escape character
92 * converts shell input "\x23" -> 0x23
118 static void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len) in transfer() argument
123 .tx_buf = (unsigned long)tx, in transfer()
131 if (mode & SPI_TX_OCTAL) in transfer()
133 else if (mode & SPI_TX_QUAD) in transfer()
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| /kernel/linux/linux-5.10/drivers/tty/serial/ |
| D | zs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
29 int tx_stopped; /* Output is suspended. */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
87 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
92 #define TxINT_ENAB 0x2 /* Tx Int Enable */
110 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
112 #define ENT_HM 0x10 /* Enter Hunt Mode */
132 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
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| D | ip22zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
66 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
72 #define TxINT_ENAB 0x2 /* Tx Int Enable */
91 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
93 #define ENT_HM 0x10 /* Enter Hunt Mode */
113 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
114 #define EXTSYNC 0x30 /* External Sync Mode */
116 #define X1CLK 0x0 /* x1 clock mode */
117 #define X16CLK 0x40 /* x16 clock mode */
[all …]
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| D | sunzilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
58 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
64 #define TxINT_ENAB 0x2 /* Tx Int Enable */
83 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
85 #define ENT_HM 0x10 /* Enter Hunt Mode */
105 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
106 #define EXTSYNC 0x30 /* External Sync Mode */
108 #define X1CLK 0x0 /* x1 clock mode */
109 #define X16CLK 0x40 /* x16 clock mode */
[all …]
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| D | pmac_zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
74 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
76 return uap->mate; in pmz_get_port_A()
88 writeb(reg, port->control_reg); in read_zsreg()
89 return readb(port->control_reg); in read_zsreg()
95 writeb(reg, port->control_reg); in write_zsreg()
96 writeb(value, port->control_reg); in write_zsreg()
101 return readb(port->data_reg); in read_zsdata()
106 writeb(data, port->data_reg); in write_zsdata()
[all …]
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| /kernel/linux/linux-6.6/drivers/tty/serial/ |
| D | zs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
29 int tx_stopped; /* Output is suspended. */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
87 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
92 #define TxINT_ENAB 0x2 /* Tx Int Enable */
110 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
112 #define ENT_HM 0x10 /* Enter Hunt Mode */
132 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
[all …]
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| D | ip22zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
66 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
72 #define TxINT_ENAB 0x2 /* Tx Int Enable */
91 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
93 #define ENT_HM 0x10 /* Enter Hunt Mode */
113 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
114 #define EXTSYNC 0x30 /* External Sync Mode */
116 #define X1CLK 0x0 /* x1 clock mode */
117 #define X16CLK 0x40 /* x16 clock mode */
[all …]
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| D | sunzilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
58 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
64 #define TxINT_ENAB 0x2 /* Tx Int Enable */
83 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
85 #define ENT_HM 0x10 /* Enter Hunt Mode */
105 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
106 #define EXTSYNC 0x30 /* External Sync Mode */
108 #define X1CLK 0x0 /* x1 clock mode */
109 #define X16CLK 0x40 /* x16 clock mode */
[all …]
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| D | pmac_zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/microchip/ |
| D | sparx5_pcb134_board.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
17 compatible = "gpio-leds";
53 default-state = "off";
58 default-state = "off";
63 default-state = "off";
68 default-state = "off";
73 default-state = "off";
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| /kernel/linux/linux-6.6/tools/spi/ |
| D | spidev_test.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
39 static uint32_t mode; variable
71 while (length-- > 0) { in hex_dump()
91 * Unescape - process hexadecimal escape character
92 * converts shell input "\x23" -> 0x23
118 static void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len) in transfer() argument
123 .tx_buf = (unsigned long)tx, in transfer()
131 if (mode & SPI_TX_OCTAL) in transfer()
133 else if (mode & SPI_TX_QUAD) in transfer()
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wan/ |
| D | z85230.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
55 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
61 #define TxINT_ENAB 0x2 /* Tx Int Enable */
79 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
81 #define ENT_HM 0x10 /* Enter Hunt Mode */
100 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
101 #define EXTSYNC 0x30 /* External Sync Mode */
103 #define X1CLK 0x0 /* x1 clock mode */
104 #define X16CLK 0x40 /* x16 clock mode */
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| /kernel/linux/linux-6.6/Documentation/networking/devlink/ |
| D | mlx5.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
15 * - Name
16 - Mode
17 - Validation
18 * - ``enable_roce``
19 - driverinit
20 - Type: Boolean
26 * - ``io_eq_size``
27 - driverinit
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| /kernel/linux/linux-6.6/tools/testing/vsock/ |
| D | README | 2 -------------------
3 These tests exercise net/vmw_vsock/ host<->guest sockets for VMware, KVM, and
4 Hyper-V.
8 * vsock_test - core AF_VSOCK socket functionality
9 * vsock_diag_test - vsock_diag.ko module for listing open sockets
22 (host)# $TEST_BINARY --mode=server \
23 --control-port=1234 \
24 --peer-cid=3
25 (guest)# $TEST_BINARY --mode=client \
26 --control-host=$HOST_IP \
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| /kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/mellanox/ |
| D | mlx5.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
12 - `Enabling the driver and kconfig options`_
13 - `Devlink info`_
14 - `Devlink parameters`_
15 - `Devlink health reporters`_
16 - `mlx5 tracepoints`_
23 | Basic features, ethernet net device rx/tx offloads and XDP, are available with the most basic fla…
35 …ng this option will allow basic ethernet netdevice support with all of the standard rx/tx offloads.
37 | built-in into mlx5_core.ko.
42 | Enables Hardware-accelerated receive flow steering (arfs) support, and ntuple filtering.
[all …]
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