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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/serial/
Dxlnx,opb-uartlite.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/xlnx,opb-uartlite.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Axi Uartlite
10 - Peter Korsgaard <jacmet@sunsite.dk>
16 - xlnx,xps-uartlite-1.00.a
17 - xlnx,opb-uartlite-1.00.b
20 maxItems: 1
23 maxItems: 1
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/kernel/linux/linux-5.10/drivers/tty/serial/
Duartlite.c1 // SPDX-License-Identifier: GPL-2.0
3 * uartlite.c: Serial driver for Xilinx uartlite serial controller
31 /* ---------------------------------------------------------------------
105 struct uartlite_data *pdata = port->private_data; in uart_in32()
107 return pdata->reg_ops->in(port->membase + offset); in uart_in32()
112 struct uartlite_data *pdata = port->private_data; in uart_out32()
114 pdata->reg_ops->out(val, port->membase + offset); in uart_out32()
119 /* ---------------------------------------------------------------------
125 struct tty_port *tport = &port->state->port; in ulite_receive()
135 port->icount.rx++; in ulite_receive()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/
Dxilinx.txt10 Each IP-core has a set of parameters which the FPGA designer can use to
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
33 (generic-name): an open firmware-style name that describes the
36 (ip-core-name): the name of the ip block (given after the BEGIN
38 and all underscores '_' converted to dashes '-'.
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/
Dxilinx.txt10 Each IP-core has a set of parameters which the FPGA designer can use to
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
33 (generic-name): an open firmware-style name that describes the
36 (ip-core-name): the name of the ip block (given after the BEGIN
38 and all underscores '_' converted to dashes '-'.
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/kernel/linux/linux-6.6/drivers/tty/serial/
Duartlite.c1 // SPDX-License-Identifier: GPL-2.0
3 * uartlite.c: Serial driver for Xilinx uartlite serial controller
31 /* ---------------------------------------------------------------------
115 struct uartlite_data *pdata = port->private_data; in uart_in32()
117 return pdata->reg_ops->in(port->membase + offset); in uart_in32()
122 struct uartlite_data *pdata = port->private_data; in uart_out32()
124 pdata->reg_ops->out(val, port->membase + offset); in uart_out32()
131 /* ---------------------------------------------------------------------
137 struct tty_port *tport = &port->state->port; in ulite_receive()
147 port->icount.rx++; in ulite_receive()
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/kernel/linux/linux-5.10/arch/sh/boot/dts/
Dj2_mimas_v2.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 compatible = "jcore,j2-soc";
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&aic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 clock-frequency = <50000000>;
22 d-cache-size = <8192>;
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/kernel/linux/linux-6.6/arch/sh/boot/dts/
Dj2_mimas_v2.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 compatible = "jcore,j2-soc";
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&aic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 clock-frequency = <50000000>;
22 d-cache-size = <8192>;
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/kernel/linux/linux-5.10/arch/microblaze/boot/dts/
Dsystem.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2007-2008 Xilinx, Inc.
6 * (C) Copyright 2007-2009 Michal Simek
13 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
16 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 stdout-path = "/plb@0/serial@84000000";
35 #address-cells = <1>;
37 #size-cells = <0>;
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/kernel/linux/linux-6.6/arch/microblaze/boot/dts/
Dsystem.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2007-2008 Xilinx, Inc.
6 * (C) Copyright 2007-2009 Michal Simek
13 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
16 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 stdout-path = "/plb@0/serial@84000000";
35 #address-cells = <1>;
37 #size-cells = <0>;
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/kernel/linux/linux-5.10/
DMAINTAINERS9 -------------------------
11 1. Always *test* your changes, however small, on at least 4 or
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
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/kernel/linux/linux-6.6/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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