1/* 2 * Copyright (c) 2023 Institute of Parallel And Distributed Systems (IPADS), Shanghai Jiao Tong University (SJTU) 3 * Licensed under the Mulan PSL v2. 4 * You can use this software according to the terms and conditions of the Mulan PSL v2. 5 * You may obtain a copy of Mulan PSL v2 at: 6 * http://license.coscl.org.cn/MulanPSL2 7 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR 8 * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR 9 * PURPOSE. 10 * See the Mulan PSL v2 for more details. 11 */ 12#include <common/asm.h> 13#include <common/vars.h> 14 15.extern empty_page 16 17/* Args in x0 and x1 should be passed to main */ 18BEGIN_FUNC(start_kernel) 19 20 /* Set the kernel stack at high vaddr */ 21 ldr x2, =cpu_stacks 22 add x2, x2, CPU_STACK_SIZE 23 mov sp, x2 24 25 /* Save x0 and x1 */ 26 stp x0, x1, [sp, #-16]! 27 28 /* 29 * Make sure that no translation based 30 * on boot page table can happen. 31 */ 32 adrp x2, empty_page 33 msr ttbr0_el1, x2 34 isb 35 36 /* 37 * Call flush_tlb_all here to flush all the cached TLBs for 38 * the boot time TTBR0_EL1. 39 */ 40 bl flush_tlb_all 41 42 /* Restore x0 and x1 */ 43 ldp x0, x1, [sp], #16 44 45 bl main 46END_FUNC(start_kernel) 47 48BEGIN_FUNC(secondary_cpu_boot) 49 mov x19, x0 50 51 mov x1, #CPU_STACK_SIZE 52 mul x2, x0, x1 53 ldr x3, =cpu_stacks 54 add x2, x2, x3 55 add x2, x2, CPU_STACK_SIZE 56 mov sp, x2 57 58 /* 59 * Make sure that no translation based 60 * on boot page table can happen. 61 */ 62 adrp x3, empty_page 63 msr ttbr0_el1, x3 64 isb 65 /* 66 * Call flush_tlb_all here to flush all the cached TLBs for 67 * the boot time TTBR0_EL1. 68 */ 69 bl flush_tlb_all 70 71 mov x0, x19 72 bl secondary_start 73END_FUNC(secondary_cpu_boot) 74