1/* 2 * Copyright (c) 2023 Institute of Parallel And Distributed Systems (IPADS), Shanghai Jiao Tong University (SJTU) 3 * Licensed under the Mulan PSL v2. 4 * You can use this software according to the terms and conditions of the Mulan PSL v2. 5 * You may obtain a copy of Mulan PSL v2 at: 6 * http://license.coscl.org.cn/MulanPSL2 7 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR 8 * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR 9 * PURPOSE. 10 * See the Mulan PSL v2 for more details. 11 */ 12 13#include <common/asm.h> 14 15BEGIN_FUNC(flush_idcache) 16 mrs x0, clidr_el1 17 and w3, w0, #0x07000000 // get 2x level of coherence 18 lsr w3, w3, #23 19 cbz w3, .Lfinished_inv_cache 20 mov w10, #0 // w10 = 2x cache level 21 mov w8, #1 // w8 = constant 1 22.Lloop1_inv_cache: 23 add w2, w10, w10, lsr #1 // calculate 3x cache level 24 lsr w1, w0, w2 // extract 3 bit cache type for this level 25 and w1, w1, #0x7 26 cmp w1, #2 27 b.lt .Lskip_inv_cache // no data or unified cache at this level 28 msr csselr_el1, x10 // select this cache level 29 isb // synchronize change to csselr 30 mrs x1, ccsidr_el1 // w1 = ccsidr 31 and w2, w1, #7 // w2 = log2(line len) - 4 32 add w2, w2, #4 // w2 = log2(line len) 33 ubfx w4, w1, #3, #10 // w4 = max way number, right aligned 34 clz w5, w4 // w5 = 32 - log2(ways), bit position of way in DC operand 35 lsl w9, w4, w5 // w9 = max way number, aligned to position in DC operand 36 lsl w12, w8, w5 // w12 = amount to decrement way number per iteration 37 38.Lloop2_inv_cache: 39 ubfx w7, w1, #13, #15 // w7 = max set number, right aligned 40 lsl w7, w7, w2 // w7 = max set number, aligned to position in DC operand 41 lsl w13, w8, w2 // w13 = amount to decrement set number per iteration 42.Lloop3_inv_cache: 43 orr w11, w10, w9 // w11 = combine way number and cache number 44 orr w11, w11, w7 // and set number for DC operand 45 dc isw, x11 // data cache op 46 subs w7, w7, w13 // decrement set number 47 b.ge .Lloop3_inv_cache 48 49 subs x9, x9, x12 // decrement way number 50 b.ge .Lloop2_inv_cache 51.Lskip_inv_cache: 52 add w10, w10, #2 // increment 2x cache level 53 cmp w3, w10 54 dsb sy // ensure completetion of previous cache maintainance instructions 55 b.gt .Lloop1_inv_cache 56.Lfinished_inv_cache: 57 58 // dump the instruction cache as well 59 ic iallu 60 isb 61 ret 62END_FUNC(flush_idcache) 63 64BEGIN_FUNC(set_ttbr0_el1) 65 msr ttbr0_el1, x0 66 /* flushing tlb is not needed since we've enabled asid mechanism */ 67 //dsb sy 68 //tlbi vmalle1is 69 //dsb sy 70 isb 71 ret 72END_FUNC(set_ttbr0_el1) 73