1 /* 2 * Copyright (c) 2023 Institute of Parallel And Distributed Systems (IPADS), Shanghai Jiao Tong University (SJTU) 3 * Licensed under the Mulan PSL v2. 4 * You can use this software according to the terms and conditions of the Mulan PSL v2. 5 * You may obtain a copy of Mulan PSL v2 at: 6 * http://license.coscl.org.cn/MulanPSL2 7 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR 8 * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR 9 * PURPOSE. 10 * See the Mulan PSL v2 for more details. 11 */ 12 #pragma once 13 14 #include <common/types.h> 15 16 #define PLAT_CPU_NUM 1 17 18 void teeos_cfg_init(paddr_t start_pa); 19 20 paddr_t get_tzdram_start(void); 21 22 paddr_t get_tzdram_end(void); 23 24 paddr_t get_gicd_base(void); 25 26 paddr_t get_uart_base(void); 27 28 #define GICD_BASE (KBASE + 0xfd400000) 29 #define GICR_BASE (KBASE + 0xfd460000) 30 31 #define SIZE_128K 0x20000 32 #define GICR_PER_CPU_BASE(CPUID) (GICR_BASE + SIZE_128K * CPUID) 33 34 #define GICH_HCR 0x0 35 #define GICH_VTR 0x4 36 #define GICH_VMCR 0x8 37 #define GICH_MISR 0x10 38 #define GICH_EISR0 0x20 39 #define GICH_EISR1 0x24 40 #define GICH_ELRSR0 0x30 41 #define GICH_ELRSR1 0x34 42 #define GICH_APR 0xf0 43 #define GICH_LR0 0x100 44 45 /* GICD Registers */ 46 #define GICD_CTLR (GICD_BASE+0x000) 47 #define GICD_TYPER (GICD_BASE+0x004) 48 #define GICD_IIDR (GICD_BASE+0x008) 49 #define GICD_IGROUPR(n) (GICD_BASE+0x080+(n)*4) 50 #define GICD_ISENABLER (GICD_BASE+0x100) 51 #define GICD_ICENABLER (GICD_BASE+0x180) 52 #define GICD_ISENABLER_OFFSET (0x100) 53 #define GICD_ICENABLER_OFFSET (0x180) 54 #define GICD_ISPENDR(n) (GICD_BASE+0x200+(n)*4) 55 #define GICD_ICPENDR(n) (GICD_BASE+0x280+(n)*4) 56 #define GICD_ISACTIVER (GICD_BASE+0x300) 57 #define GICD_ICACTIVER (GICD_BASE+0x380) 58 #define GICD_IPRIORITYR (GICD_BASE+0x400) 59 #define GICD_ITARGETSR (GICD_BASE+0x800) 60 #define GICD_ICFGR (GICD_BASE+0xC00) 61 #define GICD_IGRPMODR(n) (GICD_BASE+0xD00+(n)*4) 62 #define GICD_SGIR (GICD_BASE+0xF00) 63 #define GICD_SGIR_CLRPEND (GICD_BASE+0xF10) 64 #define GICD_SGIR_SETPEND (GICD_BASE+0xF20) 65 #define GICD_IROUTER (GICD_BASE+0x6000) 66 67 #define GICD_ENABLE 0x1 68 #define GICD_DISABLE 0x0 69 #define GICD_INT_ACTLOW_LVLTRIG 0x0 70 #define GICD_INT_EN_CLR_X32 0xffffffff 71 #define GICD_INT_EN_SET_SGI 0x0000ffff 72 #define GICD_INT_EN_CLR_PPI 0xffff0000 73 #define GICD_INT_DEF_PRI 0xa0 74 #define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\ 75 (GICD_INT_DEF_PRI << 16) |\ 76 (GICD_INT_DEF_PRI << 8) |\ 77 GICD_INT_DEF_PRI) 78 79 #define GICD_CTLR_RWP (1U << 31) 80 #define GICD_CTLR_DS (1U << 6) 81 #define GICD_CTLR_ARE_S (1U << 4) 82 #define GICD_CTLR_ENABLE_G1_S (1U << 2) 83 #define GICD_CTLR_ENABLE_G0 (1U << 0) 84 85 #define GICD_TYPER_RSS (1U << 26) 86 #define GICD_TYPER_LPIS (1U << 17) 87 #define GICD_TYPER_MBIS (1U << 16) 88 89 /* GICD Register bits */ 90 #define GICD_CTL_ENABLE 0x1 91 #define GICD_TYPE_LINES 0x01F 92 #define GICD_TYPE_CPUS_SHIFT 5 93 #define GICD_TYPE_CPUS 0x0E0 94 #define GICD_TYPE_SEC 0x400 95 96 /* GICD_SGIR defination */ 97 #define GICD_SGIR_SGIINTID_SHIFT 0 98 #define GICD_SGIR_CPULIST_SHIFT 16 99 #define GICD_SGIR_LISTFILTER_SHIFT 24 100 #define GICD_SGIR_VAL(listfilter, cpulist, sgi) \ 101 (((listfilter) << GICD_SGIR_LISTFILTER_SHIFT) | \ 102 ((cpulist) << GICD_SGIR_CPULIST_SHIFT) | \ 103 ((sgi) << GICD_SGIR_SGIINTID_SHIFT)) 104 105 #define GIC_INTID_PPI 16 106 #define GIC_INTID_SPI 32 107 #define GIC_INTID_SPI_UART6 (GIC_INTID_SPI + 79) 108 #define GIC_INTID_PPI_EL1_PHYS_TIMER (GIC_INTID_PPI + 14) 109 #define GIC_INTID_PPI_EL1_VIRT_TIMER (GIC_INTID_PPI + 11) 110 #define GIC_INTID_PPI_NS_EL2_PHYS_TIMER (GIC_INTID_PPI + 10) 111 #define GIC_INTID_PPI_EL3_PHYS_TIMER (GIC_INTID_PPI + 13) 112 113 #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) 114 #define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1) 115 #define GICD_TYPER_IRQS(typer) (((((typer) & 0x1f) + 1) << 5) - 1) 116 117 /* GICR Registers */ 118 /* Redistributor - RD_BASE */ 119 #define GICR_CTLR_OFFSET 0x00000000U 120 #define GICR_IIDR_OFFSET 0x00000004U 121 #define GICR_TYPER_OFFSET 0x00000008U 122 #define GICR_STATUSR_OFFSET 0x00000010U 123 #define GICR_WAKER_OFFSET 0x00000014U 124 #define GICR_MPAMIDR_OFFSET 0x00000018U 125 #define GICR_PARTIDR_OFFSET 0x0000001CU 126 #define GICR_SETLPIR_OFFSET 0x00000040U 127 #define GICR_CLRLPIR_OFFSET 0x00000048U 128 #define GICR_PROPBASER_OFFSET 0x00000070U 129 #define GICR_PENDBASER_OFFSET 0x00000078U 130 131 #define GICR_WAKER(CPUID) (GICR_PER_CPU_BASE(CPUID) + GICR_WAKER_OFFSET) 132 #define GICR_WAKER_ProcessorSleep (1U << 1) 133 #define GICR_WAKER_ChildrenAsleep (1U << 2) 134 #define GICR_IGROUPR0(CPUID) (GICR_PER_CPU_BASE(CPUID) + SIZE_64K + 0x080) 135 136 /* Redistributor - SGI_BASE */ 137 #define GICR_SGI_BASE_OFFSET 0x10000U 138 #define GICR_IGROUPR0_OFFSET 0x00000080U 139 #define GICR_IGROUPR_E_OFFSET 0x00000084U 140 #define GICR_ISENABLER0_OFFSET 0x00000100U 141 #define GICR_ISENABLER_E_OFFSET 0x00000104U 142 #define GICR_ICENABLER0_OFFSET 0x00000180U 143 #define GICR_ICENABLER_E_OFFSET 0x00000184U 144 #define GICR_ISPENDR0_OFFSET 0x00000200U 145 #define GICR_ISPENDR_E_OFFSET 0x00000204U 146 #define GICR_ICPENDR0_OFFSET 0x00000280U 147 #define GICR_ICPENDR_E_OFFSET 0x00000284U 148 #define GICR_ISACTIVER0_OFFSET 0x00000300U 149 #define GICR_ISACTIVER_E_OFFSET 0x00000304U 150 #define GICR_ICACTIVER0_OFFSET 0x00000380U 151 #define GICR_ICACTIVER_E_OFFSET 0x00000384U 152 #define GICR_IPRIORITYR_OFFSET 0x00000400U 153 #define GICR_IPRIORITYR_E_OFFSET 0x00000420U 154 #define GICR_ICFGR0_OFFSET 0x00000C00U 155 #define GICR_ICFGR1_OFFSET 0x00000C04U 156 #define GICR_ICFGR_E_OFFSET 0x00000C08U 157 #define GICR_IGRPMODR0_OFFSET 0x00000D00U 158 #define GICR_IGRPMODR_E_OFFSET 0x00000D04U 159 #define GICR_NSACR_OFFSET 0x00000E00U 160 161 /* Default priority value. */ 162 #define DEFAULT_PMR_VALUE 0xF0 163 164 #define GICD_ICACTIVER_DEFAULT_MASK 0xffffffff 165 #define GICD_ICENABLER_DEFAULT_MASK 0xffffffff 166 #define GICD_ICPENDR_DEFAULT_MASK 0xffffffff 167 #define GICD_IGROUPR_DEFAULT_MASK 0xffffffff 168 #define GICD_IGRPMODR_DEFAULT_MASK 0xffffffff 169 170 #define GICR_ICACTIVER0_DEFAULT_MASK 0xffffffff 171 #define GICR_ICENABLER0_DEFAULT_MASK 0xffff0000 172 #define GICR_ISENABLER0_DEFAULT_MASK 0x0000ffff 173 #define GICR_IGROUPR0_DEFAULT_MASK 0xffffffff 174 175 /* Number of interrupts in one register */ 176 #define NUM_INTS_PER_REG 32 177 178 /* 179 * GICv3 cpu interface registers. 180 * Refers to GICv3 Architecture Manual 181 */ 182 183 /* ICC_CTLR_EL1 */ 184 #define ICC_CTLR_EL1_EOImode_SHIFT 1 185 #define ICC_CTLR_EL1_CBPR_SHIFT 0 186 #define ICC_CTLR_EL1_PRIbits_SHIFT 8 187 #define ICC_CTLR_EL1_PRIbits_MASK 0x700 188 189 /* ICC_SRE_EL1 */ 190 #define ICC_SRE_EL1_SRE (1U << 0) 191 192 /* SGI registers */ 193 #define ICC_SGI1R_SGI_ID_SHIFT 24 194 #define ICC_SGI1R_AFFINITY_1_SHIFT 16 195 #define ICC_SGI1R_AFFINITY_2_SHIFT 32 196 #define ICC_SGI1R_AFFINITY_3_SHIFT 48 197 #define ICC_SGI1R_RS_SHIFT 44 198 199 #define stringify(x) #x 200 #define ICC_IGRPEN1_EL1 stringify(S3_0_C12_C12_7) 201 #define ICC_SRE_EL1 stringify(S3_0_C12_C12_5) 202 #define ICC_CTLR_EL1 stringify(S3_0_C12_C12_4) 203 #define ICC_BPR1_EL1 stringify(S3_0_C12_C12_3) 204 #define ICC_EOIR1_EL1 stringify(S3_0_C12_C12_1) 205 #define ICC_IAR1_EL1 stringify(S3_0_C12_C12_0) 206 #define ICC_SGI1R_EL1 stringify(S3_0_C12_C11_5) 207 #define ICC_DIR_EL1 stringify(S3_0_C12_C11_1) 208 #define ICC_AP1R0_EL1 stringify(S3_0_C12_C9_0) 209 #define ICC_AP1R1_EL1 stringify(S3_0_C12_C9_1) 210 #define ICC_AP1R2_EL1 stringify(S3_0_C12_C9_2) 211 #define ICC_AP1R3_EL1 stringify(S3_0_C12_C9_3) 212 #define ICC_AP0R0_EL1 stringify(S3_0_C12_C8_4) 213 #define ICC_AP0R1_EL1 stringify(S3_0_C12_C8_5) 214 #define ICC_AP0R2_EL1 stringify(S3_0_C12_C8_6) 215 #define ICC_AP0R3_EL1 stringify(S3_0_C12_C8_7) 216 #define ICC_PMR_EL1 stringify(S3_0_C4_C6_0) 217 218 #define read_sys_reg(sys_reg) \ 219 ({ \ 220 u32 val; \ 221 asm volatile("mrs %0, " sys_reg : "=r"(val) : : "memory"); \ 222 val; \ 223 }) 224 225 #define write_sys_reg(sys_reg, val) \ 226 asm volatile("msr " sys_reg ", %0" : : "r"((val)) : "memory") 227 228 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ 229 ((mpidr >> (level * 8)) & 0xFF) 230 231 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 232 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 233 << ICC_SGI1R_AFFINITY_##level##_SHIFT) 234 235 #define MPIDR_RS(mpidr) (((mpidr)&0xF0UL) >> 4) 236 #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) 237 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) 238