1 /**
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 *
15 * Description: Application core main function for standard \n
16 *
17 * History: \n
18 * 2022-07-27, Create file. \n
19 */
20 #include "chip_io.h"
21 #include "tcxo.h"
22 #include "soc_porting.h"
23 #include "platform_core.h"
24 #include "timer_porting.h"
25 #include "systick_porting.h"
26 #include "watchdog_porting.h"
27 #include "tcxo_porting.h"
28 #include "uart_porting.h"
29 #include "i2c_porting.h"
30 #include "clock_init.h"
31
32
33 #ifdef BOARD_ASIC
34 #define PMU_RXLDO_1P0 0x40003134
35 #define PMU_PLLLDO_1P0 0x40003148
36 #define PMU_LNALDO_1P0 0x40003138
37 #define PMU_VCOLDO_1P0 0x40003140
38 #define PMU_TXLDO_1P8 0x40003168
39 #define PMU_ABBLDO_1P0 0x40003144
40 #define ISO_SIG 0x40003230
41 #define CLDO_SUB_CRG_CKEN_CTL1 0x44001104
42 #define DBG_CMU_XO_PD 0x40003400
43 #define CMU_CLK_WF_TX 0x40003440
44 #define CMU_CLK_WF_RX 0x40003438
45 #define CMU_CLK_BT_TX 0x40003444
46 #define CMU_CLK_BT_RX 0x4000343c
47 #define CLDO_CRG_CLK_SEL 0x44001134
48 #define DELAY_120_US 120
49 #define DELAY_10_US 10
50 #define DELAY_1_US 1
51 #define LDO_EN 0x4070
52 #define LDO_EN_DELAY_ENABLE 0x6070
53 #define PMU_VCOLDO_1P0_EN 0x4000
54 #define PMU_VCOLDO_1P0_EN_DELAY 0x6000
55 #define PMU_TXLDO_1P8_EN 0x4030
56 #define PMU_TXLDO_1P8_EN_DELAY 0x6030
57 #define RELEASE_ADDA_ISOLATION_SIGNAL 0x3
58 #define ONEN_RF_PLL 0x5
59 #define OFFSET_0 0
60 #define START_BIT2 2
61 #define BIT_LEN_2 2
62 #define WIFI_TX_160M 0x1
63 #define WIFI_RX_80M 0x2
64 #define BT_TX_160M 0x1
65 #define BT_TX_32M 0x3
66 #define RG_CMU_XO_TRIM_REV_SEL 0X30000
67 #define RG_CMU_XO_TRIM_COARSE 0X3083C
68 #define PMU_PLLLDO_1P0_DATA1 0x4080
69 #define PMU_PLLLDO_1P0_DATA2 0x6080
70
open_rf_power(void)71 void open_rf_power(void)
72 {
73 writel(CMU_XO_SIG, RG_CMU_XO_TRIM_REV_SEL);
74 writel(CMU_XO_SIG, RG_CMU_XO_TRIM_COARSE);
75
76 writel(PMU_RXLDO_1P0, LDO_EN);
77 uapi_tcxo_delay_us(DELAY_120_US);
78 writel(PMU_RXLDO_1P0, LDO_EN_DELAY_ENABLE);
79 uapi_tcxo_delay_us(DELAY_10_US);
80 writel(PMU_PLLLDO_1P0, PMU_PLLLDO_1P0_DATA1);
81 uapi_tcxo_delay_us(DELAY_120_US);
82 writel(PMU_PLLLDO_1P0, PMU_PLLLDO_1P0_DATA2);
83 uapi_tcxo_delay_us(DELAY_10_US);
84 writel(PMU_LNALDO_1P0, LDO_EN);
85 uapi_tcxo_delay_us(DELAY_120_US);
86 writel(PMU_LNALDO_1P0, LDO_EN_DELAY_ENABLE);
87 uapi_tcxo_delay_us(DELAY_10_US);
88 writel(PMU_VCOLDO_1P0, PMU_VCOLDO_1P0_EN);
89 uapi_tcxo_delay_us(DELAY_120_US);
90 writel(PMU_VCOLDO_1P0, PMU_VCOLDO_1P0_EN_DELAY);
91 uapi_tcxo_delay_us(DELAY_10_US);
92 writel(PMU_TXLDO_1P8, PMU_TXLDO_1P8_EN);
93 uapi_tcxo_delay_us(DELAY_120_US);
94 writel(PMU_TXLDO_1P8, PMU_TXLDO_1P8_EN_DELAY);
95 uapi_tcxo_delay_us(DELAY_10_US);
96 writel(PMU_ABBLDO_1P0, LDO_EN);
97 uapi_tcxo_delay_us(DELAY_120_US);
98 writel(PMU_ABBLDO_1P0, LDO_EN_DELAY_ENABLE);
99 writel(ISO_SIG, RELEASE_ADDA_ISOLATION_SIGNAL);
100 }
101 #define CLDO_CRG_DIV_CTL9 0x4400112c
102 #define CLDO_CRG_DIV_CTL7 0x44001124
103 #define TRNG_DIV2 2
104 #define TRNG_DIV4 4
105 #define TRNG_LEN 3
106 #define TSENSOR_DIV_LEN 6
107 #define TSENSOR_24_DIV 0x18
108 #define TSENSOR_40_DIV 0x28
switch_clock(void)109 void switch_clock(void)
110 {
111 writel(DBG_CMU_XO_PD, ONEN_RF_PLL); // 打开RFPLL基准时钟
112 uapi_tcxo_delay_us(DELAY_10_US);
113 reg_setbit(CLDO_CRG_CLK_SEL, OFFSET_0, POS_20); // WIFI_MAC时钟由tcxo切换到PLL
114 reg_clrbit(CLDO_SUB_CRG_CKEN_CTL1, OFFSET_0, POS_13); // 关闭WIFI入口总时钟
115 uapi_tcxo_delay_us(DELAY_1_US);
116 reg_setbit(CLDO_CRG_CLK_SEL, OFFSET_0, POS_19); // WIFI_PHY时钟由tcxo切换到PLL
117 uapi_tcxo_delay_us(DELAY_1_US);
118 reg_setbit(CLDO_SUB_CRG_CKEN_CTL1, OFFSET_0, POS_13); // 打开WIFI入口总时钟
119 reg_setbit(CLDO_CRG_CLK_SEL, OFFSET_0, POS_0); // RF_CTL时钟由tcxo切换到PLL
120
121 reg_clrbit(CLDO_SUB_CRG_CKEN_CTL1, 0, POS_18); // close uart clock
122 reg_clrbit(CLDO_SUB_CRG_CKEN_CTL1, 0, POS_19);
123 reg_clrbit(CLDO_SUB_CRG_CKEN_CTL1, 0, POS_20);
124 reg_setbit(CLDO_CRG_CLK_SEL, 0, POS_1); // switch uart clock to pll
125 reg_setbit(CLDO_CRG_CLK_SEL, 0, POS_2);
126 reg_setbit(CLDO_CRG_CLK_SEL, 0, POS_3);
127 reg_setbit(CLDO_SUB_CRG_CKEN_CTL1, 0, POS_18); // open uart clock
128 reg_setbit(CLDO_SUB_CRG_CKEN_CTL1, 0, POS_19);
129 reg_setbit(CLDO_SUB_CRG_CKEN_CTL1, 0, POS_20);
130
131 if (get_tcxo_freq() == CLK24M_TCXO) {
132 // trng
133 reg_clrbit(CLDO_CRG_DIV_CTL9, 0, POS_9);
134 reg32_setbits(CLDO_CRG_DIV_CTL9, POS_6, TRNG_LEN, TRNG_DIV2);
135 reg_setbit(CLDO_CRG_DIV_CTL9, 0, POS_9);
136 // tsensor
137 reg_clrbit(CLDO_CRG_DIV_CTL7, 0, POS_18);
138 reg32_setbits(CLDO_CRG_DIV_CTL7, POS_6, TSENSOR_DIV_LEN, TSENSOR_24_DIV);
139 reg_setbit(CLDO_CRG_DIV_CTL7, 0, POS_18);
140 } else {
141 // trng
142 reg_clrbit(CLDO_CRG_DIV_CTL9, 0, POS_9);
143 reg32_setbits(CLDO_CRG_DIV_CTL9, POS_6, TRNG_LEN, TRNG_DIV4);
144 reg_setbit(CLDO_CRG_DIV_CTL9, 0, POS_9);
145 // tsensor
146 reg_clrbit(CLDO_CRG_DIV_CTL7, 0, POS_18);
147 reg32_setbits(CLDO_CRG_DIV_CTL7, POS_6, TSENSOR_DIV_LEN, TSENSOR_40_DIV);
148 reg_setbit(CLDO_CRG_DIV_CTL7, 0, POS_18);
149 }
150 }
151
152 #define REQ_24M 24000000
153 #define REQ_40M 40000000
154 #define USEC_PER_SEC 1000000
155 #define UART_PLL_CLOCK 160000000
set_uart_tcxo_clock_period(void)156 void set_uart_tcxo_clock_period(void)
157 {
158 if (get_tcxo_freq() == CLK24M_TCXO) {
159 tcxo_porting_ticks_per_usec_set(REQ_24M / USEC_PER_SEC);
160 timer_porting_clock_value_set(REQ_24M);
161 LOS_SetSysClosk(REQ_24M);
162 watchdog_port_set_clock(REQ_24M);
163 i2c_port_set_clock_value(I2C_BUS_0, REQ_24M);
164 i2c_port_set_clock_value(I2C_BUS_1, REQ_24M);
165 } else {
166 tcxo_porting_ticks_per_usec_set(REQ_40M / USEC_PER_SEC);
167 timer_porting_clock_value_set(REQ_40M);
168 LOS_SetSysClosk(REQ_40M);
169 watchdog_port_set_clock(REQ_40M);
170 i2c_port_set_clock_value(I2C_BUS_0, REQ_40M);
171 i2c_port_set_clock_value(I2C_BUS_1, REQ_40M);
172 }
173 uart_port_set_clock_value(UART_BUS_0, UART_PLL_CLOCK);
174 }
175
176 #endif
177