1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * Description: Basic chip definitions 15 * Author: 16 * Create: 2018-10-15 17 */ 18 #ifndef LIB_COMMON_HEADERS_CHIP_DEFINITIONS_H 19 #define LIB_COMMON_HEADERS_CHIP_DEFINITIONS_H 20 21 /** @defgroup CHIP_Base CHIP Base Definitions 22 * CHIP Base Definitions 23 * @ingroup CHIP_Base 24 * */ 25 /** @defgroup CHIP_ARMCORE CHIP ARM Core Specifics 26 * CHIP ARM Core Application Core Specifics 27 * @ingroup CHIP_Base 28 * @{ 29 * */ 30 #define BT 0 31 #define PROTOCOL 1 32 #define APPS 2 33 #define GNSS 3 34 #define SECURITY 4 35 #define HIFI PROTOCOL 36 #define WIFI 5 37 #define CONTROL_CORE 6 38 #define SENSOR 7 39 40 #define CM3 0 41 #define CM7 1 42 #define RISCV31 2 43 #define RISCV70 3 44 #define RISCV32 4 45 46 #define CHIP_LIBRA (TARGET_CHIP_LIBRA) 47 #define CHIP_SOCMN1 (TARGET_CHIP_SOCMN1) 48 #define CHIP_BS25 (TARGET_CHIP_BS25) 49 #define CHIP_BRANDY (TARGET_CHIP_BRANDY) 50 #define CHIP_SW39 (TARGET_CHIP_SW39) 51 #define CHIP_SW21 (TARGET_CHIP_SW21) 52 53 #if (CHIP_LIBRA == 1) 54 #define MASTER_BY_ALL APPS 55 #define CORE_NUMS 5 // Total cores in chip 56 #define CPU_NUM 3 // Total cpus in chip 57 #elif (CHIP_SOCMN1 == 1) 58 #define MASTER_BY_ALL APPS 59 #define CORE_NUMS 4 // Total cores in chip 60 #define CPU_NUM 3 // Total cpus in chip 61 #elif (CHIP_BS25 == 1) 62 #define MASTER_BY_ALL APPS 63 #define CORE_NUMS 2 // Total cores in chip 64 #define CPU_NUM 2 // Total cpus in chip 65 #elif (CHIP_BS20 == 1 || CHIP_BS21 == 1 || CHIP_BS21A == 1 || \ 66 CHIP_BS21E == 1 || CHIP_BS22 == 1 || CHIP_BS26 == 1) 67 #define MASTER_BY_ALL APPS 68 #define CORE_NUMS 1 // Total cores in chip 69 #define CPU_NUM 1 // Total cpus in chip 70 #elif (CHIP_WS53 == 1) 71 #define MASTER_BY_ALL APPS 72 #define CORE_NUMS 2 // Total cores in chip 73 #define CPU_NUM 2 // Total cpus in chip 74 #elif (CHIP_WS63 == 1) 75 #define MASTER_BY_ALL APPS 76 #define CORE_NUMS 1 // Total cores in chip 77 #define CPU_NUM 1 // Total cpus in chip 78 #elif (CHIP_BRANDY == 1) 79 #define MASTER_BY_ALL APPS 80 #define CORE_NUMS 3 // Total cores in chip 81 #define CPU_NUM 3 // Total cpus in chip 82 #elif (CHIP_SW39 == 1) 83 #define MASTER_BY_ALL APPS 84 #define CORE_NUMS 6 // Total cores in chip 85 #define CPU_NUM 3 // Total cpus in chip 86 #elif (CHIP_CAT1 == 1) 87 #define MASTER_BY_ALL APPS 88 #define CORE_NUMS 2 // Total cores in chip 89 #define CPU_NUM 2 // Total cpus in chip 90 #elif (CHIP_SW21 == 1) 91 #define MASTER_BY_ALL APPS 92 #define CORE_NUMS 5 // Total cores in chip 93 #define CPU_NUM 5 // Total cpus in chip 94 #else 95 #error Please define master control core 96 #endif 97 98 #define OTHER_CPU_NUM (CPU_NUM - 1) // Other cpus number, exclude current cpu. 99 100 #define MASTER_BY_LIBRA_ONLY (CHIP_LIBRA && (CORE == APPS)) 101 #define MASTER_BY_SOCMN1_ONLY (CHIP_SOCMN1 && (CORE == APPS)) 102 #define MASTER_BY_BS25_ONLY (CHIP_BS25 && (CORE == APPS)) 103 #define MASTER_BY_BS20_ONLY (CHIP_BS20 && (CORE == APPS)) 104 #define MASTER_BY_BS21_ONLY (CHIP_BS21 && (CORE == APPS)) 105 #define MASTER_BY_BS21E_ONLY (CHIP_BS21E && (CORE == APPS)) 106 #define MASTER_BY_BS21A_ONLY (CHIP_BS21A && (CORE == APPS)) 107 #define MASTER_BY_BS22_ONLY (CHIP_BS22 && (CORE == APPS)) 108 #define MASTER_BY_BS26_ONLY (CHIP_BS26 && (CORE == APPS)) 109 #define MASTER_BY_BRANDY_ONLY (CHIP_BRANDY && (CORE == APPS)) 110 #define MASTER_BY_WS53_ONLY (CHIP_WS53 && (CORE == APPS)) 111 #define MASTER_BY_SW39_ONLY (CHIP_SW39 && (CORE == APPS)) 112 #define MASTER_BY_SW21_ONLY (CHIP_SW21 && (CORE == APPS)) 113 114 #define MASTER_ONLY (MASTER_BY_LIBRA_ONLY || \ 115 MASTER_BY_SOCMN1_ONLY || MASTER_BY_BS25_ONLY || \ 116 MASTER_BY_BRANDY_ONLY || MASTER_BY_BS20_ONLY || \ 117 MASTER_BY_BS21_ONLY || MASTER_BY_BS21A_ONLY || \ 118 MASTER_BY_BS22_ONLY || MASTER_BY_BS26_ONLY || \ 119 MASTER_BY_WS53_ONLY || MASTER_BY_SW39_ONLY || \ 120 MASTER_BY_SW21_ONLY || MASTER_BY_BS21E_ONLY) 121 122 #define MCU_ONLY (MASTER_BY_LIBRA_ONLY || MASTER_BY_SOCMN1_ONLY || \ 123 MASTER_BY_BS25_ONLY || MASTER_BY_BRANDY_ONLY || \ 124 MASTER_BY_WS53_ONLY || CHIP_WS63 || CHIP_BS20 || CHIP_BS21 || CHIP_BS21E || \ 125 CHIP_BS21A || CHIP_BS22 || CHIP_BS26 || MASTER_BY_SW39_ONLY || \ 126 MASTER_BY_SW21_ONLY) 127 128 129 #define SLAVE_BY_LIBRA_BT (CHIP_LIBRA && (CORE == BT)) 130 #define SLAVE_BY_LIBRA_GNSS (CHIP_LIBRA && (CORE == GNSS)) 131 #define SLAVE_BY_LIBRA_SECURITY (CHIP_LIBRA && (CORE == SECURITY)) 132 #define SLAVE_BY_LIBRA_ONLY (SLAVE_BY_LIBRA_BT || SLAVE_BY_LIBRA_GNSS || SLAVE_BY_LIBRA_SECURITY) 133 #define SLAVE_BY_SOCMN1_ONLY (CHIP_SOCMN1 && (CORE == BT)) 134 #define SLAVE_BY_SW39_BT (CHIP_SW39 && (CORE == BT)) 135 #define SLAVE_BY_BS25_ONLY (CHIP_BS25 && (CORE == BT)) 136 #define SLAVE_BY_BRANDY_BT (CHIP_BRANDY && (CORE == BT)) 137 #define SLAVE_BY_BRANDY_DSP (CHIP_BRANDY && (CORE == DSP)) 138 #define SLAVE_BY_BRANDY_ONLY (SLAVE_BY_BRANDY_BT || SLAVE_BY_BRANDY_DSP) 139 #define SLAVE_BY_WS53_ONLY (CHIP_WS53 && (CORE == CONTROL_CORE)) 140 141 #define CHIP_LIBRA_FPGA (CHIP_LIBRA && (LIBRA_CHIP_FPGA)) 142 #define CHIP_LIBRA_CS (CHIP_LIBRA && (LIBRA_CHIP_CS)) 143 144 #define CHIP_SOCMN1_FPGA (CHIP_SOCMN1 && (SOCMN1_CHIP_FPGA)) 145 #define CHIP_SOCMN1_V100 (CHIP_SOCMN1 && (SOCMN1_CHIP_V100)) 146 #define CHIP_SOCMN1_V200 (CHIP_SOCMN1 && (SOCMN1_CHIP_V200)) 147 148 #define CHIP_BS25_FPGA (CHIP_BS25 && (BS25_CHIP_FPGA)) 149 #define CHIP_BS25_V100 (CHIP_BS25 && (BS25_CHIP_V100)) 150 151 #ifdef PRE_FPGA 152 #define FPGA 1 153 #define ASIC 0 154 #endif 155 156 #ifdef PRE_ASIC 157 #define FPGA 0 158 #define ASIC 1 159 #endif 160 161 #define CHIP_BS20_FPGA (CHIP_BS20 && (FPGA)) 162 #define CHIP_BS20_V100 (CHIP_BS20 && (ASIC)) 163 164 #define CHIP_BS21_FPGA (CHIP_BS21 && (FPGA)) 165 #define CHIP_BS21_V100 (CHIP_BS21 && (ASIC)) 166 167 #define CHIP_BS21E_FPGA (CHIP_BS21E && (FPGA)) 168 #define CHIP_BS21E_V100 (CHIP_BS21E && (ASIC)) 169 170 #define CHIP_BS21A_FPGA (CHIP_BS21A && (FPGA)) 171 #define CHIP_BS21A_V100 (CHIP_BS21A && (ASIC)) 172 173 #define CHIP_BS22_FPGA (CHIP_BS22 && (FPGA)) 174 #define CHIP_BS22_V100 (CHIP_BS22 && (ASIC)) 175 176 #define CHIP_BS26_FPGA (CHIP_BS26 && (FPGA)) 177 #define CHIP_BS26_V100 (CHIP_BS26 && (ASIC)) 178 179 #define CHIP_WS63_FPGA (CHIP_WS63 && (FPGA)) 180 #define CHIP_WS63_V100 (CHIP_WS63 && (ASIC)) 181 182 #define CHIP_BRANDY_FPGA (CHIP_BRANDY && (BRANDY_CHIP_FPGA)) 183 #define CHIP_BRANDY_V100 (CHIP_BRANDY && (BRANDY_CHIP_V100)) 184 185 #define CHIP_SW39_FPGA (CHIP_SW39 && (SW39_CHIP_FPGA)) 186 187 #define CHIP_SW21_FPGA (CHIP_SW21 && (SW21_CHIP_FPGA)) 188 #define CHIP_SW21_V100 (CHIP_SW21 && (SW21_CHIP_V100)) 189 190 #define CHIP_WS53_FPGA (CHIP_WS53 && (FPGA)) 191 #define CHIP_WS53_V100 (CHIP_WS53 && (ASIC)) 192 193 #define CHIP_FPGA (CHIP_LIBRA_FPGA || CHIP_SOCMN1_FPGA || CHIP_BS25_FPGA || CHIP_SW39_FPGA || \ 194 CHIP_BRANDY_FPGA || CHIP_BS20_FPGA || CHIP_BS21_FPGA || CHIP_BS21A_FPGA || \ 195 CHIP_BS22_FPGA || CHIP_BS26_FPGA || CHIP_WS63_FPGA || CHIP_WS53_FPGA || \ 196 CHIP_SW21_FPGA || CHIP_BS21E_FPGA) 197 198 #define CHIP_SOCMN1_ASIC (CHIP_SOCMN1_V100 || CHIP_SOCMN1_V200) 199 #define CHIP_BS25_ASIC (CHIP_BS25_V100) 200 #define CHIP_BS20_ASIC (CHIP_BS20_V100) 201 #define CHIP_BS21_ASIC (CHIP_BS21_V100) 202 #define CHIP_BS21E_ASIC (CHIP_BS21E_V100) 203 #define CHIP_BS21A_ASIC (CHIP_BS21A_V100) 204 #define CHIP_BS22_ASIC (CHIP_BS22_V100) 205 #define CHIP_BS26_ASIC (CHIP_BS26_V100) 206 #define CHIP_BRANDY_ASIC (CHIP_BRANDY_V100) 207 #define CHIP_WS63_ASIC (CHIP_WS63_V100) 208 #define CHIP_WS53_ASIC (CHIP_WS53_V100) 209 #define CHIP_SW21_ASIC (CHIP_SW21_V100) 210 211 #define CHIP_ASIC (CHIP_LIBRA_CS || CHIP_SOCMN1_ASIC || \ 212 CHIP_BS25_ASIC || CHIP_BRANDY_ASIC || \ 213 CHIP_BS20_ASIC || CHIP_BS21_ASIC || \ 214 CHIP_BS21A_ASIC || CHIP_BS22_ASIC || \ 215 CHIP_BS26_ASIC || CHIP_WS63_ASIC || \ 216 CHIP_WS53_ASIC || CHIP_SW21_ASIC || \ 217 CHIP_BS21E_ASIC) 218 219 /** @} end of group CHIP_ARMCORE */ 220 #endif 221