1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 * Description: the header file for hcc ipc adapt layer.
15 * Author:
16 * Create: 2023-02-21
17 */
18 #ifndef HCC_IPC_ADAPT_H
19 #define HCC_IPC_ADAPT_H
20
21 #include "td_type.h"
22 #include "hcc_bus.h"
23 #include "hcc_queue.h"
24 #include "hcc_cfg_comm.h"
25
26 #ifdef __cplusplus
27 #if __cplusplus
28 extern "C" {
29 #endif
30 #endif
31
32 #ifdef CONFIG_HCC_SUPPORT_IPC
33
34 #define IPC_MEM_MSG_MAX 4
35 #define HCC_PREMEM_LEN 4
36 #define HCC_LOSS_MEM_MAX 8
37 #define IPC_MAX_XFER_LEN 2048
38
39 #define IPC_CHAN_DATA 0
40 #define IPC_CHAN_MSG 1
41
42 #define IPC_MEM_PRIV_MSG_FLAG 0x5A
43 #define IPC_MEM_PRIV_MSG_FLAG_OFFSET 8
44 #define IPC_MEM_PRIV_MSG (IPC_MEM_PRIV_MSG_FLAG << IPC_MEM_PRIV_MSG_FLAG_OFFSET)
45
46 enum {
47 HCC_IPC_MEM_REQUEST = 1,
48 HCC_IPC_MEM_REPLY,
49 HCC_IPC_MEM_TX_COMPLETE,
50 HCC_IPC_MEM_RX_START,
51 HCC_IPC_MEM_RX_COMPLETE,
52 HCC_IPC_MEM_PRIV_MSG = IPC_MEM_PRIV_MSG,
53 HCC_IPC_MEM_CLEAR_PREMEM,
54 };
55
56 typedef struct hcc_ipc_mem_request {
57 td_u8 type;
58 td_u8 hcc_queue_id;
59 td_u8 cnt;
60 td_u8 rsv;
61 td_u16 data_len[IPC_MEM_MSG_MAX];
62 } hcc_ipc_mem_request_t;
63
64 typedef struct hcc_ipc_mem_reply {
65 td_u8 type;
66 td_u8 hcc_queue_id;
67 td_u8 cnt;
68 td_u8 rsv;
69 td_u16 data_len[IPC_MEM_MSG_MAX];
70 td_u8 *addr[IPC_MEM_MSG_MAX];
71 } hcc_ipc_mem_reply_t;
72
73 typedef struct hcc_ipc_mem_complete {
74 td_u8 type;
75 td_u8 hcc_queue_id;
76 td_u8 cnt;
77 td_u8 rsv;
78 td_u8 *addr[IPC_MEM_MSG_MAX];
79 } hcc_ipc_mem_complete_t;
80
81 typedef struct hcc_ipc_cfg {
82 td_u8 premem_len;
83 td_u8 lossmem_max;
84 } hcc_ipc_cfg_t;
85
86 td_void hcc_ipc_complement_mem(td_void);
87 hcc_bus *hcc_adapt_ipc_load(hcc_handler *hcc);
88 td_void hcc_adapt_ipc_unload(td_void);
89 td_bool hcc_ipc_tx_dma_is_busy(hcc_queue_dir dir, hcc_trans_queue *queue);
90 td_void hcc_ipc_flowctrl_on(hcc_bus *hcc_bus, td_bool unc_check);
91 td_void hcc_ipc_flowctrl_off(hcc_bus *hcc_bus, td_bool force_check);
92 td_s32 hcc_adapt_ipc_cfg(hcc_ipc_cfg_t *cfg);
93 bus_dev_ops* hcc_ipc_get_bus_ops(td_void);
94 #endif /* CONFIG_HCC_SUPPORT_IPC */
95 td_void hcc_ipc_clear_premem(td_void);
96
hcc_check_pre_req_queue(TD_CONST hcc_trans_queue * queue)97 static inline td_bool hcc_check_pre_req_queue(TD_CONST hcc_trans_queue *queue)
98 {
99 return queue->queue_ctrl->transfer_mode == HCC_IPC_TRANS_PREMEM;
100 }
101 struct osal_list_head *hcc_ipc_get_pre_mem_list(td_u8 queue_id);
102
103 #ifdef __cplusplus
104 #if __cplusplus
105 }
106 #endif
107 #endif
108
109 #endif /* HCC_IPC_ADAPT_H */
110