1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK1808_H 4 #define _DT_BINDINGS_CLK_ROCKCHIP_RK1808_H 5 6 /* core clocks */ 7 #define PLL_APLL 1 8 #define PLL_DPLL 2 9 #define PLL_CPLL 3 10 #define PLL_GPLL 4 11 #define PLL_NPLL 5 12 #define PLL_PPLL 6 13 #define ARMCLK 7 14 15 #define DCLK_VOPRAW 10 16 #define DCLK_VOPLITE 11 17 #define DCLK_CIF 12 18 #define XIN24M_DIV 13 19 20 /* sclk (special clocks) */ 21 #define USB480M 20 22 #define SCLK_PVTM_CORE 21 23 #define SCLK_NPU 22 24 #define SCLK_PVTM_NPU 23 25 #define SCLK_DDRCLK 24 26 #define SCLK_I2S0_8CH_TX_MUX 25 27 #define SCLK_I2S0_8CH_RX_MUX 26 28 #define SCLK_RTC32K_PMU 27 29 #define SCLK_TXESC 28 30 #define SCLK_RGA 29 31 #define SCLK_ISP 30 32 #define SCLK_CIF_OUT 31 33 #define SCLK_PCIE_AUX 32 34 #define SCLK_USB3_OTG0_REF 33 35 #define SCLK_USB3_OTG0_SUSPEND 34 36 #define SCLK_SDIO_DIV 35 37 #define SCLK_SDIO_DIV50 36 38 #define SCLK_SDIO 37 39 #define SCLK_SDIO_DRV 38 40 #define SCLK_SDIO_SAMPLE 39 41 #define SCLK_EMMC_DIV 40 42 #define SCLK_EMMC_DIV50 41 43 #define SCLK_EMMC 42 44 #define SCLK_EMMC_DRV 43 45 #define SCLK_EMMC_SAMPLE 44 46 #define SCLK_SDMMC_DIV 45 47 #define SCLK_SDMMC_DIV50 46 48 #define SCLK_SDMMC 47 49 #define SCLK_SDMMC_DRV 48 50 #define SCLK_SDMMC_SAMPLE 49 51 #define SCLK_SFC 50 52 #define SCLK_GMAC_OUT 51 53 #define SCLK_GMAC_SRC 52 54 #define SCLK_GMAC 53 55 #define SCLK_GMAC_REF 54 56 #define SCLK_GMAC_REFOUT 55 57 #define SCLK_GMAC_RGMII_SPEED 56 58 #define SCLK_GMAC_RMII_SPEED 57 59 #define SCLK_GMAC_RX_TX 58 60 #define SCLK_CRYPTO 59 61 #define SCLK_CRYPTO_APK 60 62 #define SCLK_UART1 61 63 #define SCLK_UART2 62 64 #define SCLK_UART3 63 65 #define SCLK_UART4 64 66 #define SCLK_UART5 65 67 #define SCLK_UART6 66 68 #define SCLK_UART7 67 69 #define SCLK_I2C1 68 70 #define SCLK_I2C2 69 71 #define SCLK_I2C3 70 72 #define SCLK_I2C4 71 73 #define SCLK_I2C5 72 74 #define SCLK_SPI0 73 75 #define SCLK_SPI1 74 76 #define SCLK_SPI2 75 77 #define SCLK_TSADC 76 78 #define SCLK_SARADC 77 79 #define SCLK_EFUSE_S 78 80 #define SCLK_EFUSE_NS 79 81 #define DBCLK_GPIO1 80 82 #define DBCLK_GPIO2 81 83 #define DBCLK_GPIO3 82 84 #define DBCLK_GPIO4 83 85 #define SCLK_PWM0 84 86 #define SCLK_PWM1 85 87 #define SCLK_PWM2 86 88 #define SCLK_TIMER0 87 89 #define SCLK_TIMER1 88 90 #define SCLK_TIMER2 89 91 #define SCLK_TIMER3 90 92 #define SCLK_TIMER4 91 93 #define SCLK_TIMER5 92 94 #define SCLK_PDM 93 95 #define SCLK_I2S0_8CH_TX_SRC 94 96 #define SCLK_I2S0_8CH_TX 95 97 #define SCLK_I2S0_8CH_TX_OUT 96 98 #define SCLK_I2S0_8CH_RX_SRC 97 99 #define SCLK_I2S0_8CH_RX 98 100 #define SCLK_I2S0_8CH_RX_OUT 99 101 #define SCLK_I2S1_2CH_SRC 100 102 #define SCLK_I2S1_2CH 101 103 #define SCLK_I2S1_2CH_OUT 102 104 #define SCLK_WIFI_PMU 103 105 #define SCLK_UART0_PMU 104 106 #define SCLK_PVTM_PMU 105 107 #define SCLK_PMU_I2C0 106 108 #define DBCLK_PMU_GPIO0 107 109 #define SCLK_REF24M_PMU 108 110 #define SCLK_USBPHY_REF 109 111 #define SCLK_MIPIDSIPHY_REF 110 112 #define SCLK_PCIEPHY_REF 111 113 #define SCLK_RTC32K_FRAC 112 114 #define SCLK_32K_IOE 113 115 116 /* aclk gates */ 117 #define ACLK_GIC_PRE 145 118 #define ACLK_GIC 146 119 #define ACLK_VPU 147 120 #define ACLK_NPU 148 121 #define ACLK_IMEM_PRE 153 122 #define ACLK_IMEM0 154 123 #define ACLK_IMEM1 155 124 #define ACLK_IMEM2 156 125 #define ACLK_IMEM3 157 126 #define HSCLK_VIO 158 127 #define ACLK_VOPRAW 159 128 #define ACLK_VOPLITE 160 129 #define ACLK_RGA 161 130 #define ACLK_ISP 162 131 #define ACLK_CIF 163 132 #define HSCLK_PCIE 164 133 #define ACLK_USB3OTG 165 134 #define ACLK_PCIE 166 135 #define ACLK_PCIE_MST 167 136 #define ACLK_PCIE_SLV 168 137 #define MSCLK_PERI 169 138 #define ACLK_GMAC 170 139 #define HSCLK_BUS_PRE 171 140 #define ACLK_CRYPTO 172 141 #define ACLK_DCF 173 142 #define ACLK_DMAC 174 143 144 /* hclk gates */ 145 #define HCLK_NPU 199 146 #define HCLK_VPU 200 147 #define LSCLK_VIO 201 148 #define HCLK_VOPRAW 202 149 #define HCLK_VOPLITE 203 150 #define HCLK_RGA 204 151 #define HCLK_ISP 205 152 #define LSCLK_PCIE 206 153 #define HCLK_HOST 207 154 #define LSCLK_PERI 208 155 #define HCLK_SDIO 209 156 #define HCLK_EMMC 210 157 #define HCLK_SDMMC 211 158 #define HCLK_SFC 212 159 #define MSCLK_BUS_PRE 213 160 #define HCLK_ROM 214 161 #define HCLK_CRYPTO 215 162 #define HCLK_VAD 216 163 #define HCLK_PDM 217 164 #define HCLK_I2S0_8CH 218 165 #define HCLK_I2S1_2CH 219 166 #define MSCLK_CORE_NIU 220 167 #define HSCLK_IMEM 221 168 #define HCLK_HOST_ARB 222 169 #define HCLK_CIF 223 170 171 /* pclk gates */ 172 #define PCLK_DDR 250 173 #define PCLK_DSI_TX 251 174 #define PCLK_CSI_TX 252 175 #define PCLK_CSI2HOST 253 176 #define PCLK_PCIE 254 177 #define PCLK_GMAC 255 178 #define LSCLK_BUS_PRE 256 179 #define PCLK_DCF 257 180 #define PCLK_UART1 258 181 #define PCLK_UART2 259 182 #define PCLK_UART3 260 183 #define PCLK_UART4 261 184 #define PCLK_UART5 262 185 #define PCLK_UART6 263 186 #define PCLK_UART7 264 187 #define PCLK_I2C1 265 188 #define PCLK_I2C2 266 189 #define PCLK_I2C3 267 190 #define PCLK_I2C4 268 191 #define PCLK_I2C5 269 192 #define PCLK_SPI0 270 193 #define PCLK_SPI1 271 194 #define PCLK_SPI2 272 195 #define PCLK_TSADC 273 196 #define PCLK_SARADC 274 197 #define PCLK_EFUSE 275 198 #define PCLK_GPIO1 276 199 #define PCLK_GPIO2 277 200 #define PCLK_GPIO3 278 201 #define PCLK_GPIO4 279 202 #define PCLK_PWM0 280 203 #define PCLK_PWM1 281 204 #define PCLK_PWM2 282 205 #define PCLK_TIMER 283 206 #define PCLK_WDT 284 207 #define PCLK_MIPIDSIPHY 285 208 #define PCLK_MIPICSIPHY 286 209 #define PCLK_DDRMON 287 210 #define PCLK_DDRC 289 211 #define PCLK_MSCH 290 212 #define PCLK_STDBY 291 213 #define PCLK_GPIO0_PMU 292 214 #define PCLK_UART0_PMU 293 215 #define PCLK_I2C0_PMU 294 216 #define PCLK_USB3PHY_PIPE 295 217 #define PCLK_PMU_PRE 296 218 219 #define CLK_NR_CLKS (PCLK_PMU_PRE + 1) 220 221 /* soft-reset indices */ 222 223 /* cru_softrst_con0 */ 224 #define SRST_CORE0_PO 0 225 #define SRST_CORE1_PO 1 226 #define SRST_CORE0 2 227 #define SRST_CORE1 3 228 #define SRST_CORE0_DBG 4 229 #define SRST_CORE1_DBG 5 230 #define SRST_TOPDBG 6 231 #define SRST_CORE_NOC 7 232 #define SRST_STRC_A 8 233 #define SRST_L2C 9 234 #define SRST_DAP 10 235 #define SRST_CORE_MSNIU 11 236 #define SRST_GIC2CORE 12 237 #define SRST_CORE2GIC 13 238 #define SRST_CORE_PRF_A 14 239 #define SRST_CORE_GRF_P 15 240 241 /* cru_softrst_con1 */ 242 #define SRST_DDRPHY 16 243 #define SRST_DDRPHY_P 18 244 #define SRST_UPCTL2 20 245 #define SRST_UPCTL2_A 21 246 #define SRST_UPCTL2_P 22 247 #define SRST_MSCH 23 248 #define SRST_MSCH_P 24 249 #define SRST_DDRMON_P 25 250 #define SRST_DDRSTDBY_P 26 251 #define SRST_DDRSTDBY 27 252 #define SRST_DDRGRF_P 28 253 #define SRST_AXI_SPLIT_A 29 254 #define SRST_DDRDFI_CTL 30 255 #define SRST_DDRDFI_CTL_P 31 256 257 /* cru_softrst_con2 */ 258 #define SRST_GIC500_NIU_A 32 259 #define SRST_GIC500_A 33 260 #define SRST_GIC_CORE2GIC 34 261 #define SRST_GIC_GIC2CORE 35 262 #define SRST_NPU_CORE 36 263 #define SRST_NPU_A 37 264 #define SRST_NPU_H 38 265 #define SRST_NPU_NIU_A 39 266 #define SRST_NPU_NIU_H 40 267 #define SRST_NPU2MEM_A 41 268 #define SRST_NPU_PVTM 42 269 #define SRST_CORE_PVTM 43 270 #define SRST_GIC_SPINLOCK_A 47 271 272 /* cru_softrst_con3 */ 273 #define SRST_PCIE_NIU_H 48 274 #define SRST_PCIE_NIU_L 49 275 #define SRST_PCIEGRF_P 50 276 #define SRST_PCIECTL_P 51 277 #define SRST_PCIECTL_POWERUP 52 278 #define SRST_PCIECTL_MST_A 53 279 #define SRST_PCIECTL_SLV_A 54 280 #define SRST_PCIECTL_DBI_A 55 281 #define SRST_PCIECTL_BUTTON 56 282 #define SRST_PCIECTL_PE 57 283 #define SRST_PCIECTL_CORE 58 284 #define SRST_PCIECTL_NSTICKY 59 285 #define SRST_PCIECTL_STICKY 60 286 #define SRST_PCIECTL_PWR 61 287 #define SRST_PCIE_NIU_A 62 288 #define SRST_PCIE_NIU_P 63 289 290 /* cru_softrst_con4 */ 291 #define SRST_PCIEPHY_POR 64 292 #define SRST_PCIEPHY_P 65 293 #define SRST_PCIEPHY_PIPE 66 294 #define SRST_USBPHY_POR 67 295 #define SRST_USBPHY_OTG_PORT 68 296 #define SRST_USBPHY_HOST_PORT 69 297 #define SRST_USB3PHY_GRF_P 70 298 #define SRST_USB2PHY_GRF_P 71 299 #define SRST_USB3_OTG_A 72 300 #define SRST_USB2HOST_H 73 301 #define SRST_USB2HOST_ARB_H 74 302 #define SRSTUSB2HOST_UTMI 75 303 304 /* cru_softrst_con5 */ 305 #define SRST_IMEM0_A 80 306 #define SRST_IMEM1_A 81 307 #define SRST_IMEM2_A 82 308 #define SRST_IMEM3_A 83 309 #define SRST_IMEM0_NIU_A 84 310 #define SRST_IMEM1_NIU_A 85 311 #define SRST_IMEM2_NIU_A 86 312 #define SRST_IMEM3_NIU_A 87 313 #define SRST_IMEM_NIU_H 88 314 #define SRST_VPU_NIU_A 92 315 #define SRST_VPU_NIU_H 93 316 #define SRST_VPU_A 94 317 #define SRST_VPU_H 95 318 319 /* cru_softrst_con6 */ 320 #define SRST_VIO_NIU_H 96 321 #define SRST_VIO_NIU_L 97 322 #define SRST_VOPRAW_A 98 323 #define SRST_VOPRAW_H 99 324 #define SRST_VOPRAW_D 100 325 #define SRST_VOPLITE_A 101 326 #define SRST_VOPLITE_H 102 327 #define SRST_VOPLITE_D 103 328 #define SRST_MIPIDSI_HOST_P 104 329 #define SRST_CSITX_P 105 330 #define SRST_CSITX_TXBYTEHS 106 331 #define SRST_CSITX_TXESC 107 332 #define SRST_CSITX_CAM 108 333 #define SRST_CSITX_I 109 334 335 /* cru_softrst_con7 */ 336 #define SRST_RGA_A 112 337 #define SRST_RGA_H 113 338 #define SRST_RGA 114 339 #define SRST_CSI2HOST_P 115 340 #define SRST_CIF_A 116 341 #define SRST_CIF_H 117 342 #define SRST_CIF_I 118 343 #define SRST_CIF_PCLKIN 119 344 #define SRST_CIF_D 120 345 #define SRST_ISP_H 121 346 #define SRST_ISP 122 347 #define SRST_MIPICSIPHY_P 124 348 #define SRST_MIPIDSIPHY_P 125 349 350 /* cru_softrst_con8 */ 351 #define SRST_PERI_NIU_H 128 352 #define SRST_PERI_NIU_L 129 353 #define SRST_PDMMC_NIU_H 132 354 #define SRST_SDMMC_H 133 355 #define SRST_SDIO_H 134 356 #define SRST_EMMC_H 135 357 #define SRST_SFC_H 136 358 #define SRST_SFC 137 359 #define SRST_GMAC_NIU_A 140 360 #define SRST_GMAC_NIU_H 141 361 #define SRST_GMAC_NIU_P 142 362 #define SRST_GAMC_A 143 363 364 /* cru_softrst_con9 */ 365 #define SRST_PMU_NIU_P 144 366 #define SRST_PMU_SGRF_P 145 367 #define SRST_PMU_GRF_P 146 368 #define SRST_PMU_PMU 147 369 #define SRST_PMU_MEM_P 148 370 #define SRST_PMU_GPIO0_P 149 371 #define SRST_PMU_UART0_P 150 372 #define SRST_PMU_CRU 151 373 #define SRST_PMU_PVTM 152 374 #define SRST_PMU_UART0 153 375 #define SRST_PMU_NIU_H 154 376 #define SRST_PMU_DDR_FAIL_SAVE 155 377 #define SRST_PMU_I2C0_P 156 378 #define SRST_PMU_I2C0 157 379 #define SRST_PMU_GPIO0_DB 158 380 381 /* cru_softrst_con10 */ 382 #define SRST_AUDIO_NIU_H 160 383 #define SRST_VAD_H 161 384 #define SRST_PDM_H 162 385 #define SRST_PDM 163 386 #define SRST_I2S0_H 164 387 #define SRST_I2S0_TX 165 388 #define SRST_I2S1_H 166 389 #define SRST_I2S1 167 390 #define SRST_I2S0_RX 168 391 392 /* cru_softrst_con11 */ 393 #define SRST_BUS_NIU_M 176 394 #define SRST_BUS_NIU_L 177 395 #define SRST_TOP_NIU_P 178 396 #define SRST_ROM_H 179 397 #define SRST_CRYPTO_A 180 398 #define SRST_CRYPTO_H 181 399 #define SRST_CRYPTO_CORE 182 400 #define SRST_CRYPTO_APK 183 401 #define SRST_DCF_A 184 402 #define SRST_DCF_P 185 403 #define SRST_UART1_P 186 404 #define SRST_UART1 187 405 #define SRST_UART2_P 188 406 #define SRST_UART2 189 407 #define SRST_UART3_P 190 408 #define SRST_UART3 191 409 410 /* cru_softrst_con12 */ 411 #define SRST_UART4_P 192 412 #define SRST_UART4 193 413 #define SRST_UART5_P 194 414 #define SRST_UART5 195 415 #define SRST_UART6_P 196 416 #define SRST_UART6 197 417 #define SRST_UART7_P 198 418 #define SRST_UART7 199 419 #define SRST_I2C1_P 200 420 #define SRST_I2C1 201 421 #define SRST_I2C2_P 202 422 #define SRST_I2C2 203 423 #define SRST_I2C3_P 204 424 #define SRST_I2C3 205 425 #define SRST_PWM0_P 206 426 #define SRST_PWM0 207 427 428 /* cru_softrst_con13 */ 429 #define SRST_PWM1_P 208 430 #define SRST_PWM1 209 431 #define SRST_PWM2_P 210 432 #define SRST_PWM2 211 433 #define SRST_SPI0_P 212 434 #define SRST_SPI0 213 435 #define SRST_SPI1_P 214 436 #define SRST_SPI1 215 437 #define SRST_SPI2_P 216 438 #define SRST_SPI2 217 439 #define SRST_BUS_SGRF_P 218 440 #define SRST_BUS_GRF_P 219 441 #define SRST_TIMER_P 220 442 #define SRST_TIMER0 221 443 #define SRST_TIMER1 222 444 #define SRST_TIMER2 223 445 446 /* cru_softrst_con14 */ 447 #define SRST_TIMER3 224 448 #define SRST_TIMER4 225 449 #define SRST_TIMER5 226 450 #define SRST_WDT_NS_P 227 451 #define SRST_EFUSE_NS_P 228 452 #define SRST_EFUSE_NS 229 453 #define SRST_GPIO1_P 230 454 #define SRST_GPIO1_DB 231 455 #define SRST_GPIO2_P 232 456 #define SRST_GPIO2_DB 233 457 #define SRST_GPIO3_P 234 458 #define SRST_GPIO3_DB 235 459 #define SRST_GPIO4_P 236 460 #define SRST_GPIO4_DB 237 461 #define SRST_BUS_SUB_NIU_M 238 462 463 /* cru_softrst_con15 */ 464 #define SRST_I2C4_P 240 465 #define SRST_I2C4 241 466 #define SRST_I2C5_P 242 467 #define SRST_I2C5 243 468 #define SRST_SARADC 252 469 #define SRST_SARADC_P 253 470 #define SRST_TSADC_P 254 471 #define SRST_TSADC 255 472 473 #endif 474