1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/ { 8 chosen: chosen { 9 bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 hardware=dayu210 default_boot_device=fe2e0000.mmc rw rootwait ohos.required_mount.system=/dev/block/platform/fe2e0000.mmc/by-name/system@/usr@ext4@ro,barrier=1@wait,required ohos.required_mount.vendor=/dev/block/platform/fe2e0000.mmc/by-name/vendor@/vendor@ext4@ro,barrier=1@wait,required ohos.required_mount.misc=/dev/block/platform/fe2e0000.mmc/by-name/misc@none@none@none@wait,required ohos.required_mount.bootctrl=/dev/block/platform/fe2e0000.mmc/by-name/bootctrl@none@none@none@wait,required"; 10 }; 11 12 cspmu: cspmu@fd10c000 { 13 compatible = "rockchip,cspmu"; 14 reg = <0x0 0xfd10c000 0x0 0x1000>, 15 <0x0 0xfd10d000 0x0 0x1000>, 16 <0x0 0xfd10e000 0x0 0x1000>, 17 <0x0 0xfd10f000 0x0 0x1000>, 18 <0x0 0xfd12c000 0x0 0x1000>, 19 <0x0 0xfd12d000 0x0 0x1000>, 20 <0x0 0xfd12e000 0x0 0x1000>, 21 <0x0 0xfd12f000 0x0 0x1000>; 22 }; 23 24 debug: debug@fd104000 { 25 compatible = "rockchip,debug"; 26 reg = <0x0 0xfd104000 0x0 0x1000>, 27 <0x0 0xfd105000 0x0 0x1000>, 28 <0x0 0xfd106000 0x0 0x1000>, 29 <0x0 0xfd107000 0x0 0x1000>, 30 <0x0 0xfd124000 0x0 0x1000>, 31 <0x0 0xfd125000 0x0 0x1000>, 32 <0x0 0xfd126000 0x0 0x1000>, 33 <0x0 0xfd127000 0x0 0x1000>; 34 }; 35 36 fiq_debugger: fiq-debugger { 37 compatible = "rockchip,fiq-debugger"; 38 rockchip,serial-id = <2>; 39 rockchip,wake-irq = <0>; 40 /* If enable uart uses irq instead of fiq */ 41 rockchip,irq-mode-enable = <1>; 42 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 43 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_LOW>; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&uart2m0_xfer>; 46 status = "okay"; 47 }; 48 49 ramoops: ramoops@110000 { 50 compatible = "ramoops"; 51 reg = <0x0 0x110000 0x0 0xf0000>; 52 record-size = <0x20000>; 53 console-size = <0x80000>; 54 ftrace-size = <0x00000>; 55 pmsg-size = <0x50000>; 56 }; 57 58 reserved-memory { 59 #address-cells = <2>; 60 #size-cells = <2>; 61 ranges; 62 63 cma { 64 compatible = "shared-dma-pool"; 65 reusable; 66 size = <0x0 (8 * 0x100000)>; 67 linux,cma-default; 68 }; 69 70 drm_logo: drm-logo@00000000 { 71 compatible = "rockchip,drm-logo"; 72 reg = <0x0 0x0 0x0 0x0>; 73 }; 74 75 drm_cubic_lut: drm-cubic-lut@00000000 { 76 compatible = "rockchip,drm-cubic-lut"; 77 reg = <0x0 0x0 0x0 0x0>; 78 }; 79 }; 80}; 81 82&display_subsystem { 83 memory-region = <&drm_logo>; 84 memory-region-names = "drm-logo"; 85}; 86 87&rng { 88 status = "okay"; 89}; 90