1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Synopsys DesignWare Cores DisplayPort Transmitter Controller
4 *
5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
6 *
7 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
8 * Zhang Yubing <yubing.zhang@rock-chips.com>
9 */
10
11 #include <asm/unaligned.h>
12
13 #include <drm/drm_atomic_helper.h>
14 #include <drm/drm_bridge.h>
15 #include <drm/drm_dp_helper.h>
16 #include <drm/drm_of.h>
17 #include <drm/drm_print.h>
18 #include <drm/drm_probe_helper.h>
19 #include <drm/drm_simple_kms_helper.h>
20
21 #include <linux/bitfield.h>
22 #include <linux/clk.h>
23 #include <linux/component.h>
24 #include <linux/extcon-provider.h>
25 #include <linux/iopoll.h>
26 #include <linux/irq.h>
27 #include <linux/of_device.h>
28 #include <linux/of_graph.h>
29 #include <linux/regmap.h>
30 #include <linux/reset.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/phy/phy.h>
33 #include <linux/mfd/syscon.h>
34
35 #include <sound/hdmi-codec.h>
36
37 #include <uapi/linux/videodev2.h>
38
39 #include "rockchip_drm_drv.h"
40 #include "rockchip_drm_vop.h"
41
42 #define DPTX_VERSION_NUMBER 0x0000
43 #define DPTX_VERSION_TYPE 0x0004
44 #define DPTX_ID 0x0008
45
46 #define DPTX_CONFIG_REG1 0x0100
47 #define DPTX_CONFIG_REG2 0x0104
48 #define DPTX_CONFIG_REG3 0x0108
49
50 #define DPTX_CCTL 0x0200
51 #define FORCE_HPD BIT(4)
52 #define DEFAULT_FAST_LINK_TRAIN_EN BIT(2)
53 #define ENHANCE_FRAMING_EN BIT(1)
54 #define SCRAMBLE_DIS BIT(0)
55 #define DPTX_SOFT_RESET_CTRL 0x0204
56 #define VIDEO_RESET BIT(5)
57 #define AUX_RESET BIT(4)
58 #define AUDIO_SAMPLER_RESET BIT(3)
59 #define PHY_SOFT_RESET BIT(1)
60 #define CONTROLLER_RESET BIT(0)
61
62 #define DPTX_VSAMPLE_CTRL 0x0300
63 #define PIXEL_MODE_SELECT GENMASK(22, 21)
64 #define VIDEO_MAPPING GENMASK(20, 16)
65 #define VIDEO_STREAM_ENABLE BIT(5)
66 #define DPTX_VSAMPLE_STUFF_CTRL1 0x0304
67 #define DPTX_VSAMPLE_STUFF_CTRL2 0x0308
68 #define DPTX_VINPUT_POLARITY_CTRL 0x030c
69 #define DE_IN_POLARITY BIT(2)
70 #define HSYNC_IN_POLARITY BIT(1)
71 #define VSYNC_IN_POLARITY BIT(0)
72 #define DPTX_VIDEO_CONFIG1 0x0310
73 #define HACTIVE GENMASK(31, 16)
74 #define HBLANK GENMASK(15, 2)
75 #define I_P BIT(1)
76 #define R_V_BLANK_IN_OSC BIT(0)
77 #define DPTX_VIDEO_CONFIG2 0x0314
78 #define VBLANK GENMASK(31, 16)
79 #define VACTIVE GENMASK(15, 0)
80 #define DPTX_VIDEO_CONFIG3 0x0318
81 #define H_SYNC_WIDTH GENMASK(31, 16)
82 #define H_FRONT_PORCH GENMASK(15, 0)
83 #define DPTX_VIDEO_CONFIG4 0x031c
84 #define V_SYNC_WIDTH GENMASK(31, 16)
85 #define V_FRONT_PORCH GENMASK(15, 0)
86 #define DPTX_VIDEO_CONFIG5 0x0320
87 #define INIT_THRESHOLD_HI GENMASK(22, 21)
88 #define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16)
89 #define INIT_THRESHOLD GENMASK(13, 7)
90 #define AVERAGE_BYTES_PER_TU GENMASK(6, 0)
91 #define DPTX_VIDEO_MSA1 0x0324
92 #define VSTART GENMASK(31, 16)
93 #define HSTART GENMASK(15, 0)
94 #define DPTX_VIDEO_MSA2 0x0328
95 #define MISC0 GENMASK(31, 24)
96 #define DPTX_VIDEO_MSA3 0x032c
97 #define MISC1 GENMASK(31, 24)
98 #define DPTX_VIDEO_HBLANK_INTERVAL 0x0330
99 #define HBLANK_INTERVAL_EN BIT(16)
100 #define HBLANK_INTERVAL GENMASK(15, 0)
101
102 #define DPTX_AUD_CONFIG1 0x0400
103 #define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24)
104 #define AUDIO_PACKET_ID GENMASK(23, 16)
105 #define AUDIO_MUTE BIT(15)
106 #define NUM_CHANNELS GENMASK(14, 12)
107 #define HBR_MODE_ENABLE BIT(10)
108 #define AUDIO_DATA_WIDTH GENMASK(9, 5)
109 #define AUDIO_DATA_IN_EN GENMASK(4, 1)
110 #define AUDIO_INF_SELECT BIT(0)
111
112 #define DPTX_SDP_VERTICAL_CTRL 0x0500
113 #define EN_VERTICAL_SDP BIT(2)
114 #define EN_AUDIO_STREAM_SDP BIT(1)
115 #define EN_AUDIO_TIMESTAMP_SDP BIT(0)
116 #define DPTX_SDP_HORIZONTAL_CTRL 0x0504
117 #define EN_HORIZONTAL_SDP BIT(2)
118 #define DPTX_SDP_STATUS_REGISTER 0x0508
119 #define DPTX_SDP_MANUAL_CTRL 0x050c
120 #define DPTX_SDP_STATUS_EN 0x0510
121
122 #define DPTX_SDP_REGISTER_BANK 0x0600
123 #define SDP_REGS GENMASK(31, 0)
124
125 #define DPTX_PHYIF_CTRL 0x0a00
126 #define PHY_WIDTH BIT(25)
127 #define PHY_POWERDOWN GENMASK(20, 17)
128 #define PHY_BUSY GENMASK(15, 12)
129 #define SSC_DIS BIT(16)
130 #define XMIT_ENABLE GENMASK(11, 8)
131 #define PHY_LANES GENMASK(7, 6)
132 #define PHY_RATE GENMASK(5, 4)
133 #define TPS_SEL GENMASK(3, 0)
134 #define DPTX_PHY_TX_EQ 0x0a04
135 #define DPTX_CUSTOMPAT0 0x0a08
136 #define DPTX_CUSTOMPAT1 0x0a0c
137 #define DPTX_CUSTOMPAT2 0x0a10
138 #define DPTX_HBR2_COMPLIANCE_SCRAMBLER_RESET 0x0a14
139 #define DPTX_PHYIF_PWRDOWN_CTRL 0x0a18
140
141 #define DPTX_AUX_CMD 0x0b00
142 #define AUX_CMD_TYPE GENMASK(31, 28)
143 #define AUX_ADDR GENMASK(27, 8)
144 #define I2C_ADDR_ONLY BIT(4)
145 #define AUX_LEN_REQ GENMASK(3, 0)
146 #define DPTX_AUX_STATUS 0x0b04
147 #define AUX_TIMEOUT BIT(17)
148 #define AUX_BYTES_READ GENMASK(23, 19)
149 #define AUX_STATUS GENMASK(7, 4)
150 #define DPTX_AUX_DATA0 0x0b08
151 #define DPTX_AUX_DATA1 0x0b0c
152 #define DPTX_AUX_DATA2 0x0b10
153 #define DPTX_AUX_DATA3 0x0b14
154
155 #define DPTX_GENERAL_INTERRUPT 0x0d00
156 #define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6)
157 #define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5)
158 #define SDP_EVENT_STREAM0 BIT(4)
159 #define AUX_CMD_INVALID BIT(3)
160 #define AUX_REPLY_EVENT BIT(1)
161 #define HPD_EVENT BIT(0)
162 #define DPTX_GENERAL_INTERRUPT_ENABLE 0x0d04
163 #define AUX_REPLY_EVENT_EN BIT(1)
164 #define HPD_EVENT_EN BIT(0)
165 #define DPTX_HPD_STATUS 0x0d08
166 #define HPD_STATE GENMASK(11, 9)
167 #define HPD_STATUS BIT(8)
168 #define HPD_HOT_UNPLUG BIT(2)
169 #define HPD_HOT_PLUG BIT(1)
170 #define HPD_IRQ BIT(0)
171 #define DPTX_HPD_INTERRUPT_ENABLE 0x0d0c
172 #define HPD_UNPLUG_ERR_EN BIT(3)
173 #define HPD_UNPLUG_EN BIT(2)
174 #define HPD_PLUG_EN BIT(1)
175 #define HPD_IRQ_EN BIT(0)
176
177 #define DPTX_MAX_REGISTER DPTX_HPD_INTERRUPT_ENABLE
178
179 #define SDP_REG_BANK_SIZE 16
180
181 struct drm_dp_link_caps {
182 bool enhanced_framing;
183 bool tps3_supported;
184 bool tps4_supported;
185 bool fast_training;
186 bool channel_coding;
187 bool ssc;
188 };
189
190 struct drm_dp_link_train_set {
191 unsigned int voltage_swing[4];
192 unsigned int pre_emphasis[4];
193 };
194
195 struct drm_dp_link_train {
196 struct drm_dp_link_train_set request;
197 struct drm_dp_link_train_set adjust;
198 bool clock_recovered;
199 bool channel_equalized;
200 };
201
202 struct dw_dp_link {
203 u8 dpcd[DP_RECEIVER_CAP_SIZE];
204 unsigned char revision;
205 unsigned int rate;
206 unsigned int lanes;
207 struct drm_dp_link_caps caps;
208 struct drm_dp_link_train train;
209 struct drm_dp_desc desc;
210 u8 sink_count;
211 u8 vsc_sdp_extension_for_colorimetry_supported;
212 };
213
214 struct dw_dp_video {
215 struct drm_display_mode mode;
216 u32 bus_format;
217 u8 video_mapping;
218 u8 pixel_mode;
219 u8 color_format;
220 u8 bpc;
221 u8 bpp;
222 };
223
224 struct dw_dp_audio {
225 struct platform_device *pdev;
226 u8 channels;
227 };
228
229 struct dw_dp_sdp {
230 struct dp_sdp_header header;
231 u8 db[32];
232 unsigned long flags;
233 };
234
235 struct dw_dp_hotplug {
236 bool long_hpd;
237 bool status;
238 };
239
240 struct dw_dp {
241 struct device *dev;
242 struct regmap *regmap;
243 struct phy *phy;
244 struct clk_bulk_data *clks;
245 int nr_clks;
246 struct reset_control *rstc;
247 struct regmap *grf;
248 struct completion complete;
249 int irq;
250 int id;
251 struct work_struct hpd_work;
252 struct gpio_desc *hpd_gpio;
253 struct dw_dp_hotplug hotplug;
254 struct mutex irq_lock;
255 struct extcon_dev *extcon;
256
257 struct drm_bridge bridge;
258 struct drm_connector connector;
259 struct drm_encoder encoder;
260 struct drm_dp_aux aux;
261
262 struct dw_dp_link link;
263 struct dw_dp_video video;
264 struct dw_dp_audio audio;
265
266 DECLARE_BITMAP(sdp_reg_bank, SDP_REG_BANK_SIZE);
267
268 bool split_mode;
269 struct dw_dp *left;
270 struct dw_dp *right;
271 };
272
273 enum {
274 DPTX_VM_RGB_6BIT,
275 DPTX_VM_RGB_8BIT,
276 DPTX_VM_RGB_10BIT,
277 DPTX_VM_RGB_12BIT,
278 DPTX_VM_RGB_16BIT,
279 DPTX_VM_YCBCR444_8BIT,
280 DPTX_VM_YCBCR444_10BIT,
281 DPTX_VM_YCBCR444_12BIT,
282 DPTX_VM_YCBCR444_16BIT,
283 DPTX_VM_YCBCR422_8BIT,
284 DPTX_VM_YCBCR422_10BIT,
285 DPTX_VM_YCBCR422_12BIT,
286 DPTX_VM_YCBCR422_16BIT,
287 DPTX_VM_YCBCR420_8BIT,
288 DPTX_VM_YCBCR420_10BIT,
289 DPTX_VM_YCBCR420_12BIT,
290 DPTX_VM_YCBCR420_16BIT,
291 };
292
293 enum {
294 DPTX_MP_SINGLE_PIXEL,
295 DPTX_MP_DUAL_PIXEL,
296 DPTX_MP_QUAD_PIXEL,
297 };
298
299 enum {
300 DPTX_SDP_VERTICAL_INTERVAL = BIT(0),
301 DPTX_SDP_HORIZONTAL_INTERVAL = BIT(1),
302 };
303
304 enum {
305 SOURCE_STATE_IDLE,
306 SOURCE_STATE_UNPLUG,
307 SOURCE_STATE_HPD_TIMEOUT = 4,
308 SOURCE_STATE_PLUG = 7
309 };
310
311 enum {
312 DPTX_PHY_PATTERN_NONE,
313 DPTX_PHY_PATTERN_TPS_1,
314 DPTX_PHY_PATTERN_TPS_2,
315 DPTX_PHY_PATTERN_TPS_3,
316 DPTX_PHY_PATTERN_TPS_4,
317 DPTX_PHY_PATTERN_SERM,
318 DPTX_PHY_PATTERN_PBRS7,
319 DPTX_PHY_PATTERN_CUSTOM_80BIT,
320 DPTX_PHY_PATTERN_CP2520_1,
321 DPTX_PHY_PATTERN_CP2520_2,
322 };
323
324 static const unsigned int dw_dp_cable[] = {
325 EXTCON_DISP_DP,
326 EXTCON_NONE,
327 };
328
329 struct dw_dp_output_format {
330 u32 bus_format;
331 u32 color_format;
332 u8 video_mapping;
333 u8 bpc;
334 u8 bpp;
335 };
336
337 static const struct dw_dp_output_format possible_output_fmts[] = {
338 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444,
339 DPTX_VM_RGB_10BIT, 10, 30 },
340 { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444,
341 DPTX_VM_RGB_8BIT, 8, 24 },
342 { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444,
343 DPTX_VM_YCBCR444_10BIT, 10, 30 },
344 { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444,
345 DPTX_VM_YCBCR444_8BIT, 8, 24},
346 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422,
347 DPTX_VM_YCBCR422_10BIT, 10, 20 },
348 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422,
349 DPTX_VM_YCBCR422_8BIT, 8, 16 },
350 { MEDIA_BUS_FMT_UYYVYY10_0_5X30, DRM_COLOR_FORMAT_YCRCB420,
351 DPTX_VM_YCBCR420_10BIT, 10, 15 },
352 { MEDIA_BUS_FMT_UYYVYY8_0_5X24, DRM_COLOR_FORMAT_YCRCB420,
353 DPTX_VM_YCBCR420_8BIT, 8, 12 },
354 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444,
355 DPTX_VM_RGB_6BIT, 6, 18 },
356 };
357
dw_dp_get_output_format(u32 bus_format)358 static const struct dw_dp_output_format *dw_dp_get_output_format(u32 bus_format)
359 {
360 unsigned int i;
361
362 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++)
363 if (possible_output_fmts[i].bus_format == bus_format)
364 return &possible_output_fmts[i];
365
366 return &possible_output_fmts[1];
367 }
368
connector_to_dp(struct drm_connector * c)369 static inline struct dw_dp *connector_to_dp(struct drm_connector *c)
370 {
371 return container_of(c, struct dw_dp, connector);
372 }
373
encoder_to_dp(struct drm_encoder * e)374 static inline struct dw_dp *encoder_to_dp(struct drm_encoder *e)
375 {
376 return container_of(e, struct dw_dp, encoder);
377 }
378
bridge_to_dp(struct drm_bridge * b)379 static inline struct dw_dp *bridge_to_dp(struct drm_bridge *b)
380 {
381 return container_of(b, struct dw_dp, bridge);
382 }
383
dw_dp_match_by_id(struct device * dev,const void * data)384 static int dw_dp_match_by_id(struct device *dev, const void *data)
385 {
386 struct dw_dp *dp = dev_get_drvdata(dev);
387 const unsigned int *id = data;
388
389 return dp->id == *id;
390 }
391
dw_dp_find_by_id(struct device_driver * drv,unsigned int id)392 static struct dw_dp *dw_dp_find_by_id(struct device_driver *drv,
393 unsigned int id)
394 {
395 struct device *dev;
396
397 dev = driver_find_device(drv, NULL, &id, dw_dp_match_by_id);
398 if (!dev)
399 return NULL;
400
401 return dev_get_drvdata(dev);
402 }
403
dw_dp_phy_set_pattern(struct dw_dp * dp,u32 pattern)404 static void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern)
405 {
406 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, TPS_SEL,
407 FIELD_PREP(TPS_SEL, pattern));
408 }
409
dw_dp_phy_xmit_enable(struct dw_dp * dp,u32 lanes)410 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes)
411 {
412 u32 xmit_enable;
413
414 switch (lanes) {
415 case 4:
416 case 2:
417 case 1:
418 xmit_enable = GENMASK(lanes - 1, 0);
419 break;
420 case 0:
421 default:
422 xmit_enable = 0;
423 break;
424 }
425
426 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, XMIT_ENABLE,
427 FIELD_PREP(XMIT_ENABLE, xmit_enable));
428 }
429
dw_dp_bandwidth_ok(struct dw_dp * dp,const struct drm_display_mode * mode,u32 bpp,unsigned int lanes,unsigned int rate)430 static bool dw_dp_bandwidth_ok(struct dw_dp *dp,
431 const struct drm_display_mode *mode, u32 bpp,
432 unsigned int lanes, unsigned int rate)
433 {
434 u32 max_bw, req_bw;
435
436 req_bw = mode->clock * bpp / 8;
437 max_bw = lanes * rate;
438 if (req_bw > max_bw)
439 return false;
440
441 return true;
442 }
443
dw_dp_detect(struct dw_dp * dp)444 static bool dw_dp_detect(struct dw_dp *dp)
445 {
446 u32 value;
447
448 if (dp->hpd_gpio)
449 return gpiod_get_value_cansleep(dp->hpd_gpio);
450
451 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value);
452
453 return FIELD_GET(HPD_STATE, value) == SOURCE_STATE_PLUG;
454 }
455
456 static enum drm_connector_status
dw_dp_connector_detect(struct drm_connector * connector,bool force)457 dw_dp_connector_detect(struct drm_connector *connector, bool force)
458 {
459 struct dw_dp *dp = connector_to_dp(connector);
460
461 if (dp->right && drm_bridge_detect(&dp->right->bridge) != connector_status_connected)
462 return connector_status_disconnected;
463
464 return drm_bridge_detect(&dp->bridge);
465 }
466
dw_dp_connector_force(struct drm_connector * connector)467 static void dw_dp_connector_force(struct drm_connector *connector)
468 {
469 struct dw_dp *dp = connector_to_dp(connector);
470
471 if (connector->status == connector_status_connected)
472 extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, true);
473 else
474 extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, false);
475 }
476
477 static const struct drm_connector_funcs dw_dp_connector_funcs = {
478 .detect = dw_dp_connector_detect,
479 .fill_modes = drm_helper_probe_single_connector_modes,
480 .destroy = drm_connector_cleanup,
481 .force = dw_dp_connector_force,
482 .reset = drm_atomic_helper_connector_reset,
483 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
484 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
485 };
486
dw_dp_connector_get_modes(struct drm_connector * connector)487 static int dw_dp_connector_get_modes(struct drm_connector *connector)
488 {
489 struct dw_dp *dp = connector_to_dp(connector);
490 struct drm_display_info *di = &connector->display_info;
491 struct edid *edid;
492 int num_modes = 0;
493
494 edid = drm_bridge_get_edid(&dp->bridge, connector);
495 if (edid) {
496 drm_connector_update_edid_property(connector, edid);
497 num_modes = drm_add_edid_modes(connector, edid);
498 kfree(edid);
499 }
500
501 if (!di->color_formats)
502 di->color_formats = DRM_COLOR_FORMAT_RGB444;
503
504 if (!di->bpc)
505 di->bpc = 8;
506
507 if (num_modes > 0 && dp->split_mode) {
508 struct drm_display_mode *mode;
509
510 di->width_mm *= 2;
511
512 list_for_each_entry(mode, &connector->probed_modes, head)
513 drm_mode_convert_to_split_mode(mode);
514 }
515
516 return num_modes;
517 }
518
519 static const struct drm_connector_helper_funcs dw_dp_connector_helper_funcs = {
520 .get_modes = dw_dp_connector_get_modes,
521 };
522
dw_dp_link_caps_reset(struct drm_dp_link_caps * caps)523 static void dw_dp_link_caps_reset(struct drm_dp_link_caps *caps)
524 {
525 caps->enhanced_framing = false;
526 caps->tps3_supported = false;
527 caps->tps4_supported = false;
528 caps->fast_training = false;
529 caps->channel_coding = false;
530 }
531
dw_dp_link_reset(struct dw_dp_link * link)532 static void dw_dp_link_reset(struct dw_dp_link *link)
533 {
534 link->vsc_sdp_extension_for_colorimetry_supported = 0;
535 link->sink_count = 0;
536 link->revision = 0;
537
538 dw_dp_link_caps_reset(&link->caps);
539 memset(link->dpcd, 0, sizeof(link->dpcd));
540
541 link->rate = 0;
542 link->lanes = 0;
543 }
544
dw_dp_link_power_up(struct dw_dp * dp)545 static int dw_dp_link_power_up(struct dw_dp *dp)
546 {
547 struct dw_dp_link *link = &dp->link;
548 u8 value;
549 int ret;
550
551 if (link->revision < 0x11)
552 return 0;
553
554 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value);
555 if (ret < 0)
556 return ret;
557
558 value &= ~DP_SET_POWER_MASK;
559 value |= DP_SET_POWER_D0;
560
561 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value);
562 if (ret < 0)
563 return ret;
564
565 usleep_range(1000, 2000);
566
567 return 0;
568 }
569
dw_dp_link_power_down(struct dw_dp * dp)570 static int dw_dp_link_power_down(struct dw_dp *dp)
571 {
572 struct dw_dp_link *link = &dp->link;
573 u8 value;
574 int ret;
575
576 if (link->revision < 0x11)
577 return 0;
578
579 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value);
580 if (ret < 0)
581 return ret;
582
583 value &= ~DP_SET_POWER_MASK;
584 value |= DP_SET_POWER_D3;
585
586 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value);
587 if (ret < 0)
588 return ret;
589
590 return 0;
591 }
592
dw_dp_has_sink_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const struct drm_dp_desc * desc)593 static bool dw_dp_has_sink_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
594 const struct drm_dp_desc *desc)
595 {
596 return dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
597 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
598 !drm_dp_has_quirk(desc, 0, DP_DPCD_QUIRK_NO_SINK_COUNT);
599 }
600
dw_dp_link_probe(struct dw_dp * dp)601 static int dw_dp_link_probe(struct dw_dp *dp)
602 {
603 struct dw_dp_link *link = &dp->link;
604 u8 dpcd;
605 int ret;
606
607 dw_dp_link_reset(link);
608
609 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd);
610 if (ret < 0)
611 return ret;
612
613 drm_dp_read_desc(&dp->aux, &link->desc, drm_dp_is_branch(link->dpcd));
614
615 if (dw_dp_has_sink_count(link->dpcd, &link->desc)) {
616 ret = drm_dp_read_sink_count(&dp->aux);
617 if (ret < 0)
618 return ret;
619
620 link->sink_count = ret;
621
622 /* Dongle connected, but no display */
623 if (!link->sink_count)
624 return -ENODEV;
625 }
626
627 ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
628 &dpcd);
629 if (ret < 0)
630 return ret;
631
632 link->vsc_sdp_extension_for_colorimetry_supported =
633 !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED);
634
635 link->revision = link->dpcd[DP_DPCD_REV];
636 link->rate = drm_dp_max_link_rate(link->dpcd);
637 link->lanes = min_t(u8, phy_get_bus_width(dp->phy),
638 drm_dp_max_lane_count(link->dpcd));
639
640 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd);
641 link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd);
642 link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd);
643 link->caps.fast_training = drm_dp_fast_training_cap(link->dpcd);
644 link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd);
645 link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
646
647 return 0;
648 }
649
dw_dp_link_train_update_vs_emph(struct dw_dp * dp)650 static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp)
651 {
652 struct dw_dp_link *link = &dp->link;
653 struct drm_dp_link_train_set *request = &link->train.request;
654 union phy_configure_opts phy_cfg;
655 unsigned int lanes = link->lanes, *vs, *pe;
656 u8 buf[4];
657 int i, ret;
658
659 vs = request->voltage_swing;
660 pe = request->pre_emphasis;
661
662 for (i = 0; i < lanes; i++) {
663 phy_cfg.dp.voltage[i] = vs[i];
664 phy_cfg.dp.pre[i] = pe[i];
665 }
666 phy_cfg.dp.lanes = lanes;
667 phy_cfg.dp.link_rate = link->rate / 100;
668 phy_cfg.dp.set_lanes = false;
669 phy_cfg.dp.set_rate = false;
670 phy_cfg.dp.set_voltages = true;
671 ret = phy_configure(dp->phy, &phy_cfg);
672 if (ret)
673 return ret;
674
675 for (i = 0; i < lanes; i++)
676 buf[i] = (vs[i] << DP_TRAIN_VOLTAGE_SWING_SHIFT) |
677 (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT);
678 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes);
679 if (ret < 0)
680 return ret;
681
682 return 0;
683 }
684
dw_dp_link_configure(struct dw_dp * dp)685 static int dw_dp_link_configure(struct dw_dp *dp)
686 {
687 struct dw_dp_link *link = &dp->link;
688 union phy_configure_opts phy_cfg;
689 u8 buf[2];
690 int ret;
691
692 /* Move PHY to P3 */
693 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN,
694 FIELD_PREP(PHY_POWERDOWN, 0x3));
695
696 phy_cfg.dp.lanes = link->lanes;
697 phy_cfg.dp.link_rate = link->rate / 100;
698 phy_cfg.dp.ssc = link->caps.ssc;
699 phy_cfg.dp.set_lanes = true;
700 phy_cfg.dp.set_rate = true;
701 phy_cfg.dp.set_voltages = false;
702 ret = phy_configure(dp->phy, &phy_cfg);
703 if (ret)
704 return ret;
705
706 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES,
707 FIELD_PREP(PHY_LANES, link->lanes / 2));
708
709 /* Move PHY to P0 */
710 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN,
711 FIELD_PREP(PHY_POWERDOWN, 0x0));
712
713 dw_dp_phy_xmit_enable(dp, link->lanes);
714
715 buf[0] = drm_dp_link_rate_to_bw_code(link->rate);
716 buf[1] = link->lanes;
717
718 if (link->caps.enhanced_framing) {
719 buf[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
720 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN,
721 FIELD_PREP(ENHANCE_FRAMING_EN, 1));
722 } else {
723 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN,
724 FIELD_PREP(ENHANCE_FRAMING_EN, 0));
725 }
726
727 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf));
728 if (ret < 0)
729 return ret;
730
731 buf[0] = link->caps.ssc ? DP_SPREAD_AMP_0_5 : 0;
732 buf[1] = link->caps.channel_coding ? DP_SET_ANSI_8B10B : 0;
733
734 ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf,
735 sizeof(buf));
736 if (ret < 0)
737 return ret;
738
739 return 0;
740 }
741
dw_dp_link_train_init(struct drm_dp_link_train * train)742 static void dw_dp_link_train_init(struct drm_dp_link_train *train)
743 {
744 struct drm_dp_link_train_set *request = &train->request;
745 struct drm_dp_link_train_set *adjust = &train->adjust;
746 unsigned int i;
747
748 for (i = 0; i < 4; i++) {
749 request->voltage_swing[i] = 0;
750 adjust->voltage_swing[i] = 0;
751
752 request->pre_emphasis[i] = 0;
753 adjust->pre_emphasis[i] = 0;
754 }
755
756 train->clock_recovered = false;
757 train->channel_equalized = false;
758 }
759
dw_dp_link_train_valid(const struct drm_dp_link_train * train)760 static bool dw_dp_link_train_valid(const struct drm_dp_link_train *train)
761 {
762 return train->clock_recovered && train->channel_equalized;
763 }
764
dw_dp_link_train_set_pattern(struct dw_dp * dp,u32 pattern)765 static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern)
766 {
767 u8 buf = 0;
768 int ret;
769
770 if (pattern && pattern != DP_TRAINING_PATTERN_4) {
771 buf |= DP_LINK_SCRAMBLING_DISABLE;
772
773 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS,
774 FIELD_PREP(SCRAMBLE_DIS, 1));
775 } else {
776 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS,
777 FIELD_PREP(SCRAMBLE_DIS, 0));
778 }
779
780 switch (pattern) {
781 case DP_TRAINING_PATTERN_DISABLE:
782 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE);
783 break;
784 case DP_TRAINING_PATTERN_1:
785 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_1);
786 break;
787 case DP_TRAINING_PATTERN_2:
788 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_2);
789 break;
790 case DP_TRAINING_PATTERN_3:
791 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_3);
792 break;
793 case DP_TRAINING_PATTERN_4:
794 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_4);
795 break;
796 default:
797 return -EINVAL;
798 }
799
800 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
801 buf | pattern);
802 if (ret < 0)
803 return ret;
804
805 return 0;
806 }
807
dw_dp_link_get_adjustments(struct dw_dp_link * link,u8 status[DP_LINK_STATUS_SIZE])808 static void dw_dp_link_get_adjustments(struct dw_dp_link *link,
809 u8 status[DP_LINK_STATUS_SIZE])
810 {
811 struct drm_dp_link_train_set *adjust = &link->train.adjust;
812 unsigned int i;
813
814 for (i = 0; i < link->lanes; i++) {
815 adjust->voltage_swing[i] =
816 drm_dp_get_adjust_request_voltage(status, i) >>
817 DP_TRAIN_VOLTAGE_SWING_SHIFT;
818
819 adjust->pre_emphasis[i] =
820 drm_dp_get_adjust_request_pre_emphasis(status, i) >>
821 DP_TRAIN_PRE_EMPHASIS_SHIFT;
822 }
823 }
824
dw_dp_link_train_adjust(struct drm_dp_link_train * train)825 static void dw_dp_link_train_adjust(struct drm_dp_link_train *train)
826 {
827 struct drm_dp_link_train_set *request = &train->request;
828 struct drm_dp_link_train_set *adjust = &train->adjust;
829 unsigned int i;
830
831 for (i = 0; i < 4; i++)
832 if (request->voltage_swing[i] != adjust->voltage_swing[i])
833 request->voltage_swing[i] = adjust->voltage_swing[i];
834
835 for (i = 0; i < 4; i++)
836 if (request->pre_emphasis[i] != adjust->pre_emphasis[i])
837 request->pre_emphasis[i] = adjust->pre_emphasis[i];
838 }
839
dw_dp_link_clock_recovery(struct dw_dp * dp)840 static int dw_dp_link_clock_recovery(struct dw_dp *dp)
841 {
842 struct dw_dp_link *link = &dp->link;
843 u8 status[DP_LINK_STATUS_SIZE];
844 unsigned int tries = 0;
845 int ret;
846
847 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1);
848 if (ret)
849 return ret;
850
851 for (;;) {
852 ret = dw_dp_link_train_update_vs_emph(dp);
853 if (ret)
854 return ret;
855
856 drm_dp_link_train_clock_recovery_delay(link->dpcd);
857
858 ret = drm_dp_dpcd_read_link_status(&dp->aux, status);
859 if (ret < 0) {
860 dev_err(dp->dev, "failed to read link status: %d\n", ret);
861 return ret;
862 }
863
864 if (drm_dp_clock_recovery_ok(status, link->lanes)) {
865 link->train.clock_recovered = true;
866 break;
867 }
868
869 dw_dp_link_get_adjustments(link, status);
870
871 if (link->train.request.voltage_swing[0] ==
872 link->train.adjust.voltage_swing[0])
873 tries++;
874 else
875 tries = 0;
876
877 if (tries == 5)
878 break;
879
880 dw_dp_link_train_adjust(&link->train);
881 }
882
883 return 0;
884 }
885
dw_dp_link_channel_equalization(struct dw_dp * dp)886 static int dw_dp_link_channel_equalization(struct dw_dp *dp)
887 {
888 struct dw_dp_link *link = &dp->link;
889 u8 status[DP_LINK_STATUS_SIZE], pattern;
890 unsigned int tries;
891 int ret;
892
893 if (link->caps.tps4_supported)
894 pattern = DP_TRAINING_PATTERN_4;
895 else if (link->caps.tps3_supported)
896 pattern = DP_TRAINING_PATTERN_3;
897 else
898 pattern = DP_TRAINING_PATTERN_2;
899 ret = dw_dp_link_train_set_pattern(dp, pattern);
900 if (ret)
901 return ret;
902
903 for (tries = 1; tries < 5; tries++) {
904 ret = dw_dp_link_train_update_vs_emph(dp);
905 if (ret)
906 return ret;
907
908 drm_dp_link_train_channel_eq_delay(link->dpcd);
909
910 ret = drm_dp_dpcd_read_link_status(&dp->aux, status);
911 if (ret < 0)
912 return ret;
913
914 if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
915 dev_err(dp->dev, "clock recovery lost while equalizing channel\n");
916 link->train.clock_recovered = false;
917 break;
918 }
919
920 if (drm_dp_channel_eq_ok(status, link->lanes)) {
921 link->train.channel_equalized = true;
922 break;
923 }
924
925 dw_dp_link_get_adjustments(link, status);
926 dw_dp_link_train_adjust(&link->train);
927 }
928
929 return 0;
930 }
931
dw_dp_link_downgrade(struct dw_dp * dp)932 static int dw_dp_link_downgrade(struct dw_dp *dp)
933 {
934 struct dw_dp_link *link = &dp->link;
935 struct dw_dp_video *video = &dp->video;
936
937 switch (link->rate) {
938 case 162000:
939 return -EINVAL;
940 case 270000:
941 link->rate = 162000;
942 break;
943 case 540000:
944 link->rate = 270000;
945 break;
946 case 810000:
947 link->rate = 540000;
948 break;
949 }
950
951 if (!dw_dp_bandwidth_ok(dp, &video->mode, video->bpp, link->lanes,
952 link->rate))
953 return -E2BIG;
954
955 return 0;
956 }
957
dw_dp_link_train_full(struct dw_dp * dp)958 static int dw_dp_link_train_full(struct dw_dp *dp)
959 {
960 struct dw_dp_link *link = &dp->link;
961 int ret;
962
963 retry:
964 dw_dp_link_train_init(&link->train);
965
966 dev_info(dp->dev, "full-training link: %u lane%s at %u MHz\n",
967 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100);
968
969 ret = dw_dp_link_configure(dp);
970 if (ret < 0) {
971 dev_err(dp->dev, "failed to configure DP link: %d\n", ret);
972 return ret;
973 }
974
975 ret = dw_dp_link_clock_recovery(dp);
976 if (ret < 0) {
977 dev_err(dp->dev, "clock recovery failed: %d\n", ret);
978 goto out;
979 }
980
981 if (!link->train.clock_recovered) {
982 dev_err(dp->dev, "clock recovery failed, downgrading link\n");
983
984 ret = dw_dp_link_downgrade(dp);
985 if (ret < 0)
986 goto out;
987 else
988 goto retry;
989 }
990
991 dev_info(dp->dev, "clock recovery succeeded\n");
992
993 ret = dw_dp_link_channel_equalization(dp);
994 if (ret < 0) {
995 dev_err(dp->dev, "channel equalization failed: %d\n", ret);
996 goto out;
997 }
998
999 if (!link->train.channel_equalized) {
1000 dev_err(dp->dev, "channel equalization failed, downgrading link\n");
1001
1002 ret = dw_dp_link_downgrade(dp);
1003 if (ret < 0)
1004 goto out;
1005 else
1006 goto retry;
1007 }
1008
1009 dev_info(dp->dev, "channel equalization succeeded\n");
1010
1011 out:
1012 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE);
1013 return ret;
1014 }
1015
dw_dp_link_train_fast(struct dw_dp * dp)1016 static int dw_dp_link_train_fast(struct dw_dp *dp)
1017 {
1018 struct dw_dp_link *link = &dp->link;
1019 u8 status[DP_LINK_STATUS_SIZE], pattern;
1020 int ret;
1021
1022 dw_dp_link_train_init(&link->train);
1023
1024 dev_info(dp->dev, "fast-training link: %u lane%s at %u MHz\n",
1025 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100);
1026
1027 ret = dw_dp_link_configure(dp);
1028 if (ret < 0) {
1029 dev_err(dp->dev, "failed to configure DP link: %d\n", ret);
1030 return ret;
1031 }
1032
1033 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1);
1034 if (ret)
1035 goto out;
1036
1037 usleep_range(500, 1000);
1038
1039 if (link->caps.tps4_supported)
1040 pattern = DP_TRAINING_PATTERN_4;
1041 else if (link->caps.tps3_supported)
1042 pattern = DP_TRAINING_PATTERN_3;
1043 else
1044 pattern = DP_TRAINING_PATTERN_2;
1045 ret = dw_dp_link_train_set_pattern(dp, pattern);
1046 if (ret)
1047 goto out;
1048
1049 usleep_range(500, 1000);
1050
1051 ret = drm_dp_dpcd_read_link_status(&dp->aux, status);
1052 if (ret < 0) {
1053 dev_err(dp->dev, "failed to read link status: %d\n", ret);
1054 goto out;
1055 }
1056
1057 if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
1058 dev_err(dp->dev, "clock recovery failed\n");
1059 ret = -EIO;
1060 goto out;
1061 }
1062
1063 if (!drm_dp_channel_eq_ok(status, link->lanes)) {
1064 dev_err(dp->dev, "channel equalization failed\n");
1065 ret = -EIO;
1066 goto out;
1067 }
1068
1069 out:
1070 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE);
1071 return ret;
1072 }
1073
dw_dp_link_train(struct dw_dp * dp)1074 static int dw_dp_link_train(struct dw_dp *dp)
1075 {
1076 struct dw_dp_link *link = &dp->link;
1077 int ret;
1078
1079 if (link->caps.fast_training) {
1080 if (dw_dp_link_train_valid(&link->train)) {
1081 ret = dw_dp_link_train_fast(dp);
1082 if (ret < 0)
1083 dev_err(dp->dev,
1084 "fast link training failed: %d\n", ret);
1085 else
1086 return 0;
1087 }
1088 }
1089
1090 ret = dw_dp_link_train_full(dp);
1091 if (ret < 0) {
1092 dev_err(dp->dev, "full link training failed: %d\n", ret);
1093 return ret;
1094 }
1095
1096 return 0;
1097 }
1098
dw_dp_send_sdp(struct dw_dp * dp,struct dw_dp_sdp * sdp)1099 static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp)
1100 {
1101 const u8 *payload = sdp->db;
1102 u32 reg;
1103 int i, nr;
1104
1105 nr = find_first_zero_bit(dp->sdp_reg_bank, SDP_REG_BANK_SIZE);
1106 if (nr < SDP_REG_BANK_SIZE)
1107 set_bit(nr, dp->sdp_reg_bank);
1108 else
1109 return -EBUSY;
1110
1111 reg = DPTX_SDP_REGISTER_BANK + nr * 9 * 4;
1112
1113 /* SDP header */
1114 regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->header));
1115
1116 /* SDP data payload */
1117 for (i = 1; i < 9; i++, payload += 4)
1118 regmap_write(dp->regmap, reg + i * 4,
1119 FIELD_PREP(SDP_REGS, get_unaligned_le32(payload)));
1120
1121 if (sdp->flags & DPTX_SDP_VERTICAL_INTERVAL)
1122 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL,
1123 EN_VERTICAL_SDP << nr,
1124 EN_VERTICAL_SDP << nr);
1125
1126 if (sdp->flags & DPTX_SDP_HORIZONTAL_INTERVAL)
1127 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL,
1128 EN_HORIZONTAL_SDP << nr,
1129 EN_HORIZONTAL_SDP << nr);
1130
1131 return 0;
1132 }
1133
dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp * vsc,struct dw_dp_sdp * sdp)1134 static void dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
1135 struct dw_dp_sdp *sdp)
1136 {
1137 sdp->header.HB0 = 0;
1138 sdp->header.HB1 = DP_SDP_VSC;
1139 sdp->header.HB2 = vsc->revision;
1140 sdp->header.HB3 = vsc->length;
1141
1142 sdp->db[16] = (vsc->pixelformat & 0xf) << 4;
1143 sdp->db[16] |= vsc->colorimetry & 0xf;
1144
1145 switch (vsc->bpc) {
1146 case 8:
1147 sdp->db[17] = 0x1;
1148 break;
1149 case 10:
1150 sdp->db[17] = 0x2;
1151 break;
1152 case 12:
1153 sdp->db[17] = 0x3;
1154 break;
1155 case 16:
1156 sdp->db[17] = 0x4;
1157 break;
1158 case 6:
1159 default:
1160 break;
1161 }
1162
1163 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
1164 sdp->db[17] |= 0x80;
1165
1166 sdp->db[18] = vsc->content_type & 0x7;
1167
1168 sdp->flags |= DPTX_SDP_VERTICAL_INTERVAL;
1169 }
1170
dw_dp_send_vsc_sdp(struct dw_dp * dp)1171 static int dw_dp_send_vsc_sdp(struct dw_dp *dp)
1172 {
1173 struct dw_dp_video *video = &dp->video;
1174 struct drm_dp_vsc_sdp vsc = {};
1175 struct dw_dp_sdp sdp = {};
1176
1177 vsc.revision = 0x5;
1178 vsc.length = 0x13;
1179
1180 switch (video->color_format) {
1181 case DRM_COLOR_FORMAT_YCRCB444:
1182 vsc.pixelformat = DP_PIXELFORMAT_YUV444;
1183 break;
1184 case DRM_COLOR_FORMAT_YCRCB420:
1185 vsc.pixelformat = DP_PIXELFORMAT_YUV420;
1186 break;
1187 case DRM_COLOR_FORMAT_YCRCB422:
1188 vsc.pixelformat = DP_PIXELFORMAT_YUV422;
1189 break;
1190 case DRM_COLOR_FORMAT_RGB444:
1191 default:
1192 vsc.pixelformat = DP_PIXELFORMAT_RGB;
1193 break;
1194 }
1195
1196 if (video->color_format == DRM_COLOR_FORMAT_RGB444)
1197 vsc.colorimetry = DP_COLORIMETRY_DEFAULT;
1198 else
1199 vsc.colorimetry = DP_COLORIMETRY_BT709_YCC;
1200
1201 vsc.bpc = video->bpc;
1202 vsc.dynamic_range = DP_DYNAMIC_RANGE_CTA;
1203 vsc.content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1204
1205 dw_dp_vsc_sdp_pack(&vsc, &sdp);
1206
1207 return dw_dp_send_sdp(dp, &sdp);
1208 }
1209
dw_dp_video_set_pixel_mode(struct dw_dp * dp,u8 pixel_mode)1210 static int dw_dp_video_set_pixel_mode(struct dw_dp *dp, u8 pixel_mode)
1211 {
1212 switch (pixel_mode) {
1213 case DPTX_MP_SINGLE_PIXEL:
1214 case DPTX_MP_DUAL_PIXEL:
1215 case DPTX_MP_QUAD_PIXEL:
1216 break;
1217 default:
1218 return -EINVAL;
1219 }
1220
1221 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, PIXEL_MODE_SELECT,
1222 FIELD_PREP(PIXEL_MODE_SELECT, pixel_mode));
1223
1224 return 0;
1225 }
1226
dw_dp_video_set_msa(struct dw_dp * dp,u8 color_format,u8 bpc,u16 vstart,u16 hstart)1227 static int dw_dp_video_set_msa(struct dw_dp *dp, u8 color_format, u8 bpc,
1228 u16 vstart, u16 hstart)
1229 {
1230 struct dw_dp_link *link = &dp->link;
1231 u16 misc = 0;
1232
1233 if (link->vsc_sdp_extension_for_colorimetry_supported)
1234 misc |= DP_MSA_MISC_COLOR_VSC_SDP;
1235
1236 switch (color_format) {
1237 case DRM_COLOR_FORMAT_RGB444:
1238 misc |= DP_MSA_MISC_COLOR_RGB;
1239 break;
1240 case DRM_COLOR_FORMAT_YCRCB444:
1241 misc |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1242 break;
1243 case DRM_COLOR_FORMAT_YCRCB422:
1244 misc |= DP_MSA_MISC_COLOR_YCBCR_422_BT709;
1245 break;
1246 case DRM_COLOR_FORMAT_YCRCB420:
1247 break;
1248 default:
1249 return -EINVAL;
1250 }
1251
1252 switch (bpc) {
1253 case 6:
1254 misc |= DP_MSA_MISC_6_BPC;
1255 break;
1256 case 8:
1257 misc |= DP_MSA_MISC_8_BPC;
1258 break;
1259 case 10:
1260 misc |= DP_MSA_MISC_10_BPC;
1261 break;
1262 case 12:
1263 misc |= DP_MSA_MISC_12_BPC;
1264 break;
1265 case 16:
1266 misc |= DP_MSA_MISC_16_BPC;
1267 break;
1268 default:
1269 return -EINVAL;
1270 }
1271
1272 regmap_write(dp->regmap, DPTX_VIDEO_MSA1,
1273 FIELD_PREP(VSTART, vstart) | FIELD_PREP(HSTART, hstart));
1274 regmap_write(dp->regmap, DPTX_VIDEO_MSA2, FIELD_PREP(MISC0, misc));
1275 regmap_write(dp->regmap, DPTX_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 8));
1276
1277 return 0;
1278 }
1279
dw_dp_video_disable(struct dw_dp * dp)1280 static void dw_dp_video_disable(struct dw_dp *dp)
1281 {
1282 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE,
1283 FIELD_PREP(VIDEO_STREAM_ENABLE, 0));
1284 }
1285
dw_dp_video_enable(struct dw_dp * dp)1286 static int dw_dp_video_enable(struct dw_dp *dp)
1287 {
1288 struct dw_dp_video *video = &dp->video;
1289 struct dw_dp_link *link = &dp->link;
1290 struct drm_display_mode *mode = &video->mode;
1291 u8 color_format = video->color_format;
1292 u8 bpc = video->bpc;
1293 u8 pixel_mode = video->pixel_mode;
1294 u8 bpp = video->bpp, init_threshold, vic;
1295 u32 hactive, hblank, h_sync_width, h_front_porch;
1296 u32 vactive, vblank, v_sync_width, v_front_porch;
1297 u32 vstart = mode->vtotal - mode->vsync_start;
1298 u32 hstart = mode->htotal - mode->hsync_start;
1299 u32 peak_stream_bandwidth, link_bandwidth;
1300 u32 average_bytes_per_tu, average_bytes_per_tu_frac;
1301 u32 ts, hblank_interval;
1302 u32 value;
1303 int ret;
1304
1305 ret = dw_dp_video_set_pixel_mode(dp, pixel_mode);
1306 if (ret)
1307 return ret;
1308
1309 ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart);
1310 if (ret)
1311 return ret;
1312
1313 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_MAPPING,
1314 FIELD_PREP(VIDEO_MAPPING, video->video_mapping));
1315
1316 /* Configure DPTX_VINPUT_POLARITY_CTRL register */
1317 value = 0;
1318 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1319 value |= FIELD_PREP(HSYNC_IN_POLARITY, 1);
1320 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1321 value |= FIELD_PREP(VSYNC_IN_POLARITY, 1);
1322 regmap_write(dp->regmap, DPTX_VINPUT_POLARITY_CTRL, value);
1323
1324 /* Configure DPTX_VIDEO_CONFIG1 register */
1325 hactive = mode->hdisplay;
1326 hblank = mode->htotal - mode->hdisplay;
1327 value = FIELD_PREP(HACTIVE, hactive) | FIELD_PREP(HBLANK, hblank);
1328 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1329 value |= FIELD_PREP(I_P, 1);
1330 vic = drm_match_cea_mode(mode);
1331 if (vic == 5 || vic == 6 || vic == 7 ||
1332 vic == 10 || vic == 11 || vic == 20 ||
1333 vic == 21 || vic == 22 || vic == 39 ||
1334 vic == 25 || vic == 26 || vic == 40 ||
1335 vic == 44 || vic == 45 || vic == 46 ||
1336 vic == 50 || vic == 51 || vic == 54 ||
1337 vic == 55 || vic == 58 || vic == 59)
1338 value |= R_V_BLANK_IN_OSC;
1339 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG1, value);
1340
1341 /* Configure DPTX_VIDEO_CONFIG2 register */
1342 vblank = mode->vtotal - mode->vdisplay;
1343 vactive = mode->vdisplay;
1344 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG2,
1345 FIELD_PREP(VBLANK, vblank) | FIELD_PREP(VACTIVE, vactive));
1346
1347 /* Configure DPTX_VIDEO_CONFIG3 register */
1348 h_sync_width = mode->hsync_end - mode->hsync_start;
1349 h_front_porch = mode->hsync_start - mode->hdisplay;
1350 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG3,
1351 FIELD_PREP(H_SYNC_WIDTH, h_sync_width) |
1352 FIELD_PREP(H_FRONT_PORCH, h_front_porch));
1353
1354 /* Configure DPTX_VIDEO_CONFIG4 register */
1355 v_sync_width = mode->vsync_end - mode->vsync_start;
1356 v_front_porch = mode->vsync_start - mode->vdisplay;
1357 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG4,
1358 FIELD_PREP(V_SYNC_WIDTH, v_sync_width) |
1359 FIELD_PREP(V_FRONT_PORCH, v_front_porch));
1360
1361 /* Configure DPTX_VIDEO_CONFIG5 register */
1362 peak_stream_bandwidth = mode->clock * bpp / 8;
1363 link_bandwidth = (link->rate / 1000) * link->lanes;
1364 ts = peak_stream_bandwidth * 64 / link_bandwidth;
1365 average_bytes_per_tu = ts / 1000;
1366 average_bytes_per_tu_frac = ts / 100 - average_bytes_per_tu * 10;
1367 if (pixel_mode == DPTX_MP_SINGLE_PIXEL) {
1368 if (average_bytes_per_tu < 6)
1369 init_threshold = 32;
1370 else if (hblank <= 80 && color_format != DRM_COLOR_FORMAT_YCRCB420)
1371 init_threshold = 12;
1372 else if (hblank <= 40 && color_format == DRM_COLOR_FORMAT_YCRCB420)
1373 init_threshold = 3;
1374 else
1375 init_threshold = 16;
1376 } else {
1377 u32 t1 = 0, t2 = 0, t3 = 0;
1378
1379 switch (bpc) {
1380 case 6:
1381 t1 = (4 * 1000 / 9) * link->lanes;
1382 break;
1383 case 8:
1384 if (color_format == DRM_COLOR_FORMAT_YCRCB422) {
1385 t1 = (1000 / 2) * link->lanes;
1386 } else {
1387 if (pixel_mode == DPTX_MP_DUAL_PIXEL)
1388 t1 = (1000 / 3) * link->lanes;
1389 else
1390 t1 = (3000 / 16) * link->lanes;
1391 }
1392 break;
1393 case 10:
1394 if (color_format == DRM_COLOR_FORMAT_YCRCB422)
1395 t1 = (2000 / 5) * link->lanes;
1396 else
1397 t1 = (4000 / 15) * link->lanes;
1398 break;
1399 case 12:
1400 if (color_format == DRM_COLOR_FORMAT_YCRCB422) {
1401 if (pixel_mode == DPTX_MP_DUAL_PIXEL)
1402 t1 = (1000 / 6) * link->lanes;
1403 else
1404 t1 = (1000 / 3) * link->lanes;
1405 } else {
1406 t1 = (2000 / 9) * link->lanes;
1407 }
1408 break;
1409 case 16:
1410 if (color_format != DRM_COLOR_FORMAT_YCRCB422 &&
1411 pixel_mode == DPTX_MP_DUAL_PIXEL)
1412 t1 = (1000 / 6) * link->lanes;
1413 else
1414 t1 = (1000 / 4) * link->lanes;
1415 break;
1416 default:
1417 return -EINVAL;
1418 }
1419
1420 if (color_format == DRM_COLOR_FORMAT_YCRCB420)
1421 t2 = (link->rate / 4) * 1000 / (mode->clock / 2);
1422 else
1423 t2 = (link->rate / 4) * 1000 / mode->clock;
1424
1425 if (average_bytes_per_tu_frac)
1426 t3 = average_bytes_per_tu + 1;
1427 else
1428 t3 = average_bytes_per_tu;
1429 init_threshold = t1 * t2 * t3 / (1000 * 1000);
1430 if (init_threshold <= 16 || average_bytes_per_tu < 10)
1431 init_threshold = 40;
1432 }
1433
1434 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG5,
1435 FIELD_PREP(INIT_THRESHOLD_HI, init_threshold >> 6) |
1436 FIELD_PREP(AVERAGE_BYTES_PER_TU_FRAC, average_bytes_per_tu_frac) |
1437 FIELD_PREP(INIT_THRESHOLD, init_threshold) |
1438 FIELD_PREP(AVERAGE_BYTES_PER_TU, average_bytes_per_tu));
1439
1440 /* Configure DPTX_VIDEO_HBLANK_INTERVAL register */
1441 hblank_interval = hblank * (link->rate / 4) / mode->clock;
1442 regmap_write(dp->regmap, DPTX_VIDEO_HBLANK_INTERVAL,
1443 FIELD_PREP(HBLANK_INTERVAL_EN, 1) |
1444 FIELD_PREP(HBLANK_INTERVAL, hblank_interval));
1445
1446 /* Video stream enable */
1447 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE,
1448 FIELD_PREP(VIDEO_STREAM_ENABLE, 1));
1449
1450 if (link->vsc_sdp_extension_for_colorimetry_supported)
1451 dw_dp_send_vsc_sdp(dp);
1452
1453 return 0;
1454 }
1455
dw_dp_hpd_irq_handler(int irq,void * arg)1456 static irqreturn_t dw_dp_hpd_irq_handler(int irq, void *arg)
1457 {
1458 struct dw_dp *dp = arg;
1459 bool hpd = dw_dp_detect(dp);
1460
1461 mutex_lock(&dp->irq_lock);
1462
1463 dp->hotplug.long_hpd = true;
1464
1465 if (dp->hotplug.status && !hpd) {
1466 usleep_range(2000, 2001);
1467
1468 hpd = dw_dp_detect(dp);
1469 if (hpd)
1470 dp->hotplug.long_hpd = false;
1471 }
1472
1473 dp->hotplug.status = hpd;
1474
1475 mutex_unlock(&dp->irq_lock);
1476
1477 schedule_work(&dp->hpd_work);
1478
1479 return IRQ_HANDLED;
1480 }
1481
dw_dp_hpd_init(struct dw_dp * dp)1482 static void dw_dp_hpd_init(struct dw_dp *dp)
1483 {
1484 dp->hotplug.status = dw_dp_detect(dp);
1485
1486 if (dp->hpd_gpio) {
1487 regmap_update_bits(dp->regmap, DPTX_CCTL, FORCE_HPD,
1488 FIELD_PREP(FORCE_HPD, 1));
1489 return;
1490 }
1491
1492 /* Enable all HPD interrupts */
1493 regmap_update_bits(dp->regmap, DPTX_HPD_INTERRUPT_ENABLE,
1494 HPD_UNPLUG_EN | HPD_PLUG_EN | HPD_IRQ_EN,
1495 FIELD_PREP(HPD_UNPLUG_EN, 1) |
1496 FIELD_PREP(HPD_PLUG_EN, 1) |
1497 FIELD_PREP(HPD_IRQ_EN, 1));
1498
1499 /* Enable all top-level interrupts */
1500 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE,
1501 HPD_EVENT_EN, FIELD_PREP(HPD_EVENT_EN, 1));
1502 }
1503
dw_dp_aux_init(struct dw_dp * dp)1504 static void dw_dp_aux_init(struct dw_dp *dp)
1505 {
1506 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET,
1507 FIELD_PREP(AUX_RESET, 1));
1508 usleep_range(10, 20);
1509 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET,
1510 FIELD_PREP(AUX_RESET, 0));
1511
1512 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE,
1513 AUX_REPLY_EVENT_EN,
1514 FIELD_PREP(AUX_REPLY_EVENT_EN, 1));
1515 }
1516
dw_dp_init(struct dw_dp * dp)1517 static void dw_dp_init(struct dw_dp *dp)
1518 {
1519 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET,
1520 FIELD_PREP(CONTROLLER_RESET, 1));
1521 usleep_range(10, 20);
1522 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET,
1523 FIELD_PREP(CONTROLLER_RESET, 0));
1524
1525 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET,
1526 FIELD_PREP(PHY_SOFT_RESET, 1));
1527 usleep_range(10, 20);
1528 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET,
1529 FIELD_PREP(PHY_SOFT_RESET, 0));
1530
1531 regmap_update_bits(dp->regmap, DPTX_CCTL, DEFAULT_FAST_LINK_TRAIN_EN,
1532 FIELD_PREP(DEFAULT_FAST_LINK_TRAIN_EN, 0));
1533
1534 dw_dp_hpd_init(dp);
1535 dw_dp_aux_init(dp);
1536 }
1537
dw_dp_encoder_enable(struct drm_encoder * encoder)1538 static void dw_dp_encoder_enable(struct drm_encoder *encoder)
1539 {
1540
1541 }
1542
dw_dp_encoder_disable(struct drm_encoder * encoder)1543 static void dw_dp_encoder_disable(struct drm_encoder *encoder)
1544 {
1545 struct dw_dp *dp = encoder_to_dp(encoder);
1546 struct drm_crtc *crtc = encoder->crtc;
1547 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1548
1549 if (!crtc->state->active_changed)
1550 return;
1551
1552 if (dp->split_mode)
1553 s->output_if &= ~(VOP_OUTPUT_IF_DP0 | VOP_OUTPUT_IF_DP1);
1554 else
1555 s->output_if &= ~(dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0);
1556 }
1557
dw_dp_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1558 static int dw_dp_encoder_atomic_check(struct drm_encoder *encoder,
1559 struct drm_crtc_state *crtc_state,
1560 struct drm_connector_state *conn_state)
1561 {
1562 struct dw_dp *dp = encoder_to_dp(encoder);
1563 struct dw_dp_video *video = &dp->video;
1564 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1565 struct drm_display_info *di = &conn_state->connector->display_info;
1566
1567 switch (video->color_format) {
1568 case DRM_COLOR_FORMAT_YCRCB420:
1569 s->output_mode = ROCKCHIP_OUT_MODE_YUV420;
1570 break;
1571 case DRM_COLOR_FORMAT_YCRCB422:
1572 s->output_mode = ROCKCHIP_OUT_MODE_S888_DUMMY;
1573 break;
1574 case DRM_COLOR_FORMAT_RGB444:
1575 case DRM_COLOR_FORMAT_YCRCB444:
1576 default:
1577 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
1578 break;
1579 }
1580
1581 if (dp->split_mode) {
1582 s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE;
1583 s->output_flags |= dp->id ? ROCKCHIP_OUTPUT_DATA_SWAP : 0;
1584 s->output_if |= VOP_OUTPUT_IF_DP0 | VOP_OUTPUT_IF_DP1;
1585 } else {
1586 s->output_if |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0;
1587 }
1588
1589 s->output_type = DRM_MODE_CONNECTOR_DisplayPort;
1590 s->bus_format = video->bus_format;
1591 s->bus_flags = di->bus_flags;
1592 s->tv_state = &conn_state->tv;
1593 s->eotf = HDMI_EOTF_TRADITIONAL_GAMMA_SDR;
1594 s->color_space = V4L2_COLORSPACE_DEFAULT;
1595
1596 return 0;
1597 }
1598
1599 static const struct drm_encoder_helper_funcs dw_dp_encoder_helper_funcs = {
1600 .enable = dw_dp_encoder_enable,
1601 .disable = dw_dp_encoder_disable,
1602 .atomic_check = dw_dp_encoder_atomic_check,
1603 };
1604
dw_dp_aux_write_data(struct dw_dp * dp,const u8 * buffer,size_t size)1605 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size)
1606 {
1607 size_t i, j;
1608
1609 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
1610 size_t num = min_t(size_t, size - i * 4, 4);
1611 u32 value = 0;
1612
1613 for (j = 0; j < num; j++)
1614 value |= buffer[i * 4 + j] << (j * 8);
1615
1616 regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 4, value);
1617 }
1618
1619 return size;
1620 }
1621
dw_dp_aux_read_data(struct dw_dp * dp,u8 * buffer,size_t size)1622 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size)
1623 {
1624 size_t i, j;
1625
1626 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
1627 size_t num = min_t(size_t, size - i * 4, 4);
1628 u32 value;
1629
1630 regmap_read(dp->regmap, DPTX_AUX_DATA0 + i * 4, &value);
1631
1632 for (j = 0; j < num; j++)
1633 buffer[i * 4 + j] = value >> (j * 8);
1634 }
1635
1636 return size;
1637 }
1638
dw_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)1639 static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux,
1640 struct drm_dp_aux_msg *msg)
1641 {
1642 struct dw_dp *dp = container_of(aux, struct dw_dp, aux);
1643 unsigned long timeout = msecs_to_jiffies(250);
1644 u32 status, value;
1645 ssize_t ret = 0;
1646
1647 if (WARN_ON(msg->size > 16))
1648 return -E2BIG;
1649
1650 switch (msg->request & ~DP_AUX_I2C_MOT) {
1651 case DP_AUX_NATIVE_WRITE:
1652 case DP_AUX_I2C_WRITE:
1653 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1654 ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size);
1655 if (ret < 0)
1656 return ret;
1657 break;
1658 case DP_AUX_NATIVE_READ:
1659 case DP_AUX_I2C_READ:
1660 break;
1661 default:
1662 return -EINVAL;
1663 }
1664
1665 if (msg->size > 0)
1666 value = FIELD_PREP(AUX_LEN_REQ, msg->size - 1);
1667 else
1668 value = FIELD_PREP(I2C_ADDR_ONLY, 1);
1669 value |= FIELD_PREP(AUX_CMD_TYPE, msg->request);
1670 value |= FIELD_PREP(AUX_ADDR, msg->address);
1671 regmap_write(dp->regmap, DPTX_AUX_CMD, value);
1672
1673 status = wait_for_completion_timeout(&dp->complete, timeout);
1674 if (!status) {
1675 dev_err(dp->dev, "timeout waiting for AUX reply\n");
1676 return -ETIMEDOUT;
1677 }
1678
1679 regmap_read(dp->regmap, DPTX_AUX_STATUS, &value);
1680 if (value & AUX_TIMEOUT)
1681 return -ETIMEDOUT;
1682
1683 msg->reply = FIELD_GET(AUX_STATUS, value);
1684
1685 if (msg->size > 0 && msg->reply == DP_AUX_NATIVE_REPLY_ACK) {
1686 if (msg->request & DP_AUX_I2C_READ) {
1687 size_t count = FIELD_GET(AUX_BYTES_READ, value) - 1;
1688
1689 if (count != msg->size)
1690 return -EBUSY;
1691
1692 ret = dw_dp_aux_read_data(dp, msg->buffer, count);
1693 if (ret < 0)
1694 return ret;
1695 }
1696 }
1697
1698 return ret;
1699 }
1700
dw_dp_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)1701 static int dw_dp_bridge_mode_valid(struct drm_bridge *bridge,
1702 const struct drm_display_info *info,
1703 const struct drm_display_mode *mode)
1704 {
1705 struct dw_dp *dp = bridge_to_dp(bridge);
1706 struct dw_dp_link *link = &dp->link;
1707 struct drm_display_mode m;
1708 u32 min_bpp;
1709
1710 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB420 &&
1711 link->vsc_sdp_extension_for_colorimetry_supported)
1712 min_bpp = 12;
1713 else if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
1714 min_bpp = 16;
1715 else if (info->color_formats & DRM_COLOR_FORMAT_RGB444)
1716 min_bpp = 18;
1717 else
1718 min_bpp = 24;
1719
1720 drm_mode_copy(&m, mode);
1721
1722 if (dp->split_mode)
1723 drm_mode_convert_to_origin_mode(&m);
1724
1725 if (!dw_dp_bandwidth_ok(dp, &m, min_bpp, link->lanes, link->rate))
1726 return MODE_CLOCK_HIGH;
1727
1728 return MODE_OK;
1729 }
1730
dw_dp_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)1731 static int dw_dp_bridge_attach(struct drm_bridge *bridge,
1732 enum drm_bridge_attach_flags flags)
1733 {
1734 struct dw_dp *dp = bridge_to_dp(bridge);
1735 struct drm_connector *connector = &dp->connector;
1736 int ret;
1737
1738 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
1739 return 0;
1740
1741 if (!bridge->encoder) {
1742 DRM_DEV_ERROR(dp->dev, "Parent encoder object not found");
1743 return -ENODEV;
1744 }
1745
1746 connector->polled = DRM_CONNECTOR_POLL_HPD;
1747 connector->ycbcr_420_allowed = true;
1748
1749 ret = drm_connector_init(bridge->dev, connector,
1750 &dw_dp_connector_funcs,
1751 DRM_MODE_CONNECTOR_DisplayPort);
1752 if (ret) {
1753 DRM_DEV_ERROR(dp->dev, "Failed to initialize connector\n");
1754 return ret;
1755 }
1756
1757 drm_connector_helper_add(connector,
1758 &dw_dp_connector_helper_funcs);
1759
1760 drm_connector_attach_encoder(connector, bridge->encoder);
1761
1762 return 0;
1763 }
1764
dw_dp_bridge_detach(struct drm_bridge * bridge)1765 static void dw_dp_bridge_detach(struct drm_bridge *bridge)
1766 {
1767 struct dw_dp *dp = bridge_to_dp(bridge);
1768
1769 drm_connector_cleanup(&dp->connector);
1770 }
1771
dw_dp_bridge_atomic_pre_enable(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state)1772 static void dw_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1773 struct drm_bridge_state *bridge_state)
1774 {
1775 struct dw_dp *dp = bridge_to_dp(bridge);
1776 struct dw_dp_video *video = &dp->video;
1777 struct drm_crtc_state *crtc_state = bridge->encoder->crtc->state;
1778 struct drm_display_mode *m = &video->mode;
1779
1780 drm_mode_copy(m, &crtc_state->adjusted_mode);
1781
1782 if (dp->split_mode)
1783 drm_mode_convert_to_origin_mode(m);
1784 }
1785
dw_dp_needs_link_retrain(struct dw_dp * dp)1786 static bool dw_dp_needs_link_retrain(struct dw_dp *dp)
1787 {
1788 struct dw_dp_link *link = &dp->link;
1789 u8 link_status[DP_LINK_STATUS_SIZE];
1790
1791 if (!dw_dp_link_train_valid(&link->train))
1792 return false;
1793
1794 if (drm_dp_dpcd_read_link_status(&dp->aux, link_status) < 0)
1795 return false;
1796
1797 /* Retrain if Channel EQ or CR not ok */
1798 return !drm_dp_channel_eq_ok(link_status, dp->link.lanes);
1799 }
1800
dw_dp_link_disable(struct dw_dp * dp)1801 static void dw_dp_link_disable(struct dw_dp *dp)
1802 {
1803 struct dw_dp_link *link = &dp->link;
1804
1805 if (dw_dp_detect(dp))
1806 dw_dp_link_power_down(dp);
1807
1808 dw_dp_phy_xmit_enable(dp, 0);
1809
1810 phy_power_off(dp->phy);
1811
1812 link->train.clock_recovered = false;
1813 link->train.channel_equalized = false;
1814 }
1815
dw_dp_link_enable(struct dw_dp * dp)1816 static int dw_dp_link_enable(struct dw_dp *dp)
1817 {
1818 int ret;
1819
1820 ret = phy_power_on(dp->phy);
1821 if (ret)
1822 return ret;
1823
1824 ret = dw_dp_link_power_up(dp);
1825 if (ret < 0)
1826 return ret;
1827
1828 ret = dw_dp_link_train(dp);
1829 if (ret < 0) {
1830 dev_err(dp->dev, "link training failed: %d\n", ret);
1831 return ret;
1832 }
1833
1834 return 0;
1835 }
1836
dw_dp_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_state)1837 static void dw_dp_bridge_atomic_enable(struct drm_bridge *bridge,
1838 struct drm_bridge_state *old_state)
1839 {
1840 struct dw_dp *dp = bridge_to_dp(bridge);
1841 int ret;
1842
1843 set_bit(0, dp->sdp_reg_bank);
1844
1845 ret = dw_dp_link_enable(dp);
1846 if (ret < 0) {
1847 dev_err(dp->dev, "failed to enable link: %d\n", ret);
1848 return;
1849 }
1850
1851 ret = dw_dp_video_enable(dp);
1852 if (ret < 0) {
1853 dev_err(dp->dev, "failed to enable video: %d\n", ret);
1854 return;
1855 }
1856 }
1857
dw_dp_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1858 static void dw_dp_bridge_atomic_disable(struct drm_bridge *bridge,
1859 struct drm_bridge_state *old_bridge_state)
1860 {
1861 struct dw_dp *dp = bridge_to_dp(bridge);
1862
1863 dw_dp_video_disable(dp);
1864 dw_dp_link_disable(dp);
1865 bitmap_zero(dp->sdp_reg_bank, SDP_REG_BANK_SIZE);
1866 }
1867
dw_dp_detect_dpcd(struct dw_dp * dp)1868 static enum drm_connector_status dw_dp_detect_dpcd(struct dw_dp *dp)
1869 {
1870 int ret;
1871
1872 ret = phy_power_on(dp->phy);
1873 if (ret)
1874 return ret;
1875
1876 ret = dw_dp_link_probe(dp);
1877 if (ret) {
1878 phy_power_off(dp->phy);
1879 dev_err(dp->dev, "failed to probe DP link: %d\n", ret);
1880 return connector_status_disconnected;
1881 }
1882
1883 phy_power_off(dp->phy);
1884
1885 return connector_status_connected;
1886 }
1887
dw_dp_bridge_detect(struct drm_bridge * bridge)1888 static enum drm_connector_status dw_dp_bridge_detect(struct drm_bridge *bridge)
1889 {
1890 struct dw_dp *dp = bridge_to_dp(bridge);
1891 enum drm_connector_status status;
1892
1893 if (dw_dp_detect(dp))
1894 status = dw_dp_detect_dpcd(dp);
1895 else
1896 status = connector_status_disconnected;
1897
1898 if (status == connector_status_connected)
1899 extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, true);
1900 else
1901 extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, false);
1902
1903 return status;
1904 }
1905
dw_dp_bridge_get_edid(struct drm_bridge * bridge,struct drm_connector * connector)1906 static struct edid *dw_dp_bridge_get_edid(struct drm_bridge *bridge,
1907 struct drm_connector *connector)
1908 {
1909 struct dw_dp *dp = bridge_to_dp(bridge);
1910 struct edid *edid;
1911 int ret;
1912
1913 ret = phy_power_on(dp->phy);
1914 if (ret)
1915 return NULL;
1916
1917 edid = drm_get_edid(connector, &dp->aux.ddc);
1918
1919 phy_power_off(dp->phy);
1920
1921 return edid;
1922 }
1923
dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,unsigned int * num_output_fmts)1924 static u32 *dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
1925 struct drm_bridge_state *bridge_state,
1926 struct drm_crtc_state *crtc_state,
1927 struct drm_connector_state *conn_state,
1928 unsigned int *num_output_fmts)
1929 {
1930 struct dw_dp *dp = bridge_to_dp(bridge);
1931 struct dw_dp_link *link = &dp->link;
1932 struct drm_display_info *di = &conn_state->connector->display_info;
1933 struct drm_display_mode mode = crtc_state->mode;
1934 u32 *output_fmts;
1935 unsigned int i, j = 0;
1936
1937 if (dp->split_mode)
1938 drm_mode_convert_to_origin_mode(&mode);
1939
1940 *num_output_fmts = 0;
1941
1942 output_fmts = kcalloc(ARRAY_SIZE(possible_output_fmts),
1943 sizeof(*output_fmts), GFP_KERNEL);
1944 if (!output_fmts)
1945 return NULL;
1946
1947 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) {
1948 const struct dw_dp_output_format *fmt = &possible_output_fmts[i];
1949
1950 if (fmt->bpc > conn_state->max_bpc)
1951 continue;
1952
1953 if (!(di->color_formats & fmt->color_format))
1954 continue;
1955
1956 if (fmt->color_format == DRM_COLOR_FORMAT_YCRCB420 &&
1957 !link->vsc_sdp_extension_for_colorimetry_supported)
1958 continue;
1959
1960 if (drm_mode_is_420_only(di, &mode) &&
1961 fmt->color_format != DRM_COLOR_FORMAT_YCRCB420)
1962 continue;
1963
1964 if (!dw_dp_bandwidth_ok(dp, &mode, fmt->bpp, link->lanes, link->rate))
1965 continue;
1966
1967 output_fmts[j++] = fmt->bus_format;
1968 }
1969
1970 *num_output_fmts = j;
1971
1972 return output_fmts;
1973 }
1974
dw_dp_bridge_atomic_check(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1975 static int dw_dp_bridge_atomic_check(struct drm_bridge *bridge,
1976 struct drm_bridge_state *bridge_state,
1977 struct drm_crtc_state *crtc_state,
1978 struct drm_connector_state *conn_state)
1979 {
1980 struct dw_dp *dp = bridge_to_dp(bridge);
1981 struct dw_dp_video *video = &dp->video;
1982 const struct dw_dp_output_format *fmt =
1983 dw_dp_get_output_format(bridge_state->output_bus_cfg.format);
1984
1985 dev_dbg(dp->dev, "input format 0x%04x, output format 0x%04x\n",
1986 bridge_state->input_bus_cfg.format,
1987 bridge_state->output_bus_cfg.format);
1988
1989 video->video_mapping = fmt->video_mapping;
1990 video->color_format = fmt->color_format;
1991 video->bus_format = fmt->bus_format;
1992 video->bpc = fmt->bpc;
1993 video->bpp = fmt->bpp;
1994
1995 return 0;
1996 }
1997
1998 static const struct drm_bridge_funcs dw_dp_bridge_funcs = {
1999 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2000 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2001 .atomic_reset = drm_atomic_helper_bridge_reset,
2002 .atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt,
2003 .atomic_get_output_bus_fmts = dw_dp_bridge_atomic_get_output_bus_fmts,
2004 .attach = dw_dp_bridge_attach,
2005 .detach = dw_dp_bridge_detach,
2006 .mode_valid = dw_dp_bridge_mode_valid,
2007 .atomic_check = dw_dp_bridge_atomic_check,
2008 .atomic_pre_enable = dw_dp_bridge_atomic_pre_enable,
2009 .atomic_enable = dw_dp_bridge_atomic_enable,
2010 .atomic_disable = dw_dp_bridge_atomic_disable,
2011 .detect = dw_dp_bridge_detect,
2012 .get_edid = dw_dp_bridge_get_edid,
2013 };
2014
dw_dp_link_retrain(struct dw_dp * dp)2015 static int dw_dp_link_retrain(struct dw_dp *dp)
2016 {
2017 struct drm_device *dev = dp->bridge.dev;
2018 struct drm_modeset_acquire_ctx ctx;
2019 int ret;
2020
2021 if (!dw_dp_needs_link_retrain(dp))
2022 return 0;
2023
2024 dev_dbg(dp->dev, "Retraining link\n");
2025
2026 drm_modeset_acquire_init(&ctx, 0);
2027 for (;;) {
2028 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
2029 if (ret != -EDEADLK)
2030 break;
2031
2032 drm_modeset_backoff(&ctx);
2033 }
2034
2035 ret = dw_dp_link_train(dp);
2036 drm_modeset_drop_locks(&ctx);
2037 drm_modeset_acquire_fini(&ctx);
2038
2039 return ret;
2040 }
2041
dw_dp_hpd_work(struct work_struct * work)2042 static void dw_dp_hpd_work(struct work_struct *work)
2043 {
2044 struct dw_dp *dp = container_of(work, struct dw_dp, hpd_work);
2045 bool long_hpd;
2046 int ret;
2047
2048 mutex_lock(&dp->irq_lock);
2049 long_hpd = dp->hotplug.long_hpd;
2050 mutex_unlock(&dp->irq_lock);
2051
2052 dev_dbg(dp->dev, "got hpd irq - %s\n", long_hpd ? "long" : "short");
2053
2054 if (!long_hpd) {
2055 ret = dw_dp_link_retrain(dp);
2056 if (ret)
2057 dev_warn(dp->dev, "Retrain link failed\n");
2058 } else {
2059 drm_helper_hpd_irq_event(dp->bridge.dev);
2060 }
2061 }
2062
dw_dp_handle_hpd_event(struct dw_dp * dp)2063 static void dw_dp_handle_hpd_event(struct dw_dp *dp)
2064 {
2065 u32 value;
2066
2067 mutex_lock(&dp->irq_lock);
2068
2069 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value);
2070
2071 if (value & HPD_IRQ) {
2072 dev_dbg(dp->dev, "IRQ from the HPD\n");
2073 dp->hotplug.long_hpd = false;
2074 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_IRQ);
2075 }
2076
2077 if (value & HPD_HOT_PLUG) {
2078 dev_dbg(dp->dev, "Hot plug detected\n");
2079 dp->hotplug.long_hpd = true;
2080 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_PLUG);
2081 }
2082
2083 if (value & HPD_HOT_UNPLUG) {
2084 dev_dbg(dp->dev, "Unplug detected\n");
2085 dp->hotplug.long_hpd = true;
2086 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_UNPLUG);
2087 }
2088
2089 mutex_unlock(&dp->irq_lock);
2090
2091 schedule_work(&dp->hpd_work);
2092 }
2093
dw_dp_irq_handler(int irq,void * data)2094 static irqreturn_t dw_dp_irq_handler(int irq, void *data)
2095 {
2096 struct dw_dp *dp = data;
2097 u32 value;
2098
2099 regmap_read(dp->regmap, DPTX_GENERAL_INTERRUPT, &value);
2100 if (!value)
2101 return IRQ_NONE;
2102
2103 if (value & HPD_EVENT)
2104 dw_dp_handle_hpd_event(dp);
2105
2106 if (value & AUX_REPLY_EVENT) {
2107 regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT,
2108 AUX_REPLY_EVENT);
2109 complete(&dp->complete);
2110 }
2111
2112 return IRQ_HANDLED;
2113 }
2114
dw_dp_audio_hw_params(struct device * dev,void * data,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)2115 static int dw_dp_audio_hw_params(struct device *dev, void *data,
2116 struct hdmi_codec_daifmt *daifmt,
2117 struct hdmi_codec_params *params)
2118 {
2119 struct dw_dp *dp = dev_get_drvdata(dev);
2120 struct dw_dp_audio *audio = &dp->audio;
2121 u8 audio_data_in_en, num_channels, audio_inf_select;
2122
2123 audio->channels = params->cea.channels;
2124
2125 switch (params->cea.channels) {
2126 case 1:
2127 audio_data_in_en = 0x1;
2128 num_channels = 0x0;
2129 break;
2130 case 2:
2131 audio_data_in_en = 0x1;
2132 num_channels = 0x1;
2133 break;
2134 case 8:
2135 audio_data_in_en = 0xf;
2136 num_channels = 0x7;
2137 break;
2138 default:
2139 dev_err(dp->dev, "invalid channels %d\n", params->cea.channels);
2140 return -EINVAL;
2141 }
2142
2143 switch (daifmt->fmt) {
2144 case HDMI_SPDIF:
2145 audio_inf_select = 0x1;
2146 break;
2147 case HDMI_I2S:
2148 audio_inf_select = 0x0;
2149 break;
2150 default:
2151 dev_err(dp->dev, "invalid daifmt %d\n", daifmt->fmt);
2152 return -EINVAL;
2153 }
2154
2155 regmap_update_bits(dp->regmap, DPTX_AUD_CONFIG1,
2156 AUDIO_DATA_IN_EN | NUM_CHANNELS | AUDIO_DATA_WIDTH |
2157 AUDIO_INF_SELECT,
2158 FIELD_PREP(AUDIO_DATA_IN_EN, audio_data_in_en) |
2159 FIELD_PREP(NUM_CHANNELS, num_channels) |
2160 FIELD_PREP(AUDIO_DATA_WIDTH, params->sample_width) |
2161 FIELD_PREP(AUDIO_INF_SELECT, audio_inf_select));
2162
2163 return 0;
2164 }
2165
dw_dp_audio_infoframe_send(struct dw_dp * dp)2166 static int dw_dp_audio_infoframe_send(struct dw_dp *dp)
2167 {
2168 struct dw_dp_audio *audio = &dp->audio;
2169 struct hdmi_audio_infoframe frame;
2170 struct dp_sdp_header header;
2171 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
2172 u8 size = sizeof(buffer);
2173 int i, j, ret;
2174
2175 header.HB0 = 0;
2176 header.HB1 = HDMI_INFOFRAME_TYPE_AUDIO;
2177 header.HB2 = 0x1b;
2178 header.HB3 = 0x48;
2179
2180 ret = hdmi_audio_infoframe_init(&frame);
2181 if (ret < 0)
2182 return ret;
2183
2184 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
2185 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
2186 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
2187 frame.channels = audio->channels;
2188
2189 ret = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2190 if (ret < 0)
2191 return ret;
2192
2193 regmap_write(dp->regmap, DPTX_SDP_REGISTER_BANK,
2194 get_unaligned_le32(&header));
2195
2196 for (i = 1; i < DIV_ROUND_UP(size, 4); i++) {
2197 size_t num = min_t(size_t, size - i * 4, 4);
2198 u32 value = 0;
2199
2200 for (j = 0; j < num; j++)
2201 value |= buffer[i * 4 + j] << (j * 8);
2202
2203 regmap_write(dp->regmap, DPTX_SDP_REGISTER_BANK + 4 * i, value);
2204 }
2205
2206 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL,
2207 EN_VERTICAL_SDP, FIELD_PREP(EN_VERTICAL_SDP, 1));
2208
2209 return 0;
2210 }
2211
dw_dp_audio_startup(struct device * dev,void * data)2212 static int dw_dp_audio_startup(struct device *dev, void *data)
2213 {
2214 struct dw_dp *dp = dev_get_drvdata(dev);
2215
2216 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL,
2217 EN_AUDIO_STREAM_SDP | EN_AUDIO_TIMESTAMP_SDP,
2218 FIELD_PREP(EN_AUDIO_STREAM_SDP, 1) |
2219 FIELD_PREP(EN_AUDIO_TIMESTAMP_SDP, 1));
2220 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL,
2221 EN_AUDIO_STREAM_SDP,
2222 FIELD_PREP(EN_AUDIO_STREAM_SDP, 1));
2223
2224 return dw_dp_audio_infoframe_send(dp);
2225 }
2226
dw_dp_audio_shutdown(struct device * dev,void * data)2227 static void dw_dp_audio_shutdown(struct device *dev, void *data)
2228 {
2229 struct dw_dp *dp = dev_get_drvdata(dev);
2230
2231 regmap_update_bits(dp->regmap, DPTX_AUD_CONFIG1, AUDIO_DATA_IN_EN,
2232 FIELD_PREP(AUDIO_DATA_IN_EN, 0));
2233 }
2234
dw_dp_audio_get_eld(struct device * dev,void * data,uint8_t * buf,size_t len)2235 static int dw_dp_audio_get_eld(struct device *dev, void *data, uint8_t *buf,
2236 size_t len)
2237 {
2238 struct dw_dp *dp = dev_get_drvdata(dev);
2239 struct drm_connector *connector = &dp->connector;
2240
2241 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2242
2243 return 0;
2244 }
2245
2246 static const struct hdmi_codec_ops dw_dp_audio_codec_ops = {
2247 .hw_params = dw_dp_audio_hw_params,
2248 .audio_startup = dw_dp_audio_startup,
2249 .audio_shutdown = dw_dp_audio_shutdown,
2250 .get_eld = dw_dp_audio_get_eld,
2251 };
2252
dw_dp_register_audio_driver(struct dw_dp * dp)2253 static int dw_dp_register_audio_driver(struct dw_dp *dp)
2254 {
2255 struct dw_dp_audio *audio = &dp->audio;
2256 struct hdmi_codec_pdata codec_data = {
2257 .ops = &dw_dp_audio_codec_ops,
2258 .spdif = 1,
2259 .i2s = 1,
2260 .max_i2s_channels = 8,
2261 };
2262
2263 audio->pdev = platform_device_register_data(dp->dev,
2264 HDMI_CODEC_DRV_NAME,
2265 PLATFORM_DEVID_AUTO,
2266 &codec_data,
2267 sizeof(codec_data));
2268
2269 return PTR_ERR_OR_ZERO(audio->pdev);
2270 }
2271
dw_dp_unregister_audio_driver(void * data)2272 static void dw_dp_unregister_audio_driver(void *data)
2273 {
2274 struct dw_dp *dp = data;
2275 struct dw_dp_audio *audio = &dp->audio;
2276
2277 if (audio->pdev) {
2278 platform_device_unregister(audio->pdev);
2279 audio->pdev = NULL;
2280 }
2281 }
2282
dw_dp_aux_unregister(void * data)2283 static void dw_dp_aux_unregister(void *data)
2284 {
2285 struct dw_dp *dp = data;
2286
2287 drm_dp_aux_unregister(&dp->aux);
2288 }
2289
dw_dp_bind(struct device * dev,struct device * master,void * data)2290 static int dw_dp_bind(struct device *dev, struct device *master, void *data)
2291 {
2292 struct dw_dp *dp = dev_get_drvdata(dev);
2293 struct drm_device *drm_dev = data;
2294 struct drm_encoder *encoder = &dp->encoder;
2295 struct drm_bridge *bridge = &dp->bridge;
2296 int ret;
2297
2298 if (!dp->left) {
2299 drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_TMDS);
2300 drm_encoder_helper_add(encoder, &dw_dp_encoder_helper_funcs);
2301
2302 encoder->possible_crtcs =
2303 rockchip_drm_of_find_possible_crtcs(drm_dev, dev->of_node);
2304
2305 ret = drm_bridge_attach(encoder, bridge, NULL, 0);
2306 if (ret) {
2307 dev_err(dev, "failed to attach bridge: %d\n", ret);
2308 return ret;
2309 }
2310 }
2311
2312 if (dp->right) {
2313 struct dw_dp *secondary = dp->right;
2314
2315 ret = drm_bridge_attach(encoder, &secondary->bridge, bridge,
2316 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
2317 if (ret)
2318 return ret;
2319 }
2320
2321 pm_runtime_enable(dp->dev);
2322 pm_runtime_get_sync(dp->dev);
2323
2324 return 0;
2325 }
2326
dw_dp_unbind(struct device * dev,struct device * master,void * data)2327 static void dw_dp_unbind(struct device *dev, struct device *master, void *data)
2328 {
2329 struct dw_dp *dp = dev_get_drvdata(dev);
2330
2331 pm_runtime_put(dp->dev);
2332 pm_runtime_disable(dp->dev);
2333
2334 drm_encoder_cleanup(&dp->encoder);
2335 }
2336
2337 static const struct component_ops dw_dp_component_ops = {
2338 .bind = dw_dp_bind,
2339 .unbind = dw_dp_unbind,
2340 };
2341
2342 static const struct regmap_range dw_dp_readable_ranges[] = {
2343 regmap_reg_range(DPTX_VERSION_NUMBER, DPTX_ID),
2344 regmap_reg_range(DPTX_CONFIG_REG1, DPTX_CONFIG_REG3),
2345 regmap_reg_range(DPTX_CCTL, DPTX_SOFT_RESET_CTRL),
2346 regmap_reg_range(DPTX_VSAMPLE_CTRL, DPTX_VIDEO_HBLANK_INTERVAL),
2347 regmap_reg_range(DPTX_AUD_CONFIG1, DPTX_AUD_CONFIG1),
2348 regmap_reg_range(DPTX_SDP_VERTICAL_CTRL, DPTX_SDP_STATUS_EN),
2349 regmap_reg_range(DPTX_PHYIF_CTRL, DPTX_PHYIF_PWRDOWN_CTRL),
2350 regmap_reg_range(DPTX_AUX_CMD, DPTX_AUX_DATA3),
2351 regmap_reg_range(DPTX_GENERAL_INTERRUPT, DPTX_HPD_INTERRUPT_ENABLE),
2352 };
2353
2354 static const struct regmap_access_table dw_dp_readable_table = {
2355 .yes_ranges = dw_dp_readable_ranges,
2356 .n_yes_ranges = ARRAY_SIZE(dw_dp_readable_ranges),
2357 };
2358
2359 static const struct regmap_config dw_dp_regmap_config = {
2360 .reg_bits = 32,
2361 .reg_stride = 4,
2362 .val_bits = 32,
2363 .fast_io = true,
2364 .max_register = DPTX_MAX_REGISTER,
2365 .rd_table = &dw_dp_readable_table,
2366 };
2367
dw_dp_probe(struct platform_device * pdev)2368 static int dw_dp_probe(struct platform_device *pdev)
2369 {
2370 struct device *dev = &pdev->dev;
2371 struct dw_dp *dp;
2372 void __iomem *base;
2373 int id, ret;
2374
2375 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
2376 if (!dp)
2377 return -ENOMEM;
2378
2379 id = of_alias_get_id(dev->of_node, "dp");
2380 if (id < 0)
2381 id = 0;
2382
2383 dp->id = id;
2384 dp->dev = dev;
2385 dp->video.pixel_mode = DPTX_MP_QUAD_PIXEL;
2386
2387 mutex_init(&dp->irq_lock);
2388 INIT_WORK(&dp->hpd_work, dw_dp_hpd_work);
2389 init_completion(&dp->complete);
2390
2391 base = devm_platform_ioremap_resource(pdev, 0);
2392 if (IS_ERR(base))
2393 return PTR_ERR(base);
2394
2395 dp->regmap = devm_regmap_init_mmio(dev, base, &dw_dp_regmap_config);
2396 if (IS_ERR(dp->regmap))
2397 return dev_err_probe(dev, PTR_ERR(dp->regmap),
2398 "failed to create regmap\n");
2399
2400 dp->phy = devm_of_phy_get(dev, dev->of_node, NULL);
2401 if (IS_ERR(dp->phy))
2402 return dev_err_probe(dev, PTR_ERR(dp->phy),
2403 "failed to get phy\n");
2404
2405 ret = devm_clk_bulk_get_all(dev, &dp->clks);
2406 if (ret < 1)
2407 return dev_err_probe(dev, ret, "failed to get clocks\n");
2408
2409 dp->nr_clks = ret;
2410
2411 dp->rstc = devm_reset_control_get(dev, NULL);
2412 if (IS_ERR(dp->rstc))
2413 return dev_err_probe(dev, PTR_ERR(dp->rstc),
2414 "failed to get reset control\n");
2415
2416 dp->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2417 if (IS_ERR(dp->hpd_gpio))
2418 return dev_err_probe(dev, PTR_ERR(dp->hpd_gpio),
2419 "failed to get hpd GPIO\n");
2420 if (dp->hpd_gpio) {
2421 int hpd_irq = gpiod_to_irq(dp->hpd_gpio);
2422
2423 ret = devm_request_threaded_irq(dev, hpd_irq, NULL,
2424 dw_dp_hpd_irq_handler,
2425 IRQF_TRIGGER_RISING |
2426 IRQF_TRIGGER_FALLING |
2427 IRQF_ONESHOT, "dw-dp-hpd", dp);
2428 if (ret) {
2429 dev_err(dev, "failed to request HPD interrupt\n");
2430 return ret;
2431 }
2432 }
2433
2434 dp->irq = platform_get_irq(pdev, 0);
2435 if (dp->irq < 0)
2436 return dp->irq;
2437
2438 irq_set_status_flags(dp->irq, IRQ_NOAUTOEN);
2439 ret = devm_request_threaded_irq(dev, dp->irq, NULL, dw_dp_irq_handler,
2440 IRQF_ONESHOT, dev_name(dev), dp);
2441 if (ret) {
2442 dev_err(dev, "failed to request irq: %d\n", ret);
2443 return ret;
2444 }
2445
2446 dp->extcon = devm_extcon_dev_allocate(dev, dw_dp_cable);
2447 if (IS_ERR(dp->extcon))
2448 return dev_err_probe(dev, PTR_ERR(dp->extcon),
2449 "failed to allocate extcon device\n");
2450
2451 ret = devm_extcon_dev_register(dev, dp->extcon);
2452 if (ret)
2453 return dev_err_probe(dev, ret,
2454 "failed to register extcon device\n");
2455
2456 ret = dw_dp_register_audio_driver(dp);
2457 if (ret)
2458 return ret;
2459
2460 ret = devm_add_action_or_reset(dev, dw_dp_unregister_audio_driver, dp);
2461 if (ret)
2462 return ret;
2463
2464 dp->aux.dev = dev;
2465 dp->aux.name = dev_name(dev);
2466 dp->aux.transfer = dw_dp_aux_transfer;
2467 ret = drm_dp_aux_register(&dp->aux);
2468 if (ret)
2469 return ret;
2470
2471 ret = devm_add_action_or_reset(dev, dw_dp_aux_unregister, dp);
2472 if (ret)
2473 return ret;
2474
2475 dp->bridge.of_node = dev->of_node;
2476 dp->bridge.funcs = &dw_dp_bridge_funcs;
2477 dp->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
2478 DRM_BRIDGE_OP_HPD;
2479 dp->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
2480
2481 platform_set_drvdata(pdev, dp);
2482
2483 if (device_property_read_bool(dev, "split-mode")) {
2484 struct dw_dp *secondary = dw_dp_find_by_id(dev->driver, !dp->id);
2485
2486 if (!secondary)
2487 return -EPROBE_DEFER;
2488
2489 dp->right = secondary;
2490 dp->split_mode = true;
2491 secondary->left = dp;
2492 secondary->split_mode = true;
2493 }
2494
2495 return component_add(dev, &dw_dp_component_ops);
2496 }
2497
dw_dp_remove(struct platform_device * pdev)2498 static int dw_dp_remove(struct platform_device *pdev)
2499 {
2500 struct dw_dp *dp = platform_get_drvdata(pdev);
2501
2502 component_del(dp->dev, &dw_dp_component_ops);
2503 cancel_work_sync(&dp->hpd_work);
2504
2505 return 0;
2506 }
2507
dw_dp_runtime_suspend(struct device * dev)2508 static int __maybe_unused dw_dp_runtime_suspend(struct device *dev)
2509 {
2510 struct dw_dp *dp = dev_get_drvdata(dev);
2511
2512 disable_irq(dp->irq);
2513
2514 clk_bulk_disable_unprepare(dp->nr_clks, dp->clks);
2515
2516 return 0;
2517 }
2518
dw_dp_runtime_resume(struct device * dev)2519 static int __maybe_unused dw_dp_runtime_resume(struct device *dev)
2520 {
2521 struct dw_dp *dp = dev_get_drvdata(dev);
2522 int ret;
2523
2524 ret = clk_bulk_prepare_enable(dp->nr_clks, dp->clks);
2525 if (ret)
2526 return ret;
2527
2528 reset_control_assert(dp->rstc);
2529 udelay(10);
2530 reset_control_deassert(dp->rstc);
2531
2532 dw_dp_init(dp);
2533 enable_irq(dp->irq);
2534
2535 return 0;
2536 }
2537
2538 static const struct dev_pm_ops dw_dp_pm_ops = {
2539 SET_RUNTIME_PM_OPS(dw_dp_runtime_suspend, dw_dp_runtime_resume, NULL)
2540 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2541 pm_runtime_force_resume)
2542 };
2543
2544 static const struct of_device_id dw_dp_of_match[] = {
2545 { .compatible = "rockchip,rk3588-dp", },
2546 {}
2547 };
2548 MODULE_DEVICE_TABLE(of, dw_dp_of_match);
2549
2550 struct platform_driver dw_dp_driver = {
2551 .probe = dw_dp_probe,
2552 .remove = dw_dp_remove,
2553 .driver = {
2554 .name = "dw-dp",
2555 .of_match_table = dw_dp_of_match,
2556 .pm = &dw_dp_pm_ops,
2557 },
2558 };
2559