1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Rockchip Electronics Co.Ltd
4 * Author:
5 * Guochun Huang <hero.huang@rock-chips.com>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/component.h>
10 #include <linux/gpio.h>
11 #include <linux/iopoll.h>
12 #include <linux/math64.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/of_gpio.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/phy/phy.h>
21
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_crtc.h>
24 #include <drm/drm_crtc_helper.h>
25 #include <drm/drm_dsc.h>
26 #include <drm/drm_mipi_dsi.h>
27 #include <drm/drm_of.h>
28 #include <drm/drm_panel.h>
29 #include <video/mipi_display.h>
30 #include <video/videomode.h>
31 #include <asm/unaligned.h>
32 #include <uapi/linux/videodev2.h>
33 #include <drm/drm_panel.h>
34 #include <drm/drm_connector.h>
35 #include <drm/drm_probe_helper.h>
36 #include <drm/drm_simple_kms_helper.h>
37
38 #include "rockchip_drm_drv.h"
39 #include "rockchip_drm_vop.h"
40
41 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l)))
42
43 #define DSI2_PWR_UP 0x000c
44 #define RESET 0
45 #define POWER_UP BIT(0)
46 #define CMD_TX_MODE(x) UPDATE(x, 24, 24)
47 #define DSI2_SOFT_RESET 0x0010
48 #define SYS_RSTN BIT(2)
49 #define PHY_RSTN BIT(1)
50 #define IPI_RSTN BIT(0)
51 #define INT_ST_MAIN 0x0014
52 #define DSI2_MODE_CTRL 0x0018
53 #define DSI2_MODE_STATUS 0x001c
54 #define DSI2_CORE_STATUS 0x0020
55 #define PRI_RD_DATA_AVAIL BIT(26)
56 #define PRI_FIFOS_NOT_EMPTY BIT(25)
57 #define PRI_BUSY BIT(24)
58 #define CRI_RD_DATA_AVAIL BIT(18)
59 #define CRT_FIFOS_NOT_EMPTY BIT(17)
60 #define CRI_BUSY BIT(16)
61 #define IPI_FIFOS_NOT_EMPTY BIT(9)
62 #define IPI_BUSY BIT(8)
63 #define CORE_FIFOS_NOT_EMPTY BIT(1)
64 #define CORE_BUSY BIT(0)
65 #define MANUAL_MODE_CFG 0x0024
66 #define MANUAL_MODE_EN BIT(0)
67 #define DSI2_TIMEOUT_HSTX_CFG 0x0048
68 #define TO_HSTX(x) UPDATE(x, 15, 0)
69 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c
70 #define TO_HSTXRDY(x) UPDATE(x, 15, 0)
71 #define DSI2_TIMEOUT_LPRX_CFG 0x0050
72 #define TO_LPRXRDY(x) UPDATE(x, 15, 0)
73 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054
74 #define TO_LPTXRDY(x) UPDATE(x, 15, 0)
75 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058
76 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0)
77 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c
78 #define TO_LPTXULPS(x) UPDATE(x, 15, 0)
79 #define DSI2_TIMEOUT_BTA_CFG 0x60
80 #define TO_BTA(x) UPDATE(x, 15, 0)
81
82 #define DSI2_PHY_MODE_CFG 0x0100
83 #define PPI_WIDTH(x) UPDATE(x, 9, 8)
84 #define PHY_LANES(x) UPDATE(x - 1, 5, 4)
85 #define PHY_TYPE(x) UPDATE(x, 0, 0)
86 #define DSI2_PHY_CLK_CFG 0X0104
87 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8)
88 #define CLK_TYPE_MASK BIT(0)
89 #define NON_CONTINUOUS_CLK BIT(0)
90 #define CONTIUOUS_CLK 0
91 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c
92 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0)
93 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114
94 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0)
95 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c
96 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0)
97 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124
98 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0)
99 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c
100 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0)
101
102 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134
103 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0)
104 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C
105 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0)
106
107 #define DSI2_DSI_GENERAL_CFG 0x0200
108 #define BTA_EN BIT(1)
109 #define EOTP_TX_EN BIT(0)
110 #define DSI2_DSI_VCID_CFG 0x0204
111 #define TX_VCID(x) UPDATE(x, 1, 0)
112 #define DSI2_DSI_SCRAMBLING_CFG 0x0208
113 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16)
114 #define SCRAMBLING_EN BIT(0)
115 #define DSI2_DSI_VID_TX_CFG 0x020c
116 #define LPDT_DISPLAY_CMD_EN BIT(20)
117 #define BLK_VFP_HS_EN BIT(14)
118 #define BLK_VBP_HS_EN BIT(13)
119 #define BLK_VSA_HS_EN BIT(12)
120 #define BLK_HFP_HS_EN BIT(6)
121 #define BLK_HBP_HS_EN BIT(5)
122 #define BLK_HSA_HS_EN BIT(4)
123 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0)
124 #define DSI2_CRI_TX_HDR 0x02c0
125 #define CMD_TX_MODE(x) UPDATE(x, 24, 24)
126 #define DSI2_CRI_TX_PLD 0x02c4
127 #define DSI2_CRI_RX_HDR 0x02c8
128 #define DSI2_CRI_RX_PLD 0x02cc
129
130 #define DSI2_IPI_COLOR_MAN_CFG 0x0300
131 #define IPI_DEPTH(x) UPDATE(x, 7, 4)
132 #define IPI_DEPTH_5_6_5_BITS 0x02
133 #define IPI_DEPTH_6_BITS 0x03
134 #define IPI_DEPTH_8_BITS 0x05
135 #define IPI_DEPTH_10_BITS 0x06
136 #define IPI_FORMAT(x) UPDATE(x, 3, 0)
137 #define IPI_FORMAT_RGB 0x0
138 #define IPI_FORMAT_DSC 0x0b
139 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304
140 #define VID_HSA_TIME(x) UPDATE(x, 29, 0)
141 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c
142 #define VID_HBP_TIME(x) UPDATE(x, 29, 0)
143 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314
144 #define VID_HACT_TIME(x) UPDATE(x, 29, 0)
145 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c
146 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0)
147 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324
148 #define VID_VSA_LINES(x) UPDATE(x, 9, 0)
149 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C
150 #define VID_VBP_LINES(x) UPDATE(x, 9, 0)
151 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334
152 #define VID_VACT_LINES(x) UPDATE(x, 13, 0)
153 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C
154 #define VID_VFP_LINES(x) UPDATE(x, 9, 0)
155 #define DSI2_IPI_PIX_PKT_CFG 0x0344
156 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0)
157
158 #define DSI2_INT_ST_PHY 0x0400
159 #define DSI2_INT_MASK_PHY 0x0404
160 #define DSI2_INT_ST_TO 0x0410
161 #define DSI2_INT_MASK_TO 0x0414
162 #define DSI2_INT_ST_ACK 0x0420
163 #define DSI2_INT_MASK_ACK 0x0424
164 #define DSI2_INT_ST_IPI 0x0430
165 #define DSI2_INT_MASK_IPI 0x0434
166 #define DSI2_INT_ST_FIFO 0x0440
167 #define DSI2_INT_MASK_FIFO 0x0444
168 #define DSI2_INT_ST_PRI 0x0450
169 #define DSI2_INT_MASK_PRI 0x0454
170 #define DSI2_INT_ST_CRI 0x0460
171 #define DSI2_INT_MASK_CRI 0x0464
172 #define DSI2_INT_FORCE_CRI 0x0468
173 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI
174
175 #define MODE_STATUS_TIMEOUT_US 10000
176 #define CMD_PKT_STATUS_TIMEOUT_US 20000
177 #define PSEC_PER_SEC 1000000000000LL
178
179 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb))
180
181 enum vid_mode_type {
182 VID_MODE_TYPE_NON_BURST_SYNC_PULSES,
183 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS,
184 VID_MODE_TYPE_BURST,
185 };
186
187 enum mode_ctrl {
188 IDLE_MODE,
189 AUTOCALC_MODE,
190 COMMAND_MODE,
191 VIDEO_MODE,
192 DATA_STREAM_MODE,
193 VIDE_TEST_MODE,
194 DATA_STREAM_TEST_MODE,
195 };
196
197 enum grf_reg_fields {
198 TXREQCLKHS_EN,
199 GATING_EN,
200 IPI_SHUTDN,
201 IPI_COLORM,
202 IPI_COLOR_DEPTH,
203 IPI_FORMAT,
204 MAX_FIELDS,
205 };
206
207 enum phy_type {
208 DPHY,
209 CPHY,
210 };
211
212 enum ppi_width {
213 PPI_WIDTH_8_BITS,
214 PPI_WIDTH_16_BITS,
215 PPI_WIDTH_32_BITS,
216 };
217
218 struct cmd_header {
219 u8 cmd_type;
220 u8 delay;
221 u8 payload_length;
222 };
223
224 struct dw_mipi_dsi2_plat_data {
225 const u32 *dsi0_grf_reg_fields;
226 const u32 *dsi1_grf_reg_fields;
227 unsigned long long dphy_max_bit_rate_per_lane;
228 unsigned long long cphy_max_symbol_rate_per_lane;
229
230 };
231
232 struct dw_mipi_dsi2 {
233 struct drm_encoder encoder;
234 struct drm_connector connector;
235 struct drm_bridge *bridge;
236 struct mipi_dsi_host host;
237 struct drm_panel *panel;
238 struct drm_display_mode mode;
239 struct device *dev;
240 struct device_node *client;
241 struct regmap *grf;
242 struct clk *pclk;
243 struct clk *sys_clk;
244 bool phy_enabled;
245 struct phy *dcphy;
246 union phy_configure_opts phy_opts;
247
248 bool c_option;
249 bool scrambling_en;
250 unsigned int slice_width;
251 unsigned int slice_height;
252 bool dsc_enable;
253 u8 version_major;
254 u8 version_minor;
255
256 struct drm_dsc_picture_parameter_set *pps;
257 struct regmap *regmap;
258 struct reset_control *apb_rst;
259 int irq;
260 int id;
261
262 /* dual-channel */
263 struct dw_mipi_dsi2 *master;
264 struct dw_mipi_dsi2 *slave;
265 bool data_swap;
266
267 unsigned int lane_hs_rate; /* Mbps or Msps per lane */
268 u32 channel;
269 u32 lanes;
270 u32 format;
271 unsigned long mode_flags;
272
273 const struct dw_mipi_dsi2_plat_data *pdata;
274 struct rockchip_drm_sub_dev sub_dev;
275
276 struct gpio_desc *te_gpio;
277 };
278
host_to_dsi2(struct mipi_dsi_host * host)279 static inline struct dw_mipi_dsi2 *host_to_dsi2(struct mipi_dsi_host *host)
280 {
281 return container_of(host, struct dw_mipi_dsi2, host);
282 }
283
con_to_dsi2(struct drm_connector * con)284 static inline struct dw_mipi_dsi2 *con_to_dsi2(struct drm_connector *con)
285 {
286 return container_of(con, struct dw_mipi_dsi2, connector);
287 }
288
encoder_to_dsi2(struct drm_encoder * encoder)289 static inline struct dw_mipi_dsi2 *encoder_to_dsi2(struct drm_encoder *encoder)
290 {
291 return container_of(encoder, struct dw_mipi_dsi2, encoder);
292 }
293
grf_field_write(struct dw_mipi_dsi2 * dsi2,enum grf_reg_fields index,unsigned int val)294 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index,
295 unsigned int val)
296 {
297 const u32 field = dsi2->id ?
298 dsi2->pdata->dsi1_grf_reg_fields[index] :
299 dsi2->pdata->dsi0_grf_reg_fields[index];
300 u16 reg;
301 u8 msb, lsb;
302
303 if (!field)
304 return;
305
306 reg = (field >> 16) & 0xffff;
307 lsb = (field >> 8) & 0xff;
308 msb = (field >> 0) & 0xff;
309
310 regmap_write(dsi2->grf, reg, (val << lsb) | (GENMASK(msb, lsb) << 16));
311 }
312
cri_fifos_wait_avail(struct dw_mipi_dsi2 * dsi2)313 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2)
314 {
315 u32 sts, mask;
316 int ret;
317
318 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY;
319 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_CORE_STATUS, sts,
320 !(sts & mask), 0,
321 CMD_PKT_STATUS_TIMEOUT_US);
322 if (ret < 0) {
323 DRM_DEV_ERROR(dsi2->dev, "command interface is busy\n");
324 return ret;
325 }
326
327 return 0;
328 }
329
dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 * dsi2,bool enable)330 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable)
331 {
332 if (enable) {
333 regmap_write(dsi2->regmap, DSI2_INT_MASK_PHY, 0x1);
334 regmap_write(dsi2->regmap, DSI2_INT_MASK_TO, 0xf);
335 regmap_write(dsi2->regmap, DSI2_INT_MASK_ACK, 0x1);
336 regmap_write(dsi2->regmap, DSI2_INT_MASK_IPI, 0x1);
337 regmap_write(dsi2->regmap, DSI2_INT_MASK_FIFO, 0x1);
338 regmap_write(dsi2->regmap, DSI2_INT_MASK_PRI, 0x1);
339 regmap_write(dsi2->regmap, DSI2_INT_MASK_CRI, 0x1);
340 } else {
341 regmap_write(dsi2->regmap, DSI2_INT_MASK_PHY, 0x0);
342 regmap_write(dsi2->regmap, DSI2_INT_MASK_TO, 0x0);
343 regmap_write(dsi2->regmap, DSI2_INT_MASK_ACK, 0x0);
344 regmap_write(dsi2->regmap, DSI2_INT_MASK_IPI, 0x0);
345 regmap_write(dsi2->regmap, DSI2_INT_MASK_FIFO, 0x0);
346 regmap_write(dsi2->regmap, DSI2_INT_MASK_PRI, 0x0);
347 regmap_write(dsi2->regmap, DSI2_INT_MASK_CRI, 0x0);
348 };
349 }
350
mipi_dcphy_power_on(struct dw_mipi_dsi2 * dsi2)351 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2)
352 {
353 if (dsi2->phy_enabled)
354 return;
355
356 if (dsi2->dcphy)
357 phy_power_on(dsi2->dcphy);
358
359 dsi2->phy_enabled = true;
360 }
361
mipi_dcphy_power_off(struct dw_mipi_dsi2 * dsi2)362 static void mipi_dcphy_power_off(struct dw_mipi_dsi2 *dsi2)
363 {
364 if (!dsi2->phy_enabled)
365 return;
366
367 if (dsi2->dcphy)
368 phy_power_off(dsi2->dcphy);
369
370 dsi2->phy_enabled = false;
371 }
372
dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 * dsi2)373 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2)
374 {
375 u32 val = 0, mode;
376 int ret;
377
378 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
379 val |= VID_MODE_TYPE_BURST;
380 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
381 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
382
383 else
384 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
385
386 regmap_write(dsi2->regmap, DSI2_DSI_VID_TX_CFG, val);
387
388
389 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, VIDEO_MODE);
390 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS,
391 mode, mode & VIDEO_MODE,
392 1000, MODE_STATUS_TIMEOUT_US);
393 if (ret < 0)
394 dev_err(dsi2->dev, "failed to enter video mode\n");
395 }
396
dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 * dsi2)397 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2)
398 {
399 u32 mode;
400 int ret;
401
402 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, DATA_STREAM_MODE);
403 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS,
404 mode, mode & DATA_STREAM_MODE,
405 1000, MODE_STATUS_TIMEOUT_US);
406 if (ret < 0)
407 dev_err(dsi2->dev, "failed to enter data stream mode\n");
408 }
409
dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 * dsi2)410 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2)
411 {
412 u32 mode;
413 int ret;
414
415 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, COMMAND_MODE);
416 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS,
417 mode, mode & COMMAND_MODE,
418 1000, MODE_STATUS_TIMEOUT_US);
419 if (ret < 0)
420 dev_err(dsi2->dev, "failed to enter data stream mode\n");
421 }
422
dw_mipi_dsi2_disable(struct dw_mipi_dsi2 * dsi2)423 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2)
424 {
425 regmap_write(dsi2->regmap, DSI2_IPI_PIX_PKT_CFG, 0);
426 dw_mipi_dsi2_set_cmd_mode(dsi2);
427
428 if (dsi2->slave)
429 dw_mipi_dsi2_disable(dsi2->slave);
430 }
431
dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 * dsi2)432 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2)
433 {
434 dw_mipi_dsi2_irq_enable(dsi2, 0);
435 regmap_write(dsi2->regmap, DSI2_PWR_UP, RESET);
436 mipi_dcphy_power_off(dsi2);
437 pm_runtime_put(dsi2->dev);
438
439 if (dsi2->slave)
440 dw_mipi_dsi2_post_disable(dsi2->slave);
441 }
442
dw_mipi_dsi2_encoder_disable(struct drm_encoder * encoder)443 static void dw_mipi_dsi2_encoder_disable(struct drm_encoder *encoder)
444 {
445 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
446
447 if (dsi2->panel)
448 drm_panel_disable(dsi2->panel);
449
450 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO))
451 vop2_standby(encoder->crtc, 1);
452
453 dw_mipi_dsi2_disable(dsi2);
454
455 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO))
456 vop2_standby(encoder->crtc, 0);
457
458 if (dsi2->panel)
459 drm_panel_unprepare(dsi2->panel);
460
461 dw_mipi_dsi2_post_disable(dsi2);
462 }
463
dw_mipi_dsi2_set_lane_rate(struct dw_mipi_dsi2 * dsi2)464 static void dw_mipi_dsi2_set_lane_rate(struct dw_mipi_dsi2 *dsi2)
465 {
466 struct device *dev = dsi2->dev;
467 const struct drm_display_mode *mode = &dsi2->mode;
468 unsigned long max_lane_rate;
469 unsigned long lane_rate, hs_clk_rate, target_pclk;
470 unsigned int value;
471 int bpp, lanes;
472 u64 tmp;
473
474 max_lane_rate = (dsi2->c_option) ?
475 dsi2->pdata->cphy_max_symbol_rate_per_lane :
476 dsi2->pdata->dphy_max_bit_rate_per_lane;
477
478 lanes = (dsi2->slave || dsi2->master) ? dsi2->lanes * 2 : dsi2->lanes;
479 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format);
480 if (bpp < 0)
481 bpp = 24;
482
483 /* optional override of the desired bandwidth */
484 if (!of_property_read_u32(dev->of_node, "rockchip,lane-rate", &value)) {
485 lane_rate = value * USEC_PER_SEC;
486 } else {
487 tmp = (u64)mode->clock * 1000 * bpp;
488 do_div(tmp, lanes);
489
490 /*
491 * Multiple bits are encoded into each symbol epoch,
492 * the data rate is ~2.28x the symbol rate.
493 */
494 if (dsi2->c_option)
495 tmp = DIV_ROUND_CLOSEST_ULL(tmp * 100, 228);
496
497 /* take 1 / 0.9, since Mbps must big than bandwidth of RGB */
498 tmp *= 10;
499 do_div(tmp, 9);
500
501 if (tmp > max_lane_rate)
502 lane_rate = max_lane_rate;
503 else
504 lane_rate = tmp;
505 }
506
507 target_pclk = DIV_ROUND_CLOSEST_ULL(lane_rate * lanes, bpp);
508 phy_mipi_dphy_get_default_config(target_pclk, bpp, lanes,
509 &dsi2->phy_opts.mipi_dphy);
510
511 if (dsi2->dcphy)
512 if (!dsi2->c_option)
513 phy_set_mode(dsi2->dcphy, PHY_MODE_MIPI_DPHY);
514
515 phy_configure(dsi2->dcphy, &dsi2->phy_opts);
516 hs_clk_rate = dsi2->phy_opts.mipi_dphy.hs_clk_rate;
517 dsi2->lane_hs_rate = DIV_ROUND_UP(hs_clk_rate, USEC_PER_SEC);
518 }
519
dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 * dsi2)520 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2)
521 {
522 if (dsi2->apb_rst) {
523 reset_control_assert(dsi2->apb_rst);
524 usleep_range(10, 20);
525 reset_control_deassert(dsi2->apb_rst);
526 }
527
528 regmap_write(dsi2->regmap, DSI2_SOFT_RESET, 0x0);
529 udelay(100);
530 regmap_write(dsi2->regmap, DSI2_SOFT_RESET,
531 SYS_RSTN | PHY_RSTN | IPI_RSTN);
532
533 }
534
dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 * dsi2)535 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2)
536 {
537 u32 val = 0;
538
539 /* PPI width is fixed to 16 bits in DCPHY */
540 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes);
541 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY);
542 regmap_write(dsi2->regmap, DSI2_PHY_MODE_CFG, val);
543 }
544
dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 * dsi2)545 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2)
546 {
547 u32 sys_clk, esc_clk_div;
548 u32 val = 0;
549
550 /*
551 * clk_type should be NON_CONTINUOUS_CLK before
552 * initial deskew calibration be sent.
553 */
554 val |= NON_CONTINUOUS_CLK;
555
556 /* The Escape clock ranges from 1MHz to 20MHz. */
557 sys_clk = clk_get_rate(dsi2->sys_clk) / USEC_PER_SEC;
558 esc_clk_div = DIV_ROUND_UP(sys_clk, 10 * 2);
559 val |= PHY_LPTX_CLK_DIV(esc_clk_div);
560
561 regmap_write(dsi2->regmap, DSI2_PHY_CLK_CFG, val);
562 }
563
dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 * dsi2)564 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2)
565 {
566 struct drm_display_mode *mode = &dsi2->mode;
567 u32 sys_clk = clk_get_rate(dsi2->sys_clk) / MSEC_PER_SEC;
568 u64 pixel_clk, ipi_clk, phy_hsclk;
569 u64 tmp;
570
571 /*
572 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed
573 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio
574 * high speed symbol rate.
575 */
576 if (dsi2->c_option)
577 phy_hsclk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 7);
578 else
579 phy_hsclk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 16);
580
581 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */
582 pixel_clk = mode->clock;
583 ipi_clk = pixel_clk / 4;
584
585 tmp = DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, ipi_clk);
586 regmap_write(dsi2->regmap, DSI2_PHY_IPI_RATIO_MAN_CFG,
587 PHY_IPI_RATIO(tmp));
588
589 /*
590 * SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / MIPI_DCPHY_HSCLK_Freq
591 */
592 tmp = DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, sys_clk);
593 regmap_write(dsi2->regmap, DSI2_PHY_SYS_RATIO_MAN_CFG,
594 PHY_SYS_RATIO(tmp));
595 }
596
dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 * dsi2)597 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2)
598 {
599 struct phy_configure_opts_mipi_dphy *cfg = &dsi2->phy_opts.mipi_dphy;
600 unsigned long long tmp, ui;
601 unsigned long long hstx_clk;
602
603 hstx_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * USEC_PER_SEC, 16);
604
605 ui = ALIGN(PSEC_PER_SEC, hstx_clk);
606 do_div(ui, hstx_clk);
607
608 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */
609 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero;
610 tmp = DIV_ROUND_CLOSEST_ULL(tmp << 16, ui);
611 regmap_write(dsi2->regmap, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp));
612
613 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */
614 tmp = cfg->hs_trail + cfg->hs_exit;
615 tmp = DIV_ROUND_CLOSEST_ULL(tmp << 16, ui);
616 regmap_write(dsi2->regmap, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp));
617 }
618
dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 * dsi2)619 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2)
620 {
621 dw_mipi_dsi2_phy_mode_cfg(dsi2);
622 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2);
623 dw_mipi_dsi2_phy_ratio_cfg(dsi2);
624 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2);
625
626 /* phy configuration 8 - 10 */
627 }
628
dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 * dsi2)629 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2)
630 {
631 u32 val;
632
633 val = BTA_EN | EOTP_TX_EN;
634
635 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET)
636 val &= ~EOTP_TX_EN;
637
638 regmap_write(dsi2->regmap, DSI2_DSI_GENERAL_CFG, val);
639 regmap_write(dsi2->regmap, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel));
640
641 if (dsi2->scrambling_en)
642 regmap_write(dsi2->regmap, DSI2_DSI_SCRAMBLING_CFG,
643 SCRAMBLING_EN);
644
645 val = 0;
646 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)
647 val |= BLK_HFP_HS_EN;
648
649 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)
650 val |= BLK_HBP_HS_EN;
651
652 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)
653 val |= BLK_HSA_HS_EN;
654
655 regmap_write(dsi2->regmap, DSI2_DSI_VID_TX_CFG, val);
656
657 /* configure the maximum return packet size that periphera can send */
658 }
659
dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 * dsi2)660 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2)
661 {
662 u32 val, color_depth;
663
664 switch (dsi2->format) {
665 case MIPI_DSI_FMT_RGB666:
666 case MIPI_DSI_FMT_RGB666_PACKED:
667 color_depth = IPI_DEPTH_6_BITS;
668 break;
669 case MIPI_DSI_FMT_RGB565:
670 color_depth = IPI_DEPTH_5_6_5_BITS;
671 break;
672 case MIPI_DSI_FMT_RGB888:
673 default:
674 color_depth = IPI_DEPTH_8_BITS;
675 break;
676 }
677
678 val = IPI_DEPTH(color_depth) |
679 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB);
680 regmap_write(dsi2->regmap, DSI2_IPI_COLOR_MAN_CFG, val);
681 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth);
682
683 if (dsi2->dsc_enable)
684 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC);
685 }
686
dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 * dsi2)687 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2)
688 {
689 struct drm_display_mode *mode = &dsi2->mode;
690 u32 hline, hsa, hbp, hact;
691 u64 hline_time, hsa_time, hbp_time, hact_time, tmp;
692 u32 vact, vsa, vfp, vbp;
693 u32 pixel_clk, phy_hs_clk;
694 u16 val;
695
696 if (dsi2->slave || dsi2->master)
697 val = mode->hdisplay / 2;
698 else
699 val = mode->hdisplay;
700
701 regmap_write(dsi2->regmap, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val));
702
703 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2);
704
705 /*
706 * if the controller is intended to operate in data stream mode,
707 * no more steps are required.
708 */
709 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO))
710 return;
711
712 vact = mode->vdisplay;
713 vsa = mode->vsync_end - mode->vsync_start;
714 vfp = mode->vsync_start - mode->vdisplay;
715 vbp = mode->vtotal - mode->vsync_end;
716 hact = mode->hdisplay;
717 hsa = mode->hsync_end - mode->hsync_start;
718 hbp = mode->htotal - mode->hsync_end;
719 hline = mode->htotal;
720
721 pixel_clk = mode->clock / 1000;
722
723 if (dsi2->c_option)
724 phy_hs_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate, 7);
725 else
726 phy_hs_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate, 16);
727
728 tmp = hsa * phy_hs_clk;
729 hsa_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk);
730 regmap_write(dsi2->regmap, DSI2_IPI_VID_HSA_MAN_CFG,
731 VID_HSA_TIME(hsa_time));
732
733 tmp = hbp * phy_hs_clk;
734 hbp_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk);
735 regmap_write(dsi2->regmap, DSI2_IPI_VID_HBP_MAN_CFG,
736 VID_HBP_TIME(hbp_time));
737
738 tmp = hact * phy_hs_clk;
739 hact_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk);
740 regmap_write(dsi2->regmap, DSI2_IPI_VID_HACT_MAN_CFG,
741 VID_HACT_TIME(hact_time));
742
743 tmp = hline * phy_hs_clk;
744 hline_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk);
745 regmap_write(dsi2->regmap, DSI2_IPI_VID_HLINE_MAN_CFG,
746 VID_HLINE_TIME(hline_time));
747
748 regmap_write(dsi2->regmap, DSI2_IPI_VID_VSA_MAN_CFG,
749 VID_VSA_LINES(vsa));
750 regmap_write(dsi2->regmap, DSI2_IPI_VID_VBP_MAN_CFG,
751 VID_VBP_LINES(vbp));
752 regmap_write(dsi2->regmap, DSI2_IPI_VID_VACT_MAN_CFG,
753 VID_VACT_LINES(vact));
754 regmap_write(dsi2->regmap, DSI2_IPI_VID_VFP_MAN_CFG,
755 VID_VFP_LINES(vfp));
756 }
757
758 static void
dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 * dsi2,u32 mode)759 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode)
760 {
761 /*
762 * select controller work in Manual mode
763 * Manual: MANUAL_MODE_EN
764 * Automatic: 0
765 */
766 regmap_write(dsi2->regmap, MANUAL_MODE_CFG, mode);
767 }
768
dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 * dsi2)769 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2)
770 {
771 pm_runtime_get_sync(dsi2->dev);
772
773 dw_mipi_dsi2_host_softrst(dsi2);
774 regmap_write(dsi2->regmap, DSI2_PWR_UP, RESET);
775
776 /* there may be some timeout registers may be configured if desired */
777
778 dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN);
779 dw_mipi_dsi2_phy_init(dsi2);
780 dw_mipi_dsi2_tx_option_set(dsi2);
781 dw_mipi_dsi2_irq_enable(dsi2, 1);
782 mipi_dcphy_power_on(dsi2);
783
784 /*
785 * initial deskew calibration is send after phy_power_on,
786 * then we can configure clk_type.
787 */
788 if (!(dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
789 regmap_update_bits(dsi2->regmap, DSI2_PHY_CLK_CFG,
790 CLK_TYPE_MASK, CONTIUOUS_CLK);
791
792 regmap_write(dsi2->regmap, DSI2_PWR_UP, POWER_UP);
793 dw_mipi_dsi2_set_cmd_mode(dsi2);
794
795 if (dsi2->slave)
796 dw_mipi_dsi2_pre_enable(dsi2->slave);
797 }
798
dw_mipi_dsi2_enable(struct dw_mipi_dsi2 * dsi2)799 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2)
800 {
801 dw_mipi_dsi2_ipi_set(dsi2);
802
803 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)
804 dw_mipi_dsi2_set_vid_mode(dsi2);
805 else
806 dw_mipi_dsi2_set_data_stream_mode(dsi2);
807
808 if (dsi2->slave)
809 dw_mipi_dsi2_enable(dsi2->slave);
810 }
811
dw_mipi_dsi2_encoder_enable(struct drm_encoder * encoder)812 static void dw_mipi_dsi2_encoder_enable(struct drm_encoder *encoder)
813 {
814 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
815
816 if (dsi2->dcphy)
817 dw_mipi_dsi2_set_lane_rate(dsi2);
818
819 if (dsi2->slave && dsi2->slave->dcphy)
820 dw_mipi_dsi2_set_lane_rate(dsi2->slave);
821
822 dw_mipi_dsi2_pre_enable(dsi2);
823
824 if (dsi2->panel)
825 drm_panel_prepare(dsi2->panel);
826
827 dw_mipi_dsi2_enable(dsi2);
828
829 if (dsi2->panel)
830 drm_panel_enable(dsi2->panel);
831
832 DRM_DEV_INFO(dsi2->dev, "final DSI-Link bandwidth: %u x %d %s\n",
833 dsi2->lane_hs_rate,
834 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes,
835 dsi2->c_option ? "Msps" : "Mbps");
836 }
837
838 static int
dw_mipi_dsi2_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)839 dw_mipi_dsi2_encoder_atomic_check(struct drm_encoder *encoder,
840 struct drm_crtc_state *crtc_state,
841 struct drm_connector_state *conn_state)
842 {
843
844 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
845 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
846 struct drm_connector *connector = conn_state->connector;
847 struct drm_display_info *info = &connector->display_info;
848
849 switch (dsi2->format) {
850 case MIPI_DSI_FMT_RGB888:
851 s->output_mode = ROCKCHIP_OUT_MODE_P888;
852 break;
853 case MIPI_DSI_FMT_RGB666:
854 s->output_mode = ROCKCHIP_OUT_MODE_P666;
855 break;
856 case MIPI_DSI_FMT_RGB565:
857 s->output_mode = ROCKCHIP_OUT_MODE_P565;
858 break;
859 default:
860 WARN_ON(1);
861 return -EINVAL;
862 }
863
864 if (info->num_bus_formats)
865 s->bus_format = info->bus_formats[0];
866 else
867 s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
868
869 s->output_type = DRM_MODE_CONNECTOR_DSI;
870 s->output_if = dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0;
871 s->bus_flags = info->bus_flags;
872
873 s->tv_state = &conn_state->tv;
874 s->color_space = V4L2_COLORSPACE_DEFAULT;
875
876 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) {
877 s->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE;
878 s->hold_mode = true;
879 }
880
881 if (dsi2->slave) {
882 s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE;
883 if (dsi2->data_swap)
884 s->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP;
885
886 s->output_if |= VOP_OUTPUT_IF_MIPI1;
887 }
888
889 if (dsi2->dsc_enable) {
890 s->dsc_enable = 1;
891 s->dsc_sink_cap.version_major = dsi2->version_major;
892 s->dsc_sink_cap.version_minor = dsi2->version_minor;
893 s->dsc_sink_cap.slice_width = dsi2->slice_width;
894 s->dsc_sink_cap.slice_height = dsi2->slice_height;
895 /* only can support rgb888 panel now */
896 s->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4;
897 s->dsc_sink_cap.native_420 = 0;
898
899 memcpy(&s->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set));
900 }
901
902 return 0;
903 }
904
905 static void
dw_mipi_dsi2_encoder_atomic_mode_set(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * connector_state)906 dw_mipi_dsi2_encoder_atomic_mode_set(struct drm_encoder *encoder,
907 struct drm_crtc_state *crtc_state,
908 struct drm_connector_state *connector_state)
909 {
910 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
911
912 drm_mode_copy(&dsi2->mode, &crtc_state->adjusted_mode);
913 if (dsi2->slave)
914 drm_mode_copy(&dsi2->slave->mode, &crtc_state->adjusted_mode);
915 }
916
dw_mipi_dsi2_loader_protect(struct dw_mipi_dsi2 * dsi2,bool on)917 static void dw_mipi_dsi2_loader_protect(struct dw_mipi_dsi2 *dsi2, bool on)
918 {
919 if (on) {
920 pm_runtime_get_sync(dsi2->dev);
921 phy_init(dsi2->dcphy);
922 dsi2->phy_enabled = true;
923 if (dsi2->dcphy)
924 dsi2->dcphy->power_count++;
925 } else {
926 pm_runtime_put(dsi2->dev);
927 phy_exit(dsi2->dcphy);
928 dsi2->phy_enabled = false;
929 if (dsi2->dcphy)
930 dsi2->dcphy->power_count--;
931 }
932
933 if (dsi2->slave)
934 dw_mipi_dsi2_loader_protect(dsi2->slave, on);
935 }
936
dw_mipi_dsi2_encoder_loader_protect(struct drm_encoder * encoder,bool on)937 static void dw_mipi_dsi2_encoder_loader_protect(struct drm_encoder *encoder,
938 bool on)
939 {
940 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
941
942 if (dsi2->panel)
943 panel_simple_loader_protect(dsi2->panel);
944
945 dw_mipi_dsi2_loader_protect(dsi2, on);
946 }
947
948 static const struct drm_encoder_helper_funcs
949 dw_mipi_dsi2_encoder_helper_funcs = {
950 .enable = dw_mipi_dsi2_encoder_enable,
951 .disable = dw_mipi_dsi2_encoder_disable,
952 .atomic_check = dw_mipi_dsi2_encoder_atomic_check,
953 .atomic_mode_set = dw_mipi_dsi2_encoder_atomic_mode_set,
954 };
955
dw_mipi_dsi2_connector_get_modes(struct drm_connector * connector)956 static int dw_mipi_dsi2_connector_get_modes(struct drm_connector *connector)
957 {
958 struct dw_mipi_dsi2 *dsi2 = con_to_dsi2(connector);
959
960 return drm_panel_get_modes(dsi2->panel, connector);
961 }
962
dw_mipi_dsi2_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)963 static int dw_mipi_dsi2_connector_mode_valid(struct drm_connector *connector,
964 struct drm_display_mode *mode)
965 {
966 struct videomode vm;
967
968 drm_display_mode_to_videomode(mode, &vm);
969
970 /*
971 * the minimum region size (HSA,HBP,HACT,HFP) is 4 pixels
972 * which is the ip known issues and limitations.
973 */
974 if (!(vm.hsync_len < 4 || vm.hback_porch < 4 ||
975 vm.hfront_porch < 4 || vm.hactive < 4))
976 return MODE_OK;
977
978 if (vm.hsync_len < 4)
979 vm.hsync_len = 4;
980
981 if (vm.hback_porch < 4)
982 vm.hback_porch = 4;
983
984 if (vm.hfront_porch < 4)
985 vm.hfront_porch = 4;
986
987 if (vm.hactive < 4)
988 vm.hactive = 4;
989
990 drm_display_mode_from_videomode(&vm, mode);
991
992 return MODE_OK;
993 }
994
995 static struct drm_connector_helper_funcs dw_mipi_dsi2_connector_helper_funcs = {
996 .get_modes = dw_mipi_dsi2_connector_get_modes,
997 .mode_valid = dw_mipi_dsi2_connector_mode_valid,
998 };
999
dw_mipi_dsi2_drm_connector_destroy(struct drm_connector * connector)1000 static void dw_mipi_dsi2_drm_connector_destroy(struct drm_connector *connector)
1001 {
1002 drm_connector_unregister(connector);
1003 drm_connector_cleanup(connector);
1004 }
1005
1006 static const struct drm_connector_funcs dw_mipi_dsi2_atomic_connector_funcs = {
1007 .fill_modes = drm_helper_probe_single_connector_modes,
1008 .destroy = dw_mipi_dsi2_drm_connector_destroy,
1009 .reset = drm_atomic_helper_connector_reset,
1010 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1011 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1012 };
1013
dw_mipi_dsi2_dual_channel_probe(struct dw_mipi_dsi2 * dsi2)1014 static int dw_mipi_dsi2_dual_channel_probe(struct dw_mipi_dsi2 *dsi2)
1015 {
1016 struct device_node *np;
1017 struct platform_device *secondary;
1018
1019 np = of_parse_phandle(dsi2->dev->of_node, "rockchip,dual-channel", 0);
1020 if (np) {
1021 dsi2->data_swap = of_property_read_bool(dsi2->dev->of_node,
1022 "rockchip,data-swap");
1023 secondary = of_find_device_by_node(np);
1024 dsi2->slave = platform_get_drvdata(secondary);
1025 of_node_put(np);
1026
1027 if (!dsi2->slave)
1028 return -EPROBE_DEFER;
1029
1030 dsi2->slave->master = dsi2;
1031 dsi2->lanes /= 2;
1032
1033 dsi2->slave->lanes = dsi2->lanes;
1034 dsi2->slave->channel = dsi2->channel;
1035 dsi2->slave->format = dsi2->format;
1036 dsi2->slave->mode_flags = dsi2->mode_flags;
1037 }
1038
1039 return 0;
1040 }
1041
dw_mipi_dsi2_te_irq_handler(int irq,void * dev_id)1042 static irqreturn_t dw_mipi_dsi2_te_irq_handler(int irq, void *dev_id)
1043 {
1044 struct dw_mipi_dsi2 *dsi2 = (struct dw_mipi_dsi2 *)dev_id;
1045 struct drm_encoder *encoder = &dsi2->encoder;
1046
1047 rockchip_drm_te_handle(encoder->crtc);
1048
1049 return IRQ_HANDLED;
1050 }
1051
dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 * dsi2,struct drm_panel * panel,struct drm_bridge * bridge)1052 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2,
1053 struct drm_panel *panel,
1054 struct drm_bridge *bridge)
1055 {
1056 struct drm_dsc_picture_parameter_set *pps = NULL;
1057 struct device_node *np = NULL;
1058 struct cmd_header *header;
1059 const void *data;
1060 char *d;
1061 uint8_t *dsc_packed_pps;
1062 int len;
1063
1064 if (!panel && !bridge)
1065 return -ENODEV;
1066
1067 if (panel)
1068 np = panel->dev->of_node;
1069 else
1070 np = bridge->of_node;
1071
1072 dsi2->c_option = of_property_read_bool(np, "phy-c-option");
1073 dsi2->scrambling_en = of_property_read_bool(np, "scrambling-enable");
1074 dsi2->dsc_enable = of_property_read_bool(np, "compressed-data");
1075
1076 if (dsi2->slave) {
1077 dsi2->slave->c_option = dsi2->c_option;
1078 dsi2->slave->scrambling_en = dsi2->scrambling_en;
1079 dsi2->slave->dsc_enable = dsi2->dsc_enable;
1080 }
1081
1082 of_property_read_u32(np, "slice-width", &dsi2->slice_width);
1083 of_property_read_u32(np, "slice-height", &dsi2->slice_height);
1084 of_property_read_u8(np, "version-major", &dsi2->version_major);
1085 of_property_read_u8(np, "version-minor", &dsi2->version_minor);
1086
1087 data = of_get_property(np, "panel-init-sequence", &len);
1088 if (!data)
1089 return -EINVAL;
1090
1091 d = devm_kmemdup(dsi2->dev, data, len, GFP_KERNEL);
1092 if (!d)
1093 return -ENOMEM;
1094
1095 while (len > sizeof(*header)) {
1096 header = (struct cmd_header *)d;
1097 d += sizeof(*header);
1098 len -= sizeof(*header);
1099
1100 if (header->payload_length > len)
1101 return -EINVAL;
1102
1103 if (header->cmd_type == MIPI_DSI_PICTURE_PARAMETER_SET) {
1104 dsc_packed_pps = devm_kmemdup(dsi2->dev, d,
1105 header->payload_length, GFP_KERNEL);
1106 if (!dsc_packed_pps)
1107 return -ENOMEM;
1108
1109 pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps;
1110 break;
1111 }
1112
1113 d += header->payload_length;
1114 len -= header->payload_length;
1115 }
1116
1117 dsi2->pps = pps;
1118
1119 return 0;
1120 }
1121
dw_mipi_dsi2_bind(struct device * dev,struct device * master,void * data)1122 static int dw_mipi_dsi2_bind(struct device *dev, struct device *master,
1123 void *data)
1124 {
1125 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev);
1126 struct drm_device *drm_dev = data;
1127 struct drm_encoder *encoder = &dsi2->encoder;
1128 struct drm_connector *connector = &dsi2->connector;
1129 struct device_node *of_node = dsi2->dev->of_node;
1130 int ret;
1131
1132 ret = dw_mipi_dsi2_dual_channel_probe(dsi2);
1133 if (ret)
1134 return ret;
1135
1136 if (dsi2->master)
1137 return 0;
1138
1139 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
1140 &dsi2->panel, &dsi2->bridge);
1141 if (ret) {
1142 DRM_DEV_ERROR(dev, "Failed to find panel or bridge: %d\n", ret);
1143 return ret;
1144 }
1145
1146 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2, dsi2->panel, dsi2->bridge);
1147 encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm_dev,
1148 of_node);
1149
1150 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI);
1151 if (ret) {
1152 DRM_ERROR("Failed to initialize encoder with drm\n");
1153 return ret;
1154 }
1155
1156 drm_encoder_helper_add(encoder, &dw_mipi_dsi2_encoder_helper_funcs);
1157
1158 if (dsi2->panel) {
1159 ret = drm_connector_init(drm_dev, connector,
1160 &dw_mipi_dsi2_atomic_connector_funcs,
1161 DRM_MODE_CONNECTOR_DSI);
1162 if (ret) {
1163 DRM_DEV_ERROR(dev, "Failed to initialize connector\n");
1164 goto encoder_cleanup;
1165 }
1166
1167 drm_connector_helper_add(connector,
1168 &dw_mipi_dsi2_connector_helper_funcs);
1169 drm_connector_attach_encoder(connector, encoder);
1170 if (ret < 0) {
1171 DRM_DEV_ERROR(dev, "Failed to attach encoder: %d\n", ret);
1172 goto connector_cleanup;
1173 }
1174
1175 dsi2->sub_dev.connector = &dsi2->connector;
1176 dsi2->sub_dev.of_node = dev->of_node;
1177 dsi2->sub_dev.loader_protect = dw_mipi_dsi2_encoder_loader_protect;
1178 rockchip_drm_register_sub_dev(&dsi2->sub_dev);
1179 } else {
1180 dsi2->bridge->driver_private = &dsi2->host;
1181 dsi2->bridge->encoder = encoder;
1182
1183 ret = drm_bridge_attach(encoder, dsi2->bridge, NULL, 0);
1184 if (ret) {
1185 DRM_DEV_ERROR(dev,
1186 "Failed to attach bridge: %d\n", ret);
1187 goto encoder_cleanup;
1188 }
1189
1190 }
1191
1192 pm_runtime_enable(dsi2->dev);
1193 if (dsi2->slave)
1194 pm_runtime_enable(dsi2->slave->dev);
1195
1196 return 0;
1197
1198 connector_cleanup:
1199 connector->funcs->destroy(connector);
1200 encoder_cleanup:
1201 encoder->funcs->destroy(encoder);
1202
1203 return ret;
1204 }
1205
dw_mipi_dsi2_unbind(struct device * dev,struct device * master,void * data)1206 static void dw_mipi_dsi2_unbind(struct device *dev, struct device *master,
1207 void *data)
1208 {
1209 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev);
1210
1211 if (dsi2->sub_dev.connector)
1212 rockchip_drm_unregister_sub_dev(&dsi2->sub_dev);
1213
1214 pm_runtime_disable(dsi2->dev);
1215 if (dsi2->slave)
1216 pm_runtime_disable(dsi2->slave->dev);
1217
1218 dsi2->connector.funcs->destroy(&dsi2->connector);
1219 dsi2->encoder.funcs->destroy(&dsi2->encoder);
1220 }
1221
1222 static const struct component_ops dw_mipi_dsi2_ops = {
1223 .bind = dw_mipi_dsi2_bind,
1224 .unbind = dw_mipi_dsi2_unbind,
1225 };
1226
1227 struct dsi2_irq_data {
1228 u32 offeset;
1229 char *irq_src;
1230 };
1231
1232 static const struct dsi2_irq_data dw_mipi_dsi2_irq_data[] = {
1233 {DSI2_INT_ST_PHY, "int_st_phy"},
1234 {DSI2_INT_ST_TO, "int_st_to"},
1235 {DSI2_INT_ST_ACK, "int_st_ack"},
1236 {DSI2_INT_ST_IPI, "int_st_ipi"},
1237 {DSI2_INT_ST_FIFO, "int_st_fifo"},
1238 {DSI2_INT_ST_PRI, "int_st_pri"},
1239 {DSI2_INT_ST_CRI, "int_st_cri"},
1240 };
1241
dw_mipi_dsi2_irq_handler(int irq,void * dev_id)1242 static irqreturn_t dw_mipi_dsi2_irq_handler(int irq, void *dev_id)
1243 {
1244
1245 struct dw_mipi_dsi2 *dsi2 = dev_id;
1246 u32 int_st;
1247 unsigned int i;
1248
1249 regmap_read(dsi2->regmap, INT_ST_MAIN, &int_st);
1250
1251 for (i = 0; i < ARRAY_SIZE(dw_mipi_dsi2_irq_data); i++)
1252 if (int_st & BIT(i))
1253 DRM_DEV_DEBUG(dsi2->dev, "%s\n",
1254 dw_mipi_dsi2_irq_data[i].irq_src);
1255
1256 return IRQ_HANDLED;
1257 }
1258
1259 static const struct regmap_config dw_mipi_dsi2_regmap_config = {
1260 .name = "host",
1261 .reg_bits = 32,
1262 .val_bits = 32,
1263 .reg_stride = 4,
1264 .fast_io = true,
1265 .max_register = DSI2_MAX_REGISGER,
1266 };
1267
dw_mipi_dsi2_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1268 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host,
1269 struct mipi_dsi_device *device)
1270 {
1271 struct dw_mipi_dsi2 *dsi2 = host_to_dsi2(host);
1272
1273 if (dsi2->master)
1274 return 0;
1275
1276 if (device->lanes < 1 || device->lanes > 8)
1277 return -EINVAL;
1278
1279 dsi2->client = device->dev.of_node;
1280 dsi2->lanes = device->lanes;
1281 dsi2->channel = device->channel;
1282 dsi2->format = device->format;
1283 dsi2->mode_flags = device->mode_flags;
1284
1285 return 0;
1286 }
1287
dw_mipi_dsi2_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1288 static int dw_mipi_dsi2_host_detach(struct mipi_dsi_host *host,
1289 struct mipi_dsi_device *device)
1290 {
1291 return 0;
1292 }
1293
dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 * dsi2,const struct mipi_dsi_msg * msg)1294 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2,
1295 const struct mipi_dsi_msg *msg)
1296 {
1297 u8 *payload = msg->rx_buf;
1298 u8 data_type;
1299 u16 wc;
1300 int i, j, ret, len = msg->rx_len;
1301 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode);
1302 u32 val;
1303
1304 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_CORE_STATUS,
1305 val, val & CRI_RD_DATA_AVAIL,
1306 0, DIV_ROUND_UP(1000000, vrefresh));
1307 if (ret) {
1308 DRM_DEV_ERROR(dsi2->dev, "CRI has no available read data\n");
1309 return ret;
1310 }
1311
1312 regmap_read(dsi2->regmap, DSI2_CRI_RX_HDR, &val);
1313 data_type = val & 0x3f;
1314
1315 if (mipi_dsi_packet_format_is_short(data_type)) {
1316 for (i = 0; i < len && i < 2; i++)
1317 payload[i] = (val >> (8 * (i + 1))) & 0xff;
1318
1319 return 0;
1320 }
1321
1322 wc = (val >> 8) & 0xffff;
1323 /* Receive payload */
1324 for (i = 0; i < len && i < wc; i += 4) {
1325 regmap_read(dsi2->regmap, DSI2_CRI_RX_PLD, &val);
1326 for (j = 0; j < 4 && j + i < len && j + i < wc; j++)
1327 payload[i + j] = val >> (8 * j);
1328 }
1329
1330 return 0;
1331 }
1332
dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 * dsi2,const struct mipi_dsi_msg * msg)1333 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2,
1334 const struct mipi_dsi_msg *msg)
1335 {
1336 struct mipi_dsi_packet packet;
1337 int ret;
1338 u32 val;
1339 u32 mode;
1340
1341 regmap_update_bits(dsi2->regmap, DSI2_DSI_VID_TX_CFG,
1342 LPDT_DISPLAY_CMD_EN,
1343 msg->flags & MIPI_DSI_MSG_USE_LPM ?
1344 LPDT_DISPLAY_CMD_EN : 0);
1345
1346 /* create a packet to the DSI protocol */
1347 ret = mipi_dsi_create_packet(&packet, msg);
1348 if (ret) {
1349 DRM_DEV_ERROR(dsi2->dev, "failed to create packet: %d\n", ret);
1350 return ret;
1351 }
1352
1353 ret = cri_fifos_wait_avail(dsi2);
1354 if (ret)
1355 return ret;
1356
1357 /* Send payload */
1358 while (DIV_ROUND_UP(packet.payload_length, 4)) {
1359 /* check cri interface is not busy */
1360 if (packet.payload_length < 4) {
1361 /* send residu payload */
1362 val = 0;
1363 memcpy(&val, packet.payload, packet.payload_length);
1364 regmap_write(dsi2->regmap, DSI2_CRI_TX_PLD, val);
1365 packet.payload_length = 0;
1366 } else {
1367 val = get_unaligned_le32(packet.payload);
1368 regmap_write(dsi2->regmap, DSI2_CRI_TX_PLD, val);
1369 packet.payload += 4;
1370 packet.payload_length -= 4;
1371 }
1372 }
1373
1374 /* Send packet header */
1375 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0);
1376 val = get_unaligned_le32(packet.header);
1377
1378 regmap_write(dsi2->regmap, DSI2_CRI_TX_HDR, mode | val);
1379
1380 ret = cri_fifos_wait_avail(dsi2);
1381 if (ret)
1382 return ret;
1383
1384 if (msg->rx_len) {
1385 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg);
1386 if (ret < 0)
1387 return ret;
1388 }
1389
1390 if (dsi2->slave)
1391 dw_mipi_dsi2_transfer(dsi2->slave, msg);
1392
1393 return msg->tx_len;
1394 }
1395
dw_mipi_dsi2_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1396 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host,
1397 const struct mipi_dsi_msg *msg)
1398 {
1399 struct dw_mipi_dsi2 *dsi2 = host_to_dsi2(host);
1400
1401 return dw_mipi_dsi2_transfer(dsi2, msg);
1402 }
1403
1404 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = {
1405 .attach = dw_mipi_dsi2_host_attach,
1406 .detach = dw_mipi_dsi2_host_detach,
1407 .transfer = dw_mipi_dsi2_host_transfer,
1408 };
1409
dw_mipi_dsi2_probe(struct platform_device * pdev)1410 static int dw_mipi_dsi2_probe(struct platform_device *pdev)
1411 {
1412 struct device *dev = &pdev->dev;
1413 struct dw_mipi_dsi2 *dsi2;
1414 struct resource *res;
1415 void __iomem *regs;
1416 int id;
1417 int ret;
1418
1419 dsi2 = devm_kzalloc(dev, sizeof(*dsi2), GFP_KERNEL);
1420 if (!dsi2)
1421 return -ENOMEM;
1422
1423 id = of_alias_get_id(dev->of_node, "dsi");
1424 if (id < 0)
1425 id = 0;
1426
1427 dsi2->dev = dev;
1428 dsi2->id = id;
1429 dsi2->pdata = of_device_get_match_data(dev);
1430 platform_set_drvdata(pdev, dsi2);
1431
1432 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1433 regs = devm_ioremap_resource(dev, res);
1434 if (IS_ERR(regs))
1435 return PTR_ERR(regs);
1436
1437 dsi2->irq = platform_get_irq(pdev, 0);
1438 if (dsi2->irq < 0)
1439 return dsi2->irq;
1440
1441 dsi2->pclk = devm_clk_get(dev, "pclk");
1442 if (IS_ERR(dsi2->pclk)) {
1443 ret = PTR_ERR(dsi2->pclk);
1444 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret);
1445 return ret;
1446 }
1447
1448 dsi2->sys_clk = devm_clk_get(dev, "sys_clk");
1449 if (IS_ERR(dsi2->sys_clk)) {
1450 ret = PTR_ERR(dsi2->sys_clk);
1451 DRM_DEV_ERROR(dev, "Unable to get sys_clk: %d\n", ret);
1452 return ret;
1453 }
1454
1455 dsi2->regmap = devm_regmap_init_mmio(dev, regs,
1456 &dw_mipi_dsi2_regmap_config);
1457 if (IS_ERR(dsi2->regmap)) {
1458 ret = PTR_ERR(dsi2->regmap);
1459 DRM_DEV_ERROR(dev, "failed to init register map: %d\n", ret);
1460 return ret;
1461 }
1462
1463 dsi2->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1464 "rockchip,grf");
1465 if (IS_ERR(dsi2->grf)) {
1466 ret = PTR_ERR(dsi2->grf);
1467 DRM_DEV_ERROR(dsi2->dev, "Unable to get grf: %d\n", ret);
1468 return ret;
1469 }
1470
1471 dsi2->apb_rst = devm_reset_control_get(dev, "apb");
1472 if (IS_ERR(dsi2->apb_rst)) {
1473 ret = PTR_ERR(dsi2->apb_rst);
1474 DRM_DEV_ERROR(dev,
1475 "Unable to get reset control: %d\n", ret);
1476 return ret;
1477 }
1478
1479 dsi2->dcphy = devm_phy_optional_get(dev, "dcphy");
1480 if (IS_ERR(dsi2->dcphy)) {
1481 ret = PTR_ERR(dsi2->dcphy);
1482 DRM_DEV_ERROR(dev, "failed to get mipi dcphy: %d\n", ret);
1483 return ret;
1484 }
1485
1486 dsi2->te_gpio = devm_gpiod_get_optional(dsi2->dev, "te", GPIOD_IN);
1487 if (IS_ERR(dsi2->te_gpio))
1488 dsi2->te_gpio = NULL;
1489
1490 if (dsi2->te_gpio) {
1491 ret = devm_request_threaded_irq(dsi2->dev, gpiod_to_irq(dsi2->te_gpio),
1492 NULL, dw_mipi_dsi2_te_irq_handler,
1493 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1494 "PANEL-TE", dsi2);
1495 if (ret) {
1496 dev_err(dsi2->dev, "failed to request TE IRQ: %d\n", ret);
1497 return ret;
1498 }
1499 }
1500
1501 ret = devm_request_irq(dev, dsi2->irq, dw_mipi_dsi2_irq_handler,
1502 IRQF_SHARED, dev_name(dev), dsi2);
1503 if (ret) {
1504 DRM_DEV_ERROR(dev, "failed to request irq: %d\n", ret);
1505 return ret;
1506 }
1507
1508 dsi2->host.ops = &dw_mipi_dsi2_host_ops;
1509 dsi2->host.dev = dev;
1510 ret = mipi_dsi_host_register(&dsi2->host);
1511 if (ret) {
1512 DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret);
1513 return ret;
1514 }
1515
1516 return component_add(&pdev->dev, &dw_mipi_dsi2_ops);
1517 }
1518
dw_mipi_dsi2_remove(struct platform_device * pdev)1519 static int dw_mipi_dsi2_remove(struct platform_device *pdev)
1520 {
1521 return 0;
1522 }
1523
dw_mipi_dsi2_runtime_suspend(struct device * dev)1524 static __maybe_unused int dw_mipi_dsi2_runtime_suspend(struct device *dev)
1525 {
1526 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev);
1527
1528 clk_disable_unprepare(dsi2->pclk);
1529 clk_disable_unprepare(dsi2->sys_clk);
1530
1531 return 0;
1532 }
1533
dw_mipi_dsi2_runtime_resume(struct device * dev)1534 static __maybe_unused int dw_mipi_dsi2_runtime_resume(struct device *dev)
1535 {
1536 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev);
1537
1538 clk_prepare_enable(dsi2->pclk);
1539 clk_prepare_enable(dsi2->sys_clk);
1540
1541 return 0;
1542 }
1543
1544 static const struct dev_pm_ops dw_mipi_dsi2_rockchip_pm_ops = {
1545 SET_RUNTIME_PM_OPS(dw_mipi_dsi2_runtime_suspend,
1546 dw_mipi_dsi2_runtime_resume, NULL)
1547 };
1548
1549 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = {
1550 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11),
1551 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10),
1552 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9),
1553 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8),
1554 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7),
1555 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3),
1556 };
1557
1558 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = {
1559 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11),
1560 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10),
1561 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9),
1562 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8),
1563 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7),
1564 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3),
1565 };
1566
1567 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = {
1568 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields,
1569 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields,
1570 .dphy_max_bit_rate_per_lane = 4500000000ULL,
1571 .cphy_max_symbol_rate_per_lane = 2000000000ULL,
1572 };
1573
1574 static const struct of_device_id dw_mipi_dsi2_dt_ids[] = {
1575 {
1576 .compatible = "rockchip,rk3588-mipi-dsi2",
1577 .data = &rk3588_mipi_dsi2_plat_data,
1578 },
1579 {}
1580 };
1581 MODULE_DEVICE_TABLE(of, dw_mipi_dsi2_dt_ids);
1582
1583 struct platform_driver dw_mipi_dsi2_rockchip_driver = {
1584 .probe = dw_mipi_dsi2_probe,
1585 .remove = dw_mipi_dsi2_remove,
1586 .driver = {
1587 .of_match_table = dw_mipi_dsi2_dt_ids,
1588 .pm = &dw_mipi_dsi2_rockchip_pm_ops,
1589 .name = "dw-mipi-dsi2",
1590 },
1591 };
1592