1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Rockchip CIF Driver 4 * 5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd. 6 */ 7 8 #ifndef _RKCIF_HW_H 9 #define _RKCIF_HW_H 10 11 #include <linux/mutex.h> 12 #include <media/media-device.h> 13 #include <media/media-entity.h> 14 #include <media/v4l2-ctrls.h> 15 #include <media/v4l2-device.h> 16 #include <media/videobuf2-v4l2.h> 17 #include <media/v4l2-mc.h> 18 #include <linux/rk-camera-module.h> 19 #include "regs.h" 20 #include "version.h" 21 22 #define RKCIF_DEV_MAX 7 23 #define RKCIF_HW_DRIVER_NAME "rkcifhw" 24 #define RKCIF_MAX_BUS_CLK 8 25 #define RKCIF_MAX_RESET 15 26 27 #define write_cif_reg(base, addr, val) \ 28 writel(val, (addr) + (base)) 29 #define read_cif_reg(base, addr) \ 30 readl((addr) + (base)) 31 #define write_cif_reg_or(base, addr, val) \ 32 writel(readl((addr) + (base)) | (val), (addr) + (base)) 33 #define write_cif_reg_and(base, addr, val) \ 34 writel(readl((addr) + (base)) & (val), (addr) + (base)) 35 36 /* 37 * multi sensor sync mode 38 * RKCIF_NOSYNC_MODE: not used sync mode 39 * RKCIF_MASTER_MASTER: internal master->external master 40 * RKCIF_MASTER_SLAVE: internal master->slave 41 * RKCIF_MASTER_MASTER: pwm/gpio->external master 42 * RKCIF_MASTER_MASTER: pwm/gpio->slave 43 */ 44 enum rkcif_sync_mode { 45 RKCIF_NOSYNC_MODE, 46 RKCIF_MASTER_MASTER, 47 RKCIF_MASTER_SLAVE, 48 RKCIF_EXT_MASTER, 49 RKCIF_EXT_SLAVE, 50 }; 51 52 struct rkcif_sync_dev { 53 struct rkcif_device *cif_dev[RKCIF_DEV_MAX]; 54 int count; 55 bool is_streaming[RKCIF_DEV_MAX]; 56 }; 57 58 struct rkcif_multi_sync_config { 59 struct rkcif_sync_dev int_master; 60 struct rkcif_sync_dev ext_master; 61 struct rkcif_sync_dev slave; 62 enum rkcif_sync_mode mode; 63 int dev_cnt; 64 int streaming_cnt; 65 bool is_attach; 66 }; 67 68 /* 69 * add new chip id in tail in time order 70 * by increasing to distinguish cif version 71 */ 72 enum rkcif_chip_id { 73 CHIP_PX30_CIF, 74 CHIP_RK3128_CIF, 75 CHIP_RK3288_CIF, 76 CHIP_RK3328_CIF, 77 CHIP_RK3368_CIF, 78 CHIP_RK1808_CIF, 79 CHIP_RV1126_CIF, 80 CHIP_RV1126_CIF_LITE, 81 CHIP_RK3568_CIF, 82 CHIP_RK3588_CIF, 83 }; 84 85 struct rkcif_hw_match_data { 86 int chip_id; 87 const char * const *clks; 88 const char * const *rsts; 89 int clks_num; 90 int rsts_num; 91 const struct cif_reg *cif_regs; 92 }; 93 94 /* 95 * struct rkcif_device - ISP platform device 96 * @base_addr: base register address 97 * @active_sensor: sensor in-use, set when streaming on 98 * @stream: capture video device 99 */ 100 struct rkcif_hw { 101 struct device *dev; 102 int irq; 103 void __iomem *base_addr; 104 void __iomem *csi_base; 105 struct regmap *grf; 106 struct clk *clks[RKCIF_MAX_BUS_CLK]; 107 int clk_size; 108 struct iommu_domain *domain; 109 struct reset_control *cif_rst[RKCIF_MAX_RESET]; 110 int chip_id; 111 const struct cif_reg *cif_regs; 112 const struct vb2_mem_ops *mem_ops; 113 bool iommu_en; 114 bool can_be_reset; 115 bool is_dma_sg_ops; 116 bool is_dma_contig; 117 struct rkcif_device *cif_dev[RKCIF_DEV_MAX]; 118 int dev_num; 119 120 atomic_t power_cnt; 121 const struct rkcif_hw_match_data *match_data; 122 struct mutex dev_lock; 123 struct rkcif_multi_sync_config sync_config; 124 }; 125 126 void rkcif_hw_soft_reset(struct rkcif_hw *cif_hw, bool is_rst_iommu); 127 void rkcif_disable_sys_clk(struct rkcif_hw *cif_hw); 128 int rkcif_enable_sys_clk(struct rkcif_hw *cif_hw); 129 130 #endif 131