1 /*
2 * Rockchip MIPI RX Synopsys/Innosilicon DPHY driver
3 *
4 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/clk.h>
36 #include <linux/delay.h>
37 #include <linux/io.h>
38 #include <linux/module.h>
39 #include <linux/of.h>
40 #include <linux/of_graph.h>
41 #include <linux/of_platform.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/regmap.h>
45 #include <linux/mfd/syscon.h>
46 #include <media/media-entity.h>
47 #include <media/v4l2-ctrls.h>
48 #include <media/v4l2-fwnode.h>
49 #include <media/v4l2-subdev.h>
50 #include <media/v4l2-device.h>
51
52 /* GRF */
53 #define RK1808_GRF_PD_VI_CON_OFFSET 0x0430
54
55 #define RK3288_GRF_SOC_CON6 0x025c
56 #define RK3288_GRF_SOC_CON8 0x0264
57 #define RK3288_GRF_SOC_CON9 0x0268
58 #define RK3288_GRF_SOC_CON10 0x026c
59 #define RK3288_GRF_SOC_CON14 0x027c
60 #define RK3288_GRF_SOC_STATUS21 0x02d4
61 #define RK3288_GRF_IO_VSEL 0x0380
62 #define RK3288_GRF_SOC_CON15 0x03a4
63
64 #define RK3326_GRF_IO_VSEL_OFFSET 0x0180
65 #define RK3326_GRF_PD_VI_CON_OFFSET 0x0430
66
67 #define RK3368_GRF_SOC_CON6_OFFSET 0x0418
68 #define RK3368_GRF_IO_VSEL_OFFSET 0x0900
69
70 #define RK3399_GRF_SOC_CON9 0x6224
71 #define RK3399_GRF_SOC_CON21 0x6254
72 #define RK3399_GRF_SOC_CON22 0x6258
73 #define RK3399_GRF_SOC_CON23 0x625c
74 #define RK3399_GRF_SOC_CON24 0x6260
75 #define RK3399_GRF_SOC_CON25 0x6264
76 #define RK3399_GRF_SOC_STATUS1 0xe2a4
77 #define RK3399_GRF_IO_VSEL 0x0900
78
79 #define RV1126_GRF_CSIPHY0_CON 0x10200
80 #define RV1126_GRF_CSIPHY1_CON 0x10210
81 #define RV1126_GRF_IOFUNC_CON3 0x1026c
82 #define RV1126_GRF_PHY1_SEL_CIFLITE BIT(2)
83 #define RV1126_GRF_PHY1_SEL_ISP BIT(1)
84 #define RV1126_GRF_PHY1_SEL_CIF BIT(0)
85
86 /* PHY */
87 #define RK3288_PHY_TEST_CTRL0 0x30
88 #define RK3288_PHY_TEST_CTRL1 0x34
89 #define RK3288_PHY_SHUTDOWNZ 0x08
90 #define RK3288_PHY_RSTZ 0x0c
91
92 #define RK3399_PHY_TEST_CTRL0 0xb4
93 #define RK3399_PHY_TEST_CTRL1 0xb8
94 #define RK3399_PHY_SHUTDOWNZ 0xa0
95 #define RK3399_PHY_RSTZ 0xa0
96
97 #define CLOCK_LANE_HS_RX_CONTROL 0x34
98 #define LANE0_HS_RX_CONTROL 0x44
99 #define LANE1_HS_RX_CONTROL 0x54
100 #define LANE2_HS_RX_CONTROL 0x84
101 #define LANE3_HS_RX_CONTROL 0x94
102 #define HS_RX_DATA_LANES_THS_SETTLE_CONTROL 0x75
103
104 /* LOW POWER MODE SET */
105 #define MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 0xFFFF
106
107 #define RK1808_CSI_DPHY_CTRL_LANE_ENABLE 0x00
108 #define RK1808_CSI_DPHY_CTRL_PWRCTL \
109 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
110 #define RK1808_CSI_DPHY_CTRL_DIG_RST 0x80
111
112 #define RK3326_CSI_DPHY_CTRL_LANE_ENABLE 0x00
113 #define RK3326_CSI_DPHY_CTRL_PWRCTL 0x04
114 #define RK3326_CSI_DPHY_CTRL_DIG_RST 0x80
115
116 #define RK3368_CSI_DPHY_CTRL_LANE_ENABLE 0x00
117 #define RK3368_CSI_DPHY_CTRL_PWRCTL 0x04
118 #define RK3368_CSI_DPHY_CTRL_DIG_RST 0x80
119
120 #define RV1126_CSI_DPHY_CTRL_LANE_ENABLE 0x00
121 #define RV1126_CSI_DPHY_CTRL_PWRCTL \
122 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
123 #define RV1126_CSI_DPHY_CTRL_DIG_RST 0x80
124
125 #define MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT 2
126 #define MIPI_CSI_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT 6
127
128 /* Configure the count time of the THS-SETTLE by protocol. */
129 #define RK1808_CSI_DPHY_CLK_WR_THS_SETTLE 0x160
130 #define RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE \
131 (RK1808_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
132 #define RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE \
133 (RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
134 #define RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE \
135 (RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
136 #define RK1808_CSI_DPHY_LANE3_WR_THS_SETTLE \
137 (RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
138
139 #define RK3326_CSI_DPHY_CLK_WR_THS_SETTLE 0x100
140 #define RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE \
141 (RK3326_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
142 #define RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE \
143 (RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
144 #define RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE \
145 (RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
146 #define RK3326_CSI_DPHY_LANE3_WR_THS_SETTLE \
147 (RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
148
149 #define RK3368_CSI_DPHY_CLK_WR_THS_SETTLE 0x100
150 #define RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE \
151 (RK3368_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
152 #define RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE \
153 (RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
154 #define RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE \
155 (RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
156 #define RK3368_CSI_DPHY_LANE3_WR_THS_SETTLE \
157 (RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
158
159 #define RV1126_CSI_DPHY_CLK_WR_THS_SETTLE 0x160
160 #define RV1126_CSI_DPHY_LANE0_WR_THS_SETTLE 0x1e0
161 #define RV1126_CSI_DPHY_LANE1_WR_THS_SETTLE 0x260
162 #define RV1126_CSI_DPHY_LANE2_WR_THS_SETTLE 0x2e0
163 #define RV1126_CSI_DPHY_LANE3_WR_THS_SETTLE 0x360
164
165 /* Calibration reception enable */
166 #define RK1808_CSI_DPHY_CLK_CALIB_EN 0x168
167 #define RK1808_CSI_DPHY_LANE0_CALIB_EN 0x1e8
168 #define RK1808_CSI_DPHY_LANE1_CALIB_EN 0x268
169 #define RK1808_CSI_DPHY_LANE2_CALIB_EN 0x2e8
170 #define RK1808_CSI_DPHY_LANE3_CALIB_EN 0x368
171
172 #define RK3326_CSI_DPHY_CLK_CALIB_EN \
173 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
174 #define RK3326_CSI_DPHY_LANE0_CALIB_EN \
175 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
176 #define RK3326_CSI_DPHY_LANE1_CALIB_EN \
177 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
178 #define RK3326_CSI_DPHY_LANE2_CALIB_EN \
179 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
180 #define RK3326_CSI_DPHY_LANE3_CALIB_EN \
181 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
182
183 #define RK3368_CSI_DPHY_CLK_CALIB_EN \
184 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
185 #define RK3368_CSI_DPHY_LANE0_CALIB_EN \
186 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
187 #define RK3368_CSI_DPHY_LANE1_CALIB_EN \
188 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
189 #define RK3368_CSI_DPHY_LANE2_CALIB_EN \
190 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
191 #define RK3368_CSI_DPHY_LANE3_CALIB_EN \
192 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
193
194 #define RV1126_CSI_DPHY_CLK_CALIB_EN 0x168
195 #define RV1126_CSI_DPHY_LANE0_CALIB_EN 0x1e8
196 #define RV1126_CSI_DPHY_LANE1_CALIB_EN 0x268
197 #define RV1126_CSI_DPHY_LANE2_CALIB_EN 0x2e8
198 #define RV1126_CSI_DPHY_LANE3_CALIB_EN 0x368
199
200 #define RV1126_CSI_DPHY_MIPI_LVDS_MODEL 0x2cc
201 #define RV1126_CSI_DPHY_LVDS_MODE 0x300
202 /*
203 * CSI HOST
204 */
205 #define PHY_TESTEN_ADDR (0x1 << 16)
206 #define PHY_TESTEN_DATA (0x0 << 16)
207 #define PHY_TESTCLK (0x1 << 1)
208 #define PHY_TESTCLR (0x1 << 0)
209 #define THS_SETTLE_COUNTER_THRESHOLD 0x04
210
211 #define HIWORD_UPDATE(val, mask, shift) \
212 ((val) << (shift) | (mask) << ((shift) + 16))
213
214 enum mipi_dphy_chip_id {
215 CHIP_ID_RK1808 = 0,
216 CHIP_ID_RK3288,
217 CHIP_ID_RK3326,
218 CHIP_ID_RK3368,
219 CHIP_ID_RK3399,
220 CHIP_ID_RK1126,
221 };
222
223 enum mipi_dphy_rx_pads {
224 MIPI_DPHY_RX_PAD_SINK = 0,
225 MIPI_DPHY_RX_PAD_SOURCE,
226 MIPI_DPHY_RX_PADS_NUM,
227 };
228
229 enum dphy_reg_id {
230 GRF_DPHY_RX0_TURNDISABLE = 0,
231 GRF_DPHY_RX0_FORCERXMODE,
232 GRF_DPHY_RX0_FORCETXSTOPMODE,
233 GRF_DPHY_RX0_ENABLE,
234 GRF_DPHY_RX0_TESTCLR,
235 GRF_DPHY_RX0_TESTCLK,
236 GRF_DPHY_RX0_TESTEN,
237 GRF_DPHY_RX0_TESTDIN,
238 GRF_DPHY_RX0_TURNREQUEST,
239 GRF_DPHY_RX0_TESTDOUT,
240 GRF_DPHY_TX0_TURNDISABLE,
241 GRF_DPHY_TX0_FORCERXMODE,
242 GRF_DPHY_TX0_FORCETXSTOPMODE,
243 GRF_DPHY_TX0_TURNREQUEST,
244 GRF_DPHY_TX1RX1_TURNDISABLE,
245 GRF_DPHY_TX1RX1_FORCERXMODE,
246 GRF_DPHY_TX1RX1_FORCETXSTOPMODE,
247 GRF_DPHY_TX1RX1_ENABLE,
248 GRF_DPHY_TX1RX1_MASTERSLAVEZ,
249 GRF_DPHY_TX1RX1_BASEDIR,
250 GRF_DPHY_TX1RX1_ENABLECLK,
251 GRF_DPHY_TX1RX1_TURNREQUEST,
252 GRF_DPHY_RX1_SRC_SEL,
253 /* rk3288 only */
254 GRF_CON_DISABLE_ISP,
255 GRF_CON_ISP_DPHY_SEL,
256 GRF_DSI_CSI_TESTBUS_SEL,
257 GRF_DVP_V18SEL,
258 /* rk1808 & rk3326 & rv1126 */
259 GRF_DPHY_CSIPHY_FORCERXMODE,
260 GRF_DPHY_CSIPHY_CLKLANE_EN,
261 GRF_DPHY_CSIPHY_DATALANE_EN,
262 /* rv1126 only */
263 GRF_DPHY_CLK_INV_SEL,
264 GRF_DPHY_SEL,
265 /* rk3368 only */
266 GRF_ISP_MIPI_CSI_HOST_SEL,
267 /* below is for rk3399 only */
268 GRF_DPHY_RX0_CLK_INV_SEL,
269 GRF_DPHY_RX1_CLK_INV_SEL,
270 GRF_DPHY_TX1RX1_SRC_SEL,
271 };
272
273 enum csiphy_reg_id {
274 CSIPHY_CTRL_LANE_ENABLE = 0,
275 CSIPHY_CTRL_PWRCTL,
276 CSIPHY_CTRL_DIG_RST,
277 CSIPHY_CLK_THS_SETTLE,
278 CSIPHY_LANE0_THS_SETTLE,
279 CSIPHY_LANE1_THS_SETTLE,
280 CSIPHY_LANE2_THS_SETTLE,
281 CSIPHY_LANE3_THS_SETTLE,
282 CSIPHY_CLK_CALIB_ENABLE,
283 CSIPHY_LANE0_CALIB_ENABLE,
284 CSIPHY_LANE1_CALIB_ENABLE,
285 CSIPHY_LANE2_CALIB_ENABLE,
286 CSIPHY_LANE3_CALIB_ENABLE,
287 //rv1126 only
288 CSIPHY_MIPI_LVDS_MODEL,
289 CSIPHY_LVDS_MODE,
290 };
291
292 enum mipi_dphy_ctl_type {
293 MIPI_DPHY_CTL_GRF_ONLY = 0,
294 MIPI_DPHY_CTL_CSI_HOST
295 };
296
297 enum mipi_dphy_lane {
298 MIPI_DPHY_LANE_CLOCK = 0,
299 MIPI_DPHY_LANE_DATA0,
300 MIPI_DPHY_LANE_DATA1,
301 MIPI_DPHY_LANE_DATA2,
302 MIPI_DPHY_LANE_DATA3
303 };
304
305 enum txrx_reg_id {
306 TXRX_PHY_TEST_CTRL0 = 0,
307 TXRX_PHY_TEST_CTRL1,
308 TXRX_PHY_SHUTDOWNZ,
309 TXRX_PHY_RSTZ,
310 };
311
312 struct dphy_reg {
313 u32 offset;
314 u32 mask;
315 u32 shift;
316 };
317
318 struct txrx_reg {
319 u32 offset;
320 };
321
322 struct csiphy_reg {
323 u32 offset;
324 };
325
326 #define PHY_REG(_offset, _width, _shift) \
327 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
328
329 #define TXRX_REG(_offset) \
330 { .offset = _offset, }
331
332 #define CSIPHY_REG(_offset) \
333 { .offset = _offset, }
334
335 static const struct dphy_reg rk1808_grf_dphy_regs[] = {
336 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),
337 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 1, 8),
338 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 4),
339 };
340
341 static const struct dphy_reg rk3288_grf_dphy_regs[] = {
342 [GRF_CON_DISABLE_ISP] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 0),
343 [GRF_CON_ISP_DPHY_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 1),
344 [GRF_DSI_CSI_TESTBUS_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 14),
345 [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 0),
346 [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 4),
347 [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 8),
348 [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 0),
349 [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 4),
350 [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 8),
351 [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 12),
352 [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 0),
353 [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 4),
354 [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 8),
355 [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 12),
356 [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 0),
357 [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 1),
358 [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 2),
359 [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3288_GRF_SOC_CON14, 8, 3),
360 [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 12),
361 [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 13),
362 [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 14),
363 [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 15),
364 [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 0),
365 [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 4),
366 [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 3, 8),
367 [GRF_DVP_V18SEL] = PHY_REG(RK3288_GRF_IO_VSEL, 1, 1),
368 [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3288_GRF_SOC_STATUS21, 8, 0),
369 };
370
371 static const struct dphy_reg rk3326_grf_dphy_regs[] = {
372 [GRF_DVP_V18SEL] = PHY_REG(RK3326_GRF_IO_VSEL_OFFSET, 1, 4),
373 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 0),
374 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 1, 8),
375 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 4),
376 };
377
378 static const struct dphy_reg rk3368_grf_dphy_regs[] = {
379 [GRF_DVP_V18SEL] = PHY_REG(RK3368_GRF_IO_VSEL_OFFSET, 1, 1),
380 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8),
381 [GRF_ISP_MIPI_CSI_HOST_SEL] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 1, 1),
382 [GRF_CON_DISABLE_ISP] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 1, 0),
383 };
384
385 static const struct dphy_reg rk3399_grf_dphy_regs[] = {
386 [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),
387 [GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10),
388 [GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11),
389 [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0),
390 [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4),
391 [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8),
392 [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12),
393 [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0),
394 [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4),
395 [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 8),
396 [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 12),
397 [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 0),
398 [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 4),
399 [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 8),
400 [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 12),
401 [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON24, 4, 0),
402 [GRF_DPHY_TX1RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4),
403 [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 5),
404 [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 6),
405 [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 7),
406 [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3399_GRF_SOC_CON25, 8, 0),
407 [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 8),
408 [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 9),
409 [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 10),
410 [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3399_GRF_SOC_STATUS1, 8, 0),
411 [GRF_DVP_V18SEL] = PHY_REG(RK3399_GRF_IO_VSEL, 1, 1),
412 };
413
414 static const struct dphy_reg rv1126_grf_dphy0_regs[] = {
415 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 4, 0),
416 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 4, 4),
417 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 1, 8),
418 [GRF_DPHY_CLK_INV_SEL] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 1, 9),
419 [GRF_DPHY_SEL] = PHY_REG(RV1126_GRF_IOFUNC_CON3, 3, 9),
420 };
421
422 static const struct dphy_reg rv1126_grf_dphy1_regs[] = {
423 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 4, 0),
424 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 4, 4),
425 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 1, 8),
426 [GRF_DPHY_CLK_INV_SEL] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 1, 9),
427 [GRF_DPHY_SEL] = PHY_REG(RV1126_GRF_IOFUNC_CON3, 3, 9),
428 };
429
430 static const struct txrx_reg rk3288_txrx_regs[] = {
431 [TXRX_PHY_TEST_CTRL0] = TXRX_REG(RK3288_PHY_TEST_CTRL0),
432 [TXRX_PHY_TEST_CTRL1] = TXRX_REG(RK3288_PHY_TEST_CTRL1),
433 [TXRX_PHY_SHUTDOWNZ] = TXRX_REG(RK3288_PHY_SHUTDOWNZ),
434 [TXRX_PHY_RSTZ] = TXRX_REG(RK3288_PHY_RSTZ),
435 };
436
437 static const struct txrx_reg rk3399_txrx_regs[] = {
438 [TXRX_PHY_TEST_CTRL0] = TXRX_REG(RK3399_PHY_TEST_CTRL0),
439 [TXRX_PHY_TEST_CTRL1] = TXRX_REG(RK3399_PHY_TEST_CTRL1),
440 [TXRX_PHY_SHUTDOWNZ] = TXRX_REG(RK3399_PHY_SHUTDOWNZ),
441 [TXRX_PHY_RSTZ] = TXRX_REG(RK3399_PHY_RSTZ),
442 };
443
444 static const struct csiphy_reg rk1808_csiphy_regs[] = {
445 [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_CTRL_LANE_ENABLE),
446 [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK1808_CSI_DPHY_CTRL_PWRCTL),
447 [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK1808_CSI_DPHY_CTRL_DIG_RST),
448 [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_CLK_WR_THS_SETTLE),
449 [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE),
450 [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE),
451 [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE),
452 [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE3_WR_THS_SETTLE),
453 [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_CLK_CALIB_EN),
454 [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE0_CALIB_EN),
455 [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE1_CALIB_EN),
456 [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE2_CALIB_EN),
457 [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE3_CALIB_EN),
458 };
459
460 static const struct csiphy_reg rk3326_csiphy_regs[] = {
461 [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_LANE_ENABLE),
462 [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_PWRCTL),
463 [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_DIG_RST),
464 [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_CLK_WR_THS_SETTLE),
465 [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE),
466 [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE),
467 [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE),
468 [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE3_WR_THS_SETTLE),
469 [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_CLK_CALIB_EN),
470 [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE0_CALIB_EN),
471 [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE1_CALIB_EN),
472 [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE2_CALIB_EN),
473 [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE3_CALIB_EN),
474 };
475
476 static const struct csiphy_reg rk3368_csiphy_regs[] = {
477 [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_LANE_ENABLE),
478 [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_PWRCTL),
479 [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_DIG_RST),
480 [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_CLK_WR_THS_SETTLE),
481 [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE),
482 [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE),
483 [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE),
484 [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE3_WR_THS_SETTLE),
485 [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_CLK_CALIB_EN),
486 [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE0_CALIB_EN),
487 [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE1_CALIB_EN),
488 [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE2_CALIB_EN),
489 [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE3_CALIB_EN),
490 };
491
492 static const struct csiphy_reg rv1126_csiphy_regs[] = {
493 [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_CTRL_LANE_ENABLE),
494 [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RV1126_CSI_DPHY_CTRL_PWRCTL),
495 [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RV1126_CSI_DPHY_CTRL_DIG_RST),
496 [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_CLK_WR_THS_SETTLE),
497 [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE0_WR_THS_SETTLE),
498 [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE1_WR_THS_SETTLE),
499 [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE2_WR_THS_SETTLE),
500 [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE3_WR_THS_SETTLE),
501 [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_CLK_CALIB_EN),
502 [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE0_CALIB_EN),
503 [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE1_CALIB_EN),
504 [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE2_CALIB_EN),
505 [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE3_CALIB_EN),
506 [CSIPHY_MIPI_LVDS_MODEL] = CSIPHY_REG(RV1126_CSI_DPHY_MIPI_LVDS_MODEL),
507 [CSIPHY_LVDS_MODE] = CSIPHY_REG(RV1126_CSI_DPHY_LVDS_MODE),
508 };
509
510 struct hsfreq_range {
511 u32 range_h;
512 u8 cfg_bit;
513 };
514
515 struct mipidphy_priv;
516
517 struct dphy_drv_data {
518 const char * const *clks;
519 int num_clks;
520 const struct hsfreq_range *hsfreq_ranges;
521 int num_hsfreq_ranges;
522 const struct dphy_reg *grf_regs;
523 const struct txrx_reg *txrx_regs;
524 const struct csiphy_reg *csiphy_regs;
525 enum mipi_dphy_ctl_type ctl_type;
526 void (*individual_init)(struct mipidphy_priv *priv);
527 enum mipi_dphy_chip_id chip_id;
528 };
529
530 struct sensor_async_subdev {
531 struct v4l2_async_subdev asd;
532 struct v4l2_mbus_config mbus;
533 int lanes;
534 };
535
536 #define MAX_DPHY_CLK 8
537 #define MAX_DPHY_SENSORS 2
538
539 struct mipidphy_sensor {
540 struct v4l2_subdev *sd;
541 struct v4l2_mbus_config mbus;
542 struct v4l2_mbus_framefmt format;
543 int lanes;
544 };
545
546 struct mipidphy_priv {
547 struct device *dev;
548 struct regmap *regmap_grf;
549 const struct dphy_reg *grf_regs;
550 const struct txrx_reg *txrx_regs;
551 const struct csiphy_reg *csiphy_regs;
552 void __iomem *csihost_base_addr;
553 struct clk *clks[MAX_DPHY_CLK];
554 const struct dphy_drv_data *drv_data;
555 u64 data_rate_mbps;
556 struct v4l2_async_notifier notifier;
557 struct v4l2_subdev sd;
558 struct mutex mutex; /* lock for updating protection */
559 struct media_pad pads[MIPI_DPHY_RX_PADS_NUM];
560 struct mipidphy_sensor sensors[MAX_DPHY_SENSORS];
561 int num_sensors;
562 int phy_index;
563 bool is_streaming;
564 void __iomem *txrx_base_addr;
565 int (*stream_on)(struct mipidphy_priv *priv, struct v4l2_subdev *sd);
566 int (*stream_off)(struct mipidphy_priv *priv, struct v4l2_subdev *sd);
567 };
568
to_dphy_priv(struct v4l2_subdev * subdev)569 static inline struct mipidphy_priv *to_dphy_priv(struct v4l2_subdev *subdev)
570 {
571 return container_of(subdev, struct mipidphy_priv, sd);
572 }
573
write_grf_reg(struct mipidphy_priv * priv,int index,u8 value)574 static inline void write_grf_reg(struct mipidphy_priv *priv,
575 int index, u8 value)
576 {
577 const struct dphy_reg *reg = &priv->grf_regs[index];
578 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
579
580 if (reg->offset)
581 regmap_write(priv->regmap_grf, reg->offset, val);
582 }
583
read_grf_reg(struct mipidphy_priv * priv,int index)584 static inline u32 read_grf_reg(struct mipidphy_priv *priv, int index)
585 {
586 const struct dphy_reg *reg = &priv->grf_regs[index];
587 unsigned int val = 0;
588
589 if (reg->offset) {
590 regmap_read(priv->regmap_grf, reg->offset, &val);
591 val = (val >> reg->shift) & reg->mask;
592 }
593 return val;
594 }
595
write_txrx_reg(struct mipidphy_priv * priv,int index,u32 value)596 static inline void write_txrx_reg(struct mipidphy_priv *priv,
597 int index, u32 value)
598 {
599 const struct txrx_reg *reg = &priv->txrx_regs[index];
600
601 if (reg->offset)
602 writel(value, priv->txrx_base_addr + reg->offset);
603 }
604
mipidphy0_wr_reg(struct mipidphy_priv * priv,u8 test_code,u8 test_data)605 static void mipidphy0_wr_reg(struct mipidphy_priv *priv,
606 u8 test_code, u8 test_data)
607 {
608 /*
609 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
610 * is latched internally as the current test code. Test data is
611 * programmed internally by rising edge on TESTCLK.
612 */
613 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
614 write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_code);
615 write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 1);
616 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 0);
617 write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 0);
618 write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_data);
619 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
620 }
621
mipidphy1_wr_reg(struct mipidphy_priv * priv,unsigned char addr,unsigned char data)622 static void mipidphy1_wr_reg(struct mipidphy_priv *priv, unsigned char addr,
623 unsigned char data)
624 {
625 /*
626 * TESTEN =1,TESTDIN=addr
627 * TESTCLK=0
628 * TESTEN =0,TESTDIN=data
629 * TESTCLK=1
630 */
631 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL1, PHY_TESTEN_ADDR | addr);
632 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, 0x00);
633 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL1, PHY_TESTEN_DATA | data);
634 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, 0x02);
635 }
636
write_csiphy_reg(struct mipidphy_priv * priv,int index,u32 value)637 static inline void write_csiphy_reg(struct mipidphy_priv *priv,
638 int index, u32 value)
639 {
640 const struct csiphy_reg *reg = &priv->csiphy_regs[index];
641
642 if (reg->offset != MIPI_CSI_DPHY_CTRL_INVALID_OFFSET)
643 writel(value, priv->csihost_base_addr + reg->offset);
644 }
645
read_csiphy_reg(struct mipidphy_priv * priv,int index,u32 * value)646 static inline void read_csiphy_reg(struct mipidphy_priv *priv,
647 int index, u32 *value)
648 {
649 const struct csiphy_reg *reg = &priv->csiphy_regs[index];
650
651 if (reg->offset != MIPI_CSI_DPHY_CTRL_INVALID_OFFSET)
652 *value = readl(priv->csihost_base_addr + reg->offset);
653 }
654
csi_mipidphy_wr_ths_settle(struct mipidphy_priv * priv,int hsfreq,enum mipi_dphy_lane lane)655 static void csi_mipidphy_wr_ths_settle(struct mipidphy_priv *priv, int hsfreq,
656 enum mipi_dphy_lane lane)
657 {
658 unsigned int val = 0;
659 unsigned int offset;
660
661 switch (lane) {
662 case MIPI_DPHY_LANE_CLOCK:
663 offset = CSIPHY_CLK_THS_SETTLE;
664 break;
665 case MIPI_DPHY_LANE_DATA0:
666 offset = CSIPHY_LANE0_THS_SETTLE;
667 break;
668 case MIPI_DPHY_LANE_DATA1:
669 offset = CSIPHY_LANE1_THS_SETTLE;
670 break;
671 case MIPI_DPHY_LANE_DATA2:
672 offset = CSIPHY_LANE2_THS_SETTLE;
673 break;
674 case MIPI_DPHY_LANE_DATA3:
675 offset = CSIPHY_LANE3_THS_SETTLE;
676 break;
677 default:
678 return;
679 }
680
681 read_csiphy_reg(priv, offset, &val);
682 val = (val & ~0x7f) | hsfreq;
683 write_csiphy_reg(priv, offset, val);
684 }
685
get_remote_sensor(struct v4l2_subdev * sd)686 static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
687 {
688 struct media_pad *local, *remote;
689 struct media_entity *sensor_me;
690
691 local = &sd->entity.pads[MIPI_DPHY_RX_PAD_SINK];
692 remote = media_entity_remote_pad(local);
693 if (!remote) {
694 v4l2_warn(sd, "No link between dphy and sensor\n");
695 return NULL;
696 }
697
698 sensor_me = media_entity_remote_pad(local)->entity;
699 return media_entity_to_v4l2_subdev(sensor_me);
700 }
701
sd_to_sensor(struct mipidphy_priv * priv,struct v4l2_subdev * sd)702 static struct mipidphy_sensor *sd_to_sensor(struct mipidphy_priv *priv,
703 struct v4l2_subdev *sd)
704 {
705 int i;
706
707 for (i = 0; i < priv->num_sensors; ++i)
708 if (priv->sensors[i].sd == sd)
709 return &priv->sensors[i];
710
711 return NULL;
712 }
713
mipidphy_get_sensor_data_rate(struct v4l2_subdev * sd)714 static int mipidphy_get_sensor_data_rate(struct v4l2_subdev *sd)
715 {
716 struct mipidphy_priv *priv = to_dphy_priv(sd);
717 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
718 struct v4l2_ctrl *link_freq;
719 struct v4l2_querymenu qm = { .id = V4L2_CID_LINK_FREQ, };
720 int ret;
721
722 link_freq = v4l2_ctrl_find(sensor_sd->ctrl_handler, V4L2_CID_LINK_FREQ);
723 if (!link_freq) {
724 v4l2_warn(sd, "No pixel rate control in subdev\n");
725 return -EPIPE;
726 }
727
728 qm.index = v4l2_ctrl_g_ctrl(link_freq);
729 ret = v4l2_querymenu(sensor_sd->ctrl_handler, &qm);
730 if (ret < 0) {
731 v4l2_err(sd, "Failed to get menu item\n");
732 return ret;
733 }
734
735 if (!qm.value) {
736 v4l2_err(sd, "Invalid link_freq\n");
737 return -EINVAL;
738 }
739 priv->data_rate_mbps = qm.value * 2;
740 do_div(priv->data_rate_mbps, 1000 * 1000);
741 v4l2_info(sd, "data_rate_mbps %lld\n", priv->data_rate_mbps);
742 return 0;
743 }
744
mipidphy_update_sensor_mbus(struct v4l2_subdev * sd)745 static int mipidphy_update_sensor_mbus(struct v4l2_subdev *sd)
746 {
747 struct mipidphy_priv *priv = to_dphy_priv(sd);
748 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
749 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
750 struct v4l2_mbus_config mbus;
751 int ret;
752
753 ret = v4l2_subdev_call(sensor_sd, pad, get_mbus_config, 0, &mbus);
754 if (ret)
755 return ret;
756
757 sensor->mbus = mbus;
758 switch (mbus.flags & V4L2_MBUS_CSI2_LANES) {
759 case V4L2_MBUS_CSI2_1_LANE:
760 sensor->lanes = 1;
761 break;
762 case V4L2_MBUS_CSI2_2_LANE:
763 sensor->lanes = 2;
764 break;
765 case V4L2_MBUS_CSI2_3_LANE:
766 sensor->lanes = 3;
767 break;
768 case V4L2_MBUS_CSI2_4_LANE:
769 sensor->lanes = 4;
770 break;
771 default:
772 return -EINVAL;
773 }
774
775 return 0;
776 }
777
rk1126_mipidphy_dphy_sel(struct v4l2_subdev * sd)778 static void rk1126_mipidphy_dphy_sel(struct v4l2_subdev *sd)
779 {
780 struct mipidphy_priv *priv = to_dphy_priv(sd);
781 char *model;
782 u8 oldval, newval;
783
784 model = sd->v4l2_dev->mdev->model;
785 oldval = read_grf_reg(priv, GRF_DPHY_SEL);
786 newval = oldval;
787 if (!strncmp(model, "rkcif_lite_mipi_lvds", sizeof("rkcif_lite_mipi_lvds") - 1)) {
788 if (priv->phy_index == 0)
789 newval &= ~RV1126_GRF_PHY1_SEL_CIFLITE;
790 else
791 newval |= RV1126_GRF_PHY1_SEL_CIFLITE;
792 } else if (!strncmp(model, "rkcif_mipi_lvds", sizeof("rkcif_mipi_lvds") - 1)) {
793 if (priv->phy_index == 0)
794 newval &= ~RV1126_GRF_PHY1_SEL_CIF;
795 else
796 newval |= RV1126_GRF_PHY1_SEL_CIF;
797 } else {
798 if (priv->phy_index == 0)
799 newval &= ~RV1126_GRF_PHY1_SEL_ISP;
800 else
801 newval |= RV1126_GRF_PHY1_SEL_ISP;
802 }
803
804 if (newval != oldval)
805 write_grf_reg(priv, GRF_DPHY_SEL, newval);
806 }
807
mipidphy_s_stream_start(struct v4l2_subdev * sd)808 static int mipidphy_s_stream_start(struct v4l2_subdev *sd)
809 {
810 struct mipidphy_priv *priv = to_dphy_priv(sd);
811 int ret = 0;
812
813 if (priv->is_streaming)
814 return 0;
815
816 ret = mipidphy_get_sensor_data_rate(sd);
817 if (ret < 0)
818 return ret;
819
820 if (priv->drv_data->chip_id == CHIP_ID_RK1126)
821 rk1126_mipidphy_dphy_sel(sd);
822
823 mipidphy_update_sensor_mbus(sd);
824 priv->stream_on(priv, sd);
825
826 priv->is_streaming = true;
827
828 return 0;
829 }
830
mipidphy_s_stream_stop(struct v4l2_subdev * sd)831 static int mipidphy_s_stream_stop(struct v4l2_subdev *sd)
832 {
833 struct mipidphy_priv *priv = to_dphy_priv(sd);
834
835 if (!priv->is_streaming)
836 return 0;
837
838 if (priv->stream_off)
839 priv->stream_off(priv, sd);
840 priv->is_streaming = false;
841
842 return 0;
843 }
844
mipidphy_s_stream(struct v4l2_subdev * sd,int on)845 static int mipidphy_s_stream(struct v4l2_subdev *sd, int on)
846 {
847 int ret = 0;
848 struct mipidphy_priv *priv = to_dphy_priv(sd);
849
850 dev_info(priv->dev, "stream on:%d\n", on);
851 mutex_lock(&priv->mutex);
852 if (on)
853 ret = mipidphy_s_stream_start(sd);
854 else
855 ret = mipidphy_s_stream_stop(sd);
856 mutex_unlock(&priv->mutex);
857 return ret;
858 }
859
mipidphy_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)860 static int mipidphy_g_frame_interval(struct v4l2_subdev *sd,
861 struct v4l2_subdev_frame_interval *fi)
862 {
863 struct v4l2_subdev *sensor = get_remote_sensor(sd);
864
865 if (sensor)
866 return v4l2_subdev_call(sensor, video, g_frame_interval, fi);
867
868 return -EINVAL;
869 }
870
mipidphy_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)871 static int mipidphy_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
872 struct v4l2_mbus_config *config)
873 {
874 struct mipidphy_priv *priv = to_dphy_priv(sd);
875 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
876 struct mipidphy_sensor *sensor;
877
878 if (!sensor_sd)
879 return -ENODEV;
880 sensor = sd_to_sensor(priv, sensor_sd);
881 mipidphy_update_sensor_mbus(sd);
882 *config = sensor->mbus;
883
884 return 0;
885 }
886
mipidphy_s_power(struct v4l2_subdev * sd,int on)887 static int mipidphy_s_power(struct v4l2_subdev *sd, int on)
888 {
889 struct mipidphy_priv *priv = to_dphy_priv(sd);
890
891 if (on)
892 return pm_runtime_get_sync(priv->dev);
893 else
894 return pm_runtime_put(priv->dev);
895 }
896
mipidphy_runtime_suspend(struct device * dev)897 static int mipidphy_runtime_suspend(struct device *dev)
898 {
899 struct media_entity *me = dev_get_drvdata(dev);
900 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
901 struct mipidphy_priv *priv = to_dphy_priv(sd);
902 int i, num_clks;
903
904 num_clks = priv->drv_data->num_clks;
905 for (i = num_clks - 1; i >= 0; i--)
906 if (!IS_ERR(priv->clks[i]))
907 clk_disable_unprepare(priv->clks[i]);
908
909 return 0;
910 }
911
mipidphy_runtime_resume(struct device * dev)912 static int mipidphy_runtime_resume(struct device *dev)
913 {
914 struct media_entity *me = dev_get_drvdata(dev);
915 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
916 struct mipidphy_priv *priv = to_dphy_priv(sd);
917 int i, num_clks, ret;
918
919 num_clks = priv->drv_data->num_clks;
920 for (i = 0; i < num_clks; i++) {
921 if (!IS_ERR(priv->clks[i])) {
922 ret = clk_prepare_enable(priv->clks[i]);
923 if (ret < 0)
924 goto err;
925 }
926 }
927
928 return 0;
929 err:
930 while (--i >= 0)
931 clk_disable_unprepare(priv->clks[i]);
932 return ret;
933 }
934
935 /* dphy accepts all fmt/size from sensor */
mipidphy_get_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)936 static int mipidphy_get_set_fmt(struct v4l2_subdev *sd,
937 struct v4l2_subdev_pad_config *cfg,
938 struct v4l2_subdev_format *fmt)
939 {
940 struct mipidphy_priv *priv = to_dphy_priv(sd);
941 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
942 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
943 int ret;
944 /*
945 * Do not allow format changes and just relay whatever
946 * set currently in the sensor.
947 */
948 if (!sensor_sd)
949 return -ENODEV;
950 ret = v4l2_subdev_call(sensor_sd, pad, get_fmt, NULL, fmt);
951 if (!ret && fmt->pad == 0)
952 sensor->format = fmt->format;
953 return ret;
954 }
955
mipidphy_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)956 static int mipidphy_get_selection(struct v4l2_subdev *sd,
957 struct v4l2_subdev_pad_config *cfg,
958 struct v4l2_subdev_selection *sel)
959 {
960 struct v4l2_subdev *sensor = get_remote_sensor(sd);
961
962 return v4l2_subdev_call(sensor, pad, get_selection, NULL, sel);
963 }
964
965 static const struct v4l2_subdev_pad_ops mipidphy_subdev_pad_ops = {
966 .set_fmt = mipidphy_get_set_fmt,
967 .get_fmt = mipidphy_get_set_fmt,
968 .get_selection = mipidphy_get_selection,
969 .get_mbus_config = mipidphy_g_mbus_config,
970 };
971
972 static const struct v4l2_subdev_core_ops mipidphy_core_ops = {
973 .s_power = mipidphy_s_power,
974 };
975
976 static const struct v4l2_subdev_video_ops mipidphy_video_ops = {
977 .g_frame_interval = mipidphy_g_frame_interval,
978 .s_stream = mipidphy_s_stream,
979 };
980
981 static const struct v4l2_subdev_ops mipidphy_subdev_ops = {
982 .core = &mipidphy_core_ops,
983 .video = &mipidphy_video_ops,
984 .pad = &mipidphy_subdev_pad_ops,
985 };
986
987 /* These tables must be sorted by .range_h ascending. */
988 static const struct hsfreq_range rk1808_rv1126_mipidphy_hsfreq_ranges[] = {
989 { 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
990 { 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
991 { 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
992 {1399, 0x23}, {1599, 0x2d}, {1799, 0x32}, {1999, 0x37},
993 {2199, 0x3c}, {2399, 0x41}, {2499, 0x46}
994 };
995
996 static const struct hsfreq_range rk3288_mipidphy_hsfreq_ranges[] = {
997 { 89, 0x00}, { 99, 0x10}, { 109, 0x20}, { 129, 0x01},
998 { 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12},
999 { 199, 0x22}, { 219, 0x03}, { 239, 0x13}, { 249, 0x23},
1000 { 269, 0x04}, { 299, 0x14}, { 329, 0x05}, { 359, 0x15},
1001 { 399, 0x25}, { 449, 0x06}, { 499, 0x16}, { 549, 0x07},
1002 { 599, 0x17}, { 649, 0x08}, { 699, 0x18}, { 749, 0x09},
1003 { 799, 0x19}, { 849, 0x29}, { 899, 0x39}, { 949, 0x0a},
1004 { 999, 0x1a}
1005 };
1006
1007 static const struct hsfreq_range rk3326_mipidphy_hsfreq_ranges[] = {
1008 { 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
1009 { 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
1010 { 699, 0x08}, { 799, 0x09}, { 899, 0x0a}, {1099, 0x0b},
1011 {1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
1012 };
1013
1014 static const struct hsfreq_range rk3368_mipidphy_hsfreq_ranges[] = {
1015 { 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
1016 { 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
1017 { 699, 0x08}, { 799, 0x09}, { 899, 0x0a}, {1099, 0x0b},
1018 {1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
1019 };
1020
1021 static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = {
1022 { 89, 0x00}, { 99, 0x10}, { 109, 0x20}, { 129, 0x01},
1023 { 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12},
1024 { 199, 0x22}, { 219, 0x03}, { 239, 0x13}, { 249, 0x23},
1025 { 269, 0x04}, { 299, 0x14}, { 329, 0x05}, { 359, 0x15},
1026 { 399, 0x25}, { 449, 0x06}, { 499, 0x16}, { 549, 0x07},
1027 { 599, 0x17}, { 649, 0x08}, { 699, 0x18}, { 749, 0x09},
1028 { 799, 0x19}, { 849, 0x29}, { 899, 0x39}, { 949, 0x0a},
1029 { 999, 0x1a}, {1049, 0x2a}, {1099, 0x3a}, {1149, 0x0b},
1030 {1199, 0x1b}, {1249, 0x2b}, {1299, 0x3b}, {1349, 0x0c},
1031 {1399, 0x1c}, {1449, 0x2c}, {1500, 0x3c}
1032 };
1033
1034 static const char * const rk1808_mipidphy_clks[] = {
1035 "pclk",
1036 };
1037
1038 static const char * const rk3288_mipidphy_clks[] = {
1039 "dphy-ref",
1040 "pclk",
1041 };
1042
1043 static const char * const rk3326_mipidphy_clks[] = {
1044 "dphy-ref",
1045 };
1046
1047 static const char * const rk3368_mipidphy_clks[] = {
1048 "pclk_dphyrx",
1049 };
1050
1051 static const char * const rk3399_mipidphy_clks[] = {
1052 "dphy-ref",
1053 "dphy-cfg",
1054 "grf",
1055 "pclk_mipi_dsi",
1056 };
1057
1058 static const char * const rv1126_mipidphy_clks[] = {
1059 "pclk",
1060 };
1061
default_mipidphy_individual_init(struct mipidphy_priv * priv)1062 static void default_mipidphy_individual_init(struct mipidphy_priv *priv)
1063 {
1064 }
1065
rk3368_mipidphy_individual_init(struct mipidphy_priv * priv)1066 static void rk3368_mipidphy_individual_init(struct mipidphy_priv *priv)
1067 {
1068 /* isp select */
1069 write_grf_reg(priv, GRF_ISP_MIPI_CSI_HOST_SEL, 1);
1070 }
1071
rk3399_mipidphy_individual_init(struct mipidphy_priv * priv)1072 static void rk3399_mipidphy_individual_init(struct mipidphy_priv *priv)
1073 {
1074 /*
1075 * According to the sequence of RK3399_TXRX_DPHY, the setting of isp0 mipi
1076 * will affect txrx dphy in default state of grf_soc_con24.
1077 */
1078 write_grf_reg(priv, GRF_DPHY_TX1RX1_SRC_SEL, 0);
1079 write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0);
1080 write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 0);
1081
1082 write_grf_reg(priv, GRF_DVP_V18SEL, 0x1);
1083 }
1084
rv1126_mipidphy_individual_init(struct mipidphy_priv * priv)1085 static void rv1126_mipidphy_individual_init(struct mipidphy_priv *priv)
1086 {
1087 struct device *dev = priv->dev;
1088 struct device_node *parent = dev->of_node;
1089 struct device_node *remote = NULL;
1090 u8 val, sel;
1091
1092 priv->grf_regs = priv->phy_index ?
1093 rv1126_grf_dphy1_regs : rv1126_grf_dphy0_regs;
1094 val = read_grf_reg(priv, GRF_DPHY_SEL);
1095 /* get port1 remote endpoint info */
1096 remote = of_graph_get_remote_node(parent, 1, 0);
1097 if (remote) {
1098 if (strstr(remote->name, "isp"))
1099 sel = !priv->phy_index ? 0 : RV1126_GRF_PHY1_SEL_ISP;
1100 else
1101 sel = !priv->phy_index ? 0 :
1102 RV1126_GRF_PHY1_SEL_CIF | RV1126_GRF_PHY1_SEL_CIFLITE;
1103 of_node_put(remote);
1104 write_grf_reg(priv, GRF_DPHY_SEL, val | sel);
1105 }
1106 }
1107
mipidphy_rx_stream_on(struct mipidphy_priv * priv,struct v4l2_subdev * sd)1108 static int mipidphy_rx_stream_on(struct mipidphy_priv *priv,
1109 struct v4l2_subdev *sd)
1110 {
1111 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
1112 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
1113 const struct dphy_drv_data *drv_data = priv->drv_data;
1114 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
1115 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
1116 int i, hsfreq = 0;
1117
1118 for (i = 0; i < num_hsfreq_ranges; i++) {
1119 if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
1120 hsfreq = hsfreq_ranges[i].cfg_bit;
1121 break;
1122 }
1123 }
1124
1125 if (i == num_hsfreq_ranges) {
1126 i = num_hsfreq_ranges - 1;
1127 dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps",
1128 priv->data_rate_mbps, hsfreq_ranges[i].range_h + 1);
1129 hsfreq = hsfreq_ranges[i].cfg_bit;
1130 }
1131
1132 /* RK3288 isp connected to phy0-rx */
1133 write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 0);
1134
1135 /* Belowed is the sequence of mipi configuration */
1136 /* Step1: set RSTZ = 1'b0, phy0 controlled by isp0 */
1137
1138 /* Step2: set SHUTDOWNZ = 1'b0, controlled by isp0 */
1139
1140 /* Step3: set TESTCLEAR = 1'b1 */
1141 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
1142 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 1);
1143 usleep_range(100, 150);
1144
1145 /* Step4: apply REFCLK signal with the appropriate frequency */
1146
1147 /* Step5: apply CFG_CLK signal with the appropriate frequency */
1148
1149 /* Step6: set MASTERSLAVEZ = 1'b0 (for SLAVE), phy0 default is slave */
1150
1151 /* Step7: set BASEDIR_N = 1’b1 (for SLAVE), phy0 default is slave */
1152
1153 /*
1154 * Step8: set all REQUEST inputs to zero, need to wait 15ns:
1155 * step8.1:set lan turndisab as 1
1156 * step8.2:set lan turnrequest as 0
1157 */
1158 write_grf_reg(priv, GRF_DPHY_RX0_TURNDISABLE, 0xf);
1159 write_grf_reg(priv, GRF_DPHY_RX0_FORCERXMODE, 0);
1160 write_grf_reg(priv, GRF_DPHY_RX0_TURNREQUEST, 0);
1161 usleep_range(100, 150);
1162
1163 /* Step9: set TESTCLR to low, need to wait 15ns */
1164 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 0);
1165 usleep_range(100, 150);
1166
1167 /*
1168 * Step10: configure Test Code 0x44 hsfreqrange according to values
1169 * step10.1:set clock lane
1170 * step10.2:set hsfreqrange by lane0(test code 0x44)
1171 */
1172 hsfreq <<= 1;
1173 mipidphy0_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
1174 mipidphy0_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq);
1175 mipidphy0_wr_reg(priv, LANE1_HS_RX_CONTROL, hsfreq);
1176 mipidphy0_wr_reg(priv, LANE2_HS_RX_CONTROL, hsfreq);
1177 mipidphy0_wr_reg(priv, LANE3_HS_RX_CONTROL, hsfreq);
1178
1179 /* Step11: Configure analog references: of Test Code 0x22 */
1180
1181 /* Step12: Set ENABLE_N=1'b1, need to wait 5ns */
1182 /* set lane num */
1183 write_grf_reg(priv, GRF_DPHY_RX0_ENABLE, GENMASK(sensor->lanes - 1, 0));
1184
1185 /* Step13: Set SHUTDOWNZ=1'b1, controlled by isp need to wait 5ns */
1186
1187 /* Step14: Set RSTZ=1'b1, controlled by isp */
1188
1189 /*
1190 * Step15: Wait until STOPSTATEDATA_N & STOPSTATECLK
1191 * outputs are asserted
1192 */
1193
1194 usleep_range(100, 150);
1195
1196 return 0;
1197 }
1198
mipidphy_txrx_stream_on(struct mipidphy_priv * priv,struct v4l2_subdev * sd)1199 static int mipidphy_txrx_stream_on(struct mipidphy_priv *priv,
1200 struct v4l2_subdev *sd)
1201 {
1202 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
1203 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
1204 const struct dphy_drv_data *drv_data = priv->drv_data;
1205 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
1206 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
1207 int i, hsfreq = 0;
1208
1209 for (i = 0; i < num_hsfreq_ranges; i++) {
1210 if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
1211 hsfreq = hsfreq_ranges[i].cfg_bit;
1212 break;
1213 }
1214 }
1215
1216 if (i == num_hsfreq_ranges) {
1217 i = num_hsfreq_ranges - 1;
1218 dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps",
1219 priv->data_rate_mbps, hsfreq_ranges[i].range_h + 1);
1220 hsfreq = hsfreq_ranges[i].cfg_bit;
1221 }
1222
1223 /*
1224 *Config rk3288:
1225 *step1:rk3288 isp connected to phy1-rx
1226 *step2:rk3288 phy1-rx test bus connected to csi host
1227 *step3:rk3288 phy1-rx source selected as: isp = 1'b1,csi-host = 1'b0
1228 */
1229 write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 1);
1230 write_grf_reg(priv, GRF_DSI_CSI_TESTBUS_SEL, 1);
1231 write_grf_reg(priv, GRF_DPHY_RX1_SRC_SEL, 1);
1232
1233 /*
1234 * Config rk3399：
1235 * step1:rk3399 phy1-rx source selected as:1'b0=isp1,1'b1=isp0
1236 */
1237 write_grf_reg(priv, GRF_DPHY_TX1RX1_SRC_SEL, 0);
1238
1239 /* Belowed is the sequence of mipi configuration */
1240 /* Step1: set RSTZ = 1'b0, phy1-rx controlled by isp */
1241
1242 /* Step2: set SHUTDOWNZ = 1'b0, phy1-rx controlled by isp */
1243
1244 /* Step3: set TESTCLR= 1'b1,TESTCLK=1'b1 */
1245 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, PHY_TESTCLR | PHY_TESTCLK);
1246 usleep_range(100, 150);
1247
1248 /* Step4: apply REFCLK signal with the appropriate frequency */
1249
1250 /* Step5: apply CFG_CLK signal with the appropriate frequency */
1251
1252 /*
1253 * Step6: set MASTERSLAVEZ = 1'b0 (for SLAVE),
1254 * phy1 is set as slave,controlled by isp
1255 */
1256 write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0);
1257
1258 /*
1259 * Step7: set BASEDIR_N = 1’b1 (for SLAVE),
1260 * phy1 is set as slave,controlled by isp
1261 */
1262 write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 1);
1263
1264 /* Step8: set all REQUEST inputs to zero, need to wait 15ns */
1265 write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCERXMODE, 0);
1266 write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCETXSTOPMODE, 0);
1267 write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNREQUEST, 0);
1268 write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNDISABLE, 0xf);
1269 usleep_range(100, 150);
1270
1271 /* Step9: set TESTCLR=1'b0,TESTCLK=1'b1 need to wait 15ns */
1272 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, PHY_TESTCLK);
1273 usleep_range(100, 150);
1274
1275 /*
1276 * Step10: configure Test Code 0x44 hsfreqrange according to values
1277 * step10.1:set clock lane
1278 * step10.2:set hsfreqrange by lane0(test code 0x44)
1279 */
1280 hsfreq <<= 1;
1281 mipidphy1_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
1282 mipidphy1_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq);
1283 mipidphy1_wr_reg(priv, LANE1_HS_RX_CONTROL, 0);
1284 mipidphy1_wr_reg(priv, LANE2_HS_RX_CONTROL, 0);
1285 mipidphy1_wr_reg(priv, LANE3_HS_RX_CONTROL, 0);
1286
1287 /* Step11: Configure analog references: of Test Code 0x22 */
1288
1289 /*
1290 * Step12: Set ENABLE_N=1'b1, need to wait 5ns
1291 * Set lane num:
1292 * for 3288,controlled by isp,enable lanes actually
1293 * is set by grf_soc_con9[12:15];
1294 * for 3399,controlled by isp1,enable lanes actually
1295 * is set by isp1,
1296 * if run 3399 here operates grf_soc_con23[0:3]
1297 */
1298 write_grf_reg(priv, GRF_DPHY_TX1RX1_ENABLE,
1299 GENMASK(sensor->lanes - 1, 0));
1300
1301 /*
1302 * Step13:Set SHUTDOWNZ=1'b1, phy1-rx controlled by isp,
1303 * need to wait 5ns
1304 */
1305
1306 /* Step14:Set RSTZ=1'b1, phy1-rx controlled by isp*/
1307
1308 /*
1309 * Step15:Wait until STOPSTATEDATA_N & STOPSTATECLK
1310 * outputs are asserted
1311 */
1312
1313 usleep_range(100, 150);
1314
1315 return 0;
1316 }
1317
csi_mipidphy_stream_on(struct mipidphy_priv * priv,struct v4l2_subdev * sd)1318 static int csi_mipidphy_stream_on(struct mipidphy_priv *priv,
1319 struct v4l2_subdev *sd)
1320 {
1321 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
1322 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
1323 const struct dphy_drv_data *drv_data = priv->drv_data;
1324 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
1325 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
1326 int i, hsfreq = 0;
1327 u32 val = 0;
1328
1329 write_grf_reg(priv, GRF_DVP_V18SEL, 0x1);
1330
1331 /* phy start */
1332 write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe4);
1333
1334 /* set data lane num and enable clock lane */
1335 write_csiphy_reg(priv, CSIPHY_CTRL_LANE_ENABLE,
1336 ((GENMASK(sensor->lanes - 1, 0) << MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) |
1337 (0x1 << MIPI_CSI_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT) | 0x1));
1338
1339 /* Reset dphy analog part */
1340 write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe0);
1341 usleep_range(500, 1000);
1342
1343 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
1344 /* Reset dphy digital part */
1345 write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1e);
1346 write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1f);
1347 } else {
1348 /* Disable MIPI internal logical and switch to LVDS bank */
1349 write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x3e);
1350 /* Enable LVDS mode */
1351 write_csiphy_reg(priv, CSIPHY_MIPI_LVDS_MODEL, 0x4);
1352 switch (sensor->format.code) {
1353 case MEDIA_BUS_FMT_Y12_1X12:
1354 case MEDIA_BUS_FMT_SRGGB12_1X12:
1355 case MEDIA_BUS_FMT_SBGGR12_1X12:
1356 case MEDIA_BUS_FMT_SGBRG12_1X12:
1357 case MEDIA_BUS_FMT_SGRBG12_1X12:
1358 val = 0x1f; //12bit
1359 break;
1360 case MEDIA_BUS_FMT_Y10_1X10:
1361 case MEDIA_BUS_FMT_SBGGR10_1X10:
1362 case MEDIA_BUS_FMT_SRGGB10_1X10:
1363 case MEDIA_BUS_FMT_SGBRG10_1X10:
1364 case MEDIA_BUS_FMT_SGRBG10_1X10:
1365 val = 0xf; //10bit
1366 break;
1367 default:
1368 val = 0x2f; //8bit
1369 }
1370 /* Enable LVDS internal logical and select bit mode */
1371 write_csiphy_reg(priv, CSIPHY_LVDS_MODE, val);
1372 }
1373
1374 /* not into receive mode/wait stopstate */
1375 write_grf_reg(priv, GRF_DPHY_CSIPHY_FORCERXMODE, 0x0);
1376
1377 /* enable calibration */
1378 if (priv->data_rate_mbps > 1500) {
1379 write_csiphy_reg(priv, CSIPHY_CLK_CALIB_ENABLE, 0x80);
1380 if (sensor->lanes > 0x00)
1381 write_csiphy_reg(priv, CSIPHY_LANE0_CALIB_ENABLE, 0x80);
1382 if (sensor->lanes > 0x01)
1383 write_csiphy_reg(priv, CSIPHY_LANE1_CALIB_ENABLE, 0x80);
1384 if (sensor->lanes > 0x02)
1385 write_csiphy_reg(priv, CSIPHY_LANE2_CALIB_ENABLE, 0x80);
1386 if (sensor->lanes > 0x03)
1387 write_csiphy_reg(priv, CSIPHY_LANE3_CALIB_ENABLE, 0x80);
1388 }
1389
1390 /* set clock lane and data lane */
1391 for (i = 0; i < num_hsfreq_ranges; i++) {
1392 if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
1393 hsfreq = hsfreq_ranges[i].cfg_bit;
1394 break;
1395 }
1396 }
1397
1398 if (i == num_hsfreq_ranges) {
1399 i = num_hsfreq_ranges - 1;
1400 dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps",
1401 priv->data_rate_mbps, hsfreq_ranges[i].range_h + 1);
1402 hsfreq = hsfreq_ranges[i].cfg_bit;
1403 }
1404
1405 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_CLOCK);
1406 if (sensor->lanes > 0x00)
1407 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA0);
1408 if (sensor->lanes > 0x01)
1409 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA1);
1410 if (sensor->lanes > 0x02)
1411 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA2);
1412 if (sensor->lanes > 0x03)
1413 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA3);
1414
1415 write_grf_reg(priv, GRF_DPHY_CLK_INV_SEL, 0x1);
1416 write_grf_reg(priv, GRF_DPHY_CSIPHY_CLKLANE_EN, 0x1);
1417 write_grf_reg(priv, GRF_DPHY_CSIPHY_DATALANE_EN,
1418 GENMASK(sensor->lanes - 1, 0));
1419 return 0;
1420 }
1421
csi_mipidphy_stream_off(struct mipidphy_priv * priv,struct v4l2_subdev * sd)1422 static int csi_mipidphy_stream_off(struct mipidphy_priv *priv,
1423 struct v4l2_subdev *sd)
1424 {
1425 /* disable all lanes */
1426 write_csiphy_reg(priv, CSIPHY_CTRL_LANE_ENABLE, 0x01);
1427 /* disable pll and ldo */
1428 write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe3);
1429 usleep_range(500, 1000);
1430
1431 return 0;
1432 }
1433
1434 static const struct dphy_drv_data rk1808_mipidphy_drv_data = {
1435 .clks = rk1808_mipidphy_clks,
1436 .num_clks = ARRAY_SIZE(rk1808_mipidphy_clks),
1437 .hsfreq_ranges = rk1808_rv1126_mipidphy_hsfreq_ranges,
1438 .num_hsfreq_ranges = ARRAY_SIZE(rk1808_rv1126_mipidphy_hsfreq_ranges),
1439 .grf_regs = rk1808_grf_dphy_regs,
1440 .csiphy_regs = rk1808_csiphy_regs,
1441 .ctl_type = MIPI_DPHY_CTL_CSI_HOST,
1442 .individual_init = default_mipidphy_individual_init,
1443 .chip_id = CHIP_ID_RK1808,
1444 };
1445
1446 static const struct dphy_drv_data rk3288_mipidphy_drv_data = {
1447 .clks = rk3288_mipidphy_clks,
1448 .num_clks = ARRAY_SIZE(rk3288_mipidphy_clks),
1449 .hsfreq_ranges = rk3288_mipidphy_hsfreq_ranges,
1450 .num_hsfreq_ranges = ARRAY_SIZE(rk3288_mipidphy_hsfreq_ranges),
1451 .grf_regs = rk3288_grf_dphy_regs,
1452 .txrx_regs = rk3288_txrx_regs,
1453 .ctl_type = MIPI_DPHY_CTL_GRF_ONLY,
1454 .individual_init = default_mipidphy_individual_init,
1455 .chip_id = CHIP_ID_RK3288,
1456 };
1457
1458 static const struct dphy_drv_data rk3326_mipidphy_drv_data = {
1459 .clks = rk3326_mipidphy_clks,
1460 .num_clks = ARRAY_SIZE(rk3326_mipidphy_clks),
1461 .hsfreq_ranges = rk3326_mipidphy_hsfreq_ranges,
1462 .num_hsfreq_ranges = ARRAY_SIZE(rk3326_mipidphy_hsfreq_ranges),
1463 .grf_regs = rk3326_grf_dphy_regs,
1464 .csiphy_regs = rk3326_csiphy_regs,
1465 .ctl_type = MIPI_DPHY_CTL_CSI_HOST,
1466 .individual_init = default_mipidphy_individual_init,
1467 .chip_id = CHIP_ID_RK3326,
1468 };
1469
1470 static const struct dphy_drv_data rk3368_mipidphy_drv_data = {
1471 .clks = rk3368_mipidphy_clks,
1472 .num_clks = ARRAY_SIZE(rk3368_mipidphy_clks),
1473 .hsfreq_ranges = rk3368_mipidphy_hsfreq_ranges,
1474 .num_hsfreq_ranges = ARRAY_SIZE(rk3368_mipidphy_hsfreq_ranges),
1475 .grf_regs = rk3368_grf_dphy_regs,
1476 .csiphy_regs = rk3368_csiphy_regs,
1477 .ctl_type = MIPI_DPHY_CTL_CSI_HOST,
1478 .individual_init = rk3368_mipidphy_individual_init,
1479 .chip_id = CHIP_ID_RK3368,
1480 };
1481
1482 static const struct dphy_drv_data rk3399_mipidphy_drv_data = {
1483 .clks = rk3399_mipidphy_clks,
1484 .num_clks = ARRAY_SIZE(rk3399_mipidphy_clks),
1485 .hsfreq_ranges = rk3399_mipidphy_hsfreq_ranges,
1486 .num_hsfreq_ranges = ARRAY_SIZE(rk3399_mipidphy_hsfreq_ranges),
1487 .grf_regs = rk3399_grf_dphy_regs,
1488 .txrx_regs = rk3399_txrx_regs,
1489 .ctl_type = MIPI_DPHY_CTL_GRF_ONLY,
1490 .individual_init = rk3399_mipidphy_individual_init,
1491 .chip_id = CHIP_ID_RK3399,
1492 };
1493
1494 static const struct dphy_drv_data rv1126_mipidphy_drv_data = {
1495 .clks = rv1126_mipidphy_clks,
1496 .num_clks = ARRAY_SIZE(rv1126_mipidphy_clks),
1497 .hsfreq_ranges = rk1808_rv1126_mipidphy_hsfreq_ranges,
1498 .num_hsfreq_ranges = ARRAY_SIZE(rk1808_rv1126_mipidphy_hsfreq_ranges),
1499 .csiphy_regs = rv1126_csiphy_regs,
1500 .ctl_type = MIPI_DPHY_CTL_CSI_HOST,
1501 .individual_init = rv1126_mipidphy_individual_init,
1502 .chip_id = CHIP_ID_RK1126,
1503 };
1504
1505 static const struct of_device_id rockchip_mipidphy_match_id[] = {
1506 {
1507 .compatible = "rockchip,rk1808-mipi-dphy-rx",
1508 .data = &rk1808_mipidphy_drv_data,
1509 },
1510 {
1511 .compatible = "rockchip,rk3288-mipi-dphy",
1512 .data = &rk3288_mipidphy_drv_data,
1513 },
1514 {
1515 .compatible = "rockchip,rk3326-mipi-dphy",
1516 .data = &rk3326_mipidphy_drv_data,
1517 },
1518 {
1519 .compatible = "rockchip,rk3368-mipi-dphy",
1520 .data = &rk3368_mipidphy_drv_data,
1521 },
1522 {
1523 .compatible = "rockchip,rk3399-mipi-dphy",
1524 .data = &rk3399_mipidphy_drv_data,
1525 },
1526 {
1527 .compatible = "rockchip,rv1126-csi-dphy",
1528 .data = &rv1126_mipidphy_drv_data,
1529 },
1530 {}
1531 };
1532 MODULE_DEVICE_TABLE(of, rockchip_mipidphy_match_id);
1533
1534 /* The .bound() notifier callback when a match is found */
1535 static int
rockchip_mipidphy_notifier_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * sd,struct v4l2_async_subdev * asd)1536 rockchip_mipidphy_notifier_bound(struct v4l2_async_notifier *notifier,
1537 struct v4l2_subdev *sd,
1538 struct v4l2_async_subdev *asd)
1539 {
1540 struct mipidphy_priv *priv = container_of(notifier,
1541 struct mipidphy_priv,
1542 notifier);
1543 struct sensor_async_subdev *s_asd = container_of(asd,
1544 struct sensor_async_subdev, asd);
1545 struct mipidphy_sensor *sensor;
1546 unsigned int pad, ret;
1547
1548 if (priv->num_sensors == ARRAY_SIZE(priv->sensors))
1549 return -EBUSY;
1550
1551 sensor = &priv->sensors[priv->num_sensors++];
1552 sensor->lanes = s_asd->lanes;
1553 sensor->mbus = s_asd->mbus;
1554 sensor->sd = sd;
1555 dev_info(priv->dev, "match %s:bus type %d\n", sd->name, s_asd->mbus.type);
1556
1557 for (pad = 0; pad < sensor->sd->entity.num_pads; pad++)
1558 if (sensor->sd->entity.pads[pad].flags & MEDIA_PAD_FL_SOURCE)
1559 break;
1560
1561 if (pad == sensor->sd->entity.num_pads) {
1562 dev_err(priv->dev,
1563 "failed to find src pad for %s\n",
1564 sensor->sd->name);
1565
1566 return -ENXIO;
1567 }
1568
1569 ret = media_create_pad_link(
1570 &sensor->sd->entity, pad,
1571 &priv->sd.entity, MIPI_DPHY_RX_PAD_SINK,
1572 priv->num_sensors != 1 ? 0 : MEDIA_LNK_FL_ENABLED);
1573 if (ret) {
1574 dev_err(priv->dev,
1575 "failed to create link for %s\n",
1576 sensor->sd->name);
1577 return ret;
1578 }
1579
1580 return 0;
1581 }
1582
1583 /* The .unbind callback */
1584 static void
rockchip_mipidphy_notifier_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * sd,struct v4l2_async_subdev * asd)1585 rockchip_mipidphy_notifier_unbind(struct v4l2_async_notifier *notifier,
1586 struct v4l2_subdev *sd,
1587 struct v4l2_async_subdev *asd)
1588 {
1589 struct mipidphy_priv *priv = container_of(notifier,
1590 struct mipidphy_priv,
1591 notifier);
1592 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sd);
1593
1594 sensor->sd = NULL;
1595 }
1596
1597 static const struct
1598 v4l2_async_notifier_operations rockchip_mipidphy_async_ops = {
1599 .bound = rockchip_mipidphy_notifier_bound,
1600 .unbind = rockchip_mipidphy_notifier_unbind,
1601 };
1602
rockchip_mipidphy_fwnode_parse(struct device * dev,struct v4l2_fwnode_endpoint * vep,struct v4l2_async_subdev * asd)1603 static int rockchip_mipidphy_fwnode_parse(struct device *dev,
1604 struct v4l2_fwnode_endpoint *vep,
1605 struct v4l2_async_subdev *asd)
1606 {
1607 struct sensor_async_subdev *s_asd =
1608 container_of(asd, struct sensor_async_subdev, asd);
1609 struct v4l2_mbus_config *config = &s_asd->mbus;
1610
1611 if (vep->base.port != 0) {
1612 dev_err(dev, "The PHY has only port 0\n");
1613 return -EINVAL;
1614 }
1615
1616 if (vep->bus_type == V4L2_MBUS_CSI2_DPHY) {
1617 config->type = V4L2_MBUS_CSI2_DPHY;
1618 config->flags = vep->bus.mipi_csi2.flags;
1619 s_asd->lanes = vep->bus.mipi_csi2.num_data_lanes;
1620 } else if (vep->bus_type == V4L2_MBUS_CCP2) {
1621 /* V4L2_MBUS_CCP2 for lvds */
1622 config->type = V4L2_MBUS_CCP2;
1623 s_asd->lanes = vep->bus.mipi_csi1.data_lane;
1624 } else {
1625 dev_err(dev, "Only CSI2 and CCP2 bus type is currently supported\n");
1626 return -EINVAL;
1627 }
1628
1629 switch (s_asd->lanes) {
1630 case 1:
1631 config->flags |= V4L2_MBUS_CSI2_1_LANE;
1632 break;
1633 case 2:
1634 config->flags |= V4L2_MBUS_CSI2_2_LANE;
1635 break;
1636 case 3:
1637 config->flags |= V4L2_MBUS_CSI2_3_LANE;
1638 break;
1639 case 4:
1640 config->flags |= V4L2_MBUS_CSI2_4_LANE;
1641 break;
1642 default:
1643 return -EINVAL;
1644 }
1645
1646 return 0;
1647 }
1648
rockchip_mipidphy_media_init(struct mipidphy_priv * priv)1649 static int rockchip_mipidphy_media_init(struct mipidphy_priv *priv)
1650 {
1651 int ret;
1652
1653 priv->pads[MIPI_DPHY_RX_PAD_SOURCE].flags =
1654 MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT;
1655 priv->pads[MIPI_DPHY_RX_PAD_SINK].flags =
1656 MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
1657 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1658 ret = media_entity_pads_init(&priv->sd.entity,
1659 MIPI_DPHY_RX_PADS_NUM, priv->pads);
1660 if (ret < 0)
1661 return ret;
1662
1663 v4l2_async_notifier_init(&priv->notifier);
1664
1665 ret = v4l2_async_notifier_parse_fwnode_endpoints_by_port(
1666 priv->dev, &priv->notifier,
1667 sizeof(struct sensor_async_subdev), 0,
1668 rockchip_mipidphy_fwnode_parse);
1669 if (ret < 0)
1670 return ret;
1671
1672 priv->sd.subdev_notifier = &priv->notifier;
1673 priv->notifier.ops = &rockchip_mipidphy_async_ops;
1674 ret = v4l2_async_subdev_notifier_register(&priv->sd, &priv->notifier);
1675 if (ret) {
1676 dev_err(priv->dev,
1677 "failed to register async notifier : %d\n", ret);
1678 v4l2_async_notifier_cleanup(&priv->notifier);
1679 return ret;
1680 }
1681
1682 return v4l2_async_register_subdev(&priv->sd);
1683 }
1684
rockchip_mipidphy_probe(struct platform_device * pdev)1685 static int rockchip_mipidphy_probe(struct platform_device *pdev)
1686 {
1687 struct device *dev = &pdev->dev;
1688 struct v4l2_subdev *sd;
1689 struct mipidphy_priv *priv;
1690 struct regmap *grf;
1691 struct resource *res;
1692 const struct of_device_id *of_id;
1693 const struct dphy_drv_data *drv_data;
1694 int i, ret;
1695
1696 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1697 if (!priv)
1698 return -ENOMEM;
1699 priv->dev = dev;
1700
1701 of_id = of_match_device(rockchip_mipidphy_match_id, dev);
1702 if (!of_id)
1703 return -EINVAL;
1704
1705 grf = syscon_node_to_regmap(dev->parent->of_node);
1706 if (IS_ERR(grf)) {
1707 grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1708 "rockchip,grf");
1709 if (IS_ERR(grf)) {
1710 dev_err(dev, "Can't find GRF syscon\n");
1711 return -ENODEV;
1712 }
1713 }
1714 priv->regmap_grf = grf;
1715
1716 priv->phy_index = of_alias_get_id(dev->of_node, "dphy");
1717 if (priv->phy_index < 0)
1718 priv->phy_index = 0;
1719
1720 drv_data = of_id->data;
1721 for (i = 0; i < drv_data->num_clks; i++) {
1722 priv->clks[i] = devm_clk_get(dev, drv_data->clks[i]);
1723
1724 if (IS_ERR(priv->clks[i]))
1725 dev_dbg(dev, "Failed to get %s\n", drv_data->clks[i]);
1726 }
1727
1728 priv->grf_regs = drv_data->grf_regs;
1729 priv->txrx_regs = drv_data->txrx_regs;
1730 priv->csiphy_regs = drv_data->csiphy_regs;
1731 priv->drv_data = drv_data;
1732 if (drv_data->ctl_type == MIPI_DPHY_CTL_CSI_HOST) {
1733 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1734 priv->csihost_base_addr = devm_ioremap_resource(dev, res);
1735 priv->stream_on = csi_mipidphy_stream_on;
1736 priv->stream_off = csi_mipidphy_stream_off;
1737 } else {
1738 priv->stream_on = mipidphy_txrx_stream_on;
1739 priv->txrx_base_addr = NULL;
1740 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1741 priv->txrx_base_addr = devm_ioremap_resource(dev, res);
1742 if (IS_ERR(priv->txrx_base_addr))
1743 priv->stream_on = mipidphy_rx_stream_on;
1744 priv->stream_off = NULL;
1745 }
1746
1747 sd = &priv->sd;
1748 mutex_init(&priv->mutex);
1749 v4l2_subdev_init(sd, &mipidphy_subdev_ops);
1750 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1751 snprintf(sd->name, sizeof(sd->name), "rockchip-mipi-dphy-rx");
1752 sd->dev = dev;
1753
1754 platform_set_drvdata(pdev, &sd->entity);
1755
1756 ret = rockchip_mipidphy_media_init(priv);
1757 if (ret < 0)
1758 goto destroy_mutex;
1759
1760 pm_runtime_enable(&pdev->dev);
1761 drv_data->individual_init(priv);
1762 return 0;
1763
1764 destroy_mutex:
1765 mutex_destroy(&priv->mutex);
1766 return 0;
1767 }
1768
rockchip_mipidphy_remove(struct platform_device * pdev)1769 static int rockchip_mipidphy_remove(struct platform_device *pdev)
1770 {
1771 struct media_entity *me = platform_get_drvdata(pdev);
1772 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
1773 struct mipidphy_priv *priv = platform_get_drvdata(pdev);
1774
1775 media_entity_cleanup(&sd->entity);
1776
1777 pm_runtime_disable(&pdev->dev);
1778 mutex_destroy(&priv->mutex);
1779 return 0;
1780 }
1781
1782 static const struct dev_pm_ops rockchip_mipidphy_pm_ops = {
1783 SET_RUNTIME_PM_OPS(mipidphy_runtime_suspend,
1784 mipidphy_runtime_resume, NULL)
1785 };
1786
1787 static struct platform_driver rockchip_isp_mipidphy_driver = {
1788 .probe = rockchip_mipidphy_probe,
1789 .remove = rockchip_mipidphy_remove,
1790 .driver = {
1791 .name = "rockchip-mipi-dphy-rx",
1792 .pm = &rockchip_mipidphy_pm_ops,
1793 .of_match_table = rockchip_mipidphy_match_id,
1794 },
1795 };
1796
1797 module_platform_driver(rockchip_isp_mipidphy_driver);
1798 MODULE_AUTHOR("Rockchip Camera/ISP team");
1799 MODULE_DESCRIPTION("Rockchip MIPI RX DPHY driver");
1800 MODULE_LICENSE("Dual BSD/GPL");
1801