1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2 /*
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
4 *
5 * author:
6 * Alpha Lin, alpha.lin@rock-chips.com
7 * Randy Li, randy.li@rock-chips.com
8 * Ding Wei, leo.ding@rock-chips.com
9 *
10 */
11 #ifndef __ROCKCHIP_MPP_COMMON_H__
12 #define __ROCKCHIP_MPP_COMMON_H__
13
14 #include <linux/cdev.h>
15 #include <linux/clk.h>
16 #include <linux/dma-buf.h>
17 #include <linux/kfifo.h>
18 #include <linux/types.h>
19 #include <linux/time.h>
20 #include <linux/workqueue.h>
21 #include <linux/kthread.h>
22 #include <linux/reset.h>
23 #include <linux/irqreturn.h>
24 #include <linux/poll.h>
25 #include <soc/rockchip/pm_domains.h>
26
27 #define MHZ (1000 * 1000)
28
29 #define MPP_MAX_MSG_NUM (16)
30 #define MPP_MAX_REG_TRANS_NUM (60)
31 #define MPP_MAX_TASK_CAPACITY (16)
32 /* define flags for mpp_request */
33 #define MPP_FLAGS_MULTI_MSG (0x00000001)
34 #define MPP_FLAGS_LAST_MSG (0x00000002)
35 #define MPP_FLAGS_REG_FD_NO_TRANS (0x00000004)
36 #define MPP_FLAGS_SCL_FD_NO_TRANS (0x00000008)
37 #define MPP_FLAGS_REG_NO_OFFSET (0x00000010)
38 #define MPP_FLAGS_SECURE_MODE (0x00010000)
39
40 /* grf mask for get value */
41 #define MPP_GRF_VAL_MASK (0xFFFF)
42
43 /* max 4 cores supported */
44 #define MPP_MAX_CORE_NUM (4)
45
46 /**
47 * Device type: classified by hardware feature
48 */
49 enum MPP_DEVICE_TYPE {
50 MPP_DEVICE_VDPU1 = 0, /* 0x00000001 */
51 MPP_DEVICE_VDPU2 = 1, /* 0x00000002 */
52 MPP_DEVICE_VDPU1_PP = 2, /* 0x00000004 */
53 MPP_DEVICE_VDPU2_PP = 3, /* 0x00000008 */
54
55 MPP_DEVICE_HEVC_DEC = 8, /* 0x00000100 */
56 MPP_DEVICE_RKVDEC = 9, /* 0x00000200 */
57 MPP_DEVICE_AVSPLUS_DEC = 12, /* 0x00001000 */
58 MPP_DEVICE_JPGDEC = 13, /* 0x00002000 */
59
60 MPP_DEVICE_RKVENC = 16, /* 0x00010000 */
61 MPP_DEVICE_VEPU1 = 17, /* 0x00020000 */
62 MPP_DEVICE_VEPU2 = 18, /* 0x00040000 */
63 MPP_DEVICE_VEPU22 = 24, /* 0x01000000 */
64
65 MPP_DEVICE_IEP2 = 28, /* 0x10000000 */
66 MPP_DEVICE_BUTT,
67 };
68
69 /**
70 * Driver type: classified by driver
71 */
72 enum MPP_DRIVER_TYPE {
73 MPP_DRIVER_NULL = 0,
74 MPP_DRIVER_VDPU1,
75 MPP_DRIVER_VEPU1,
76 MPP_DRIVER_VDPU2,
77 MPP_DRIVER_VEPU2,
78 MPP_DRIVER_VEPU22,
79 MPP_DRIVER_RKVDEC,
80 MPP_DRIVER_RKVENC,
81 MPP_DRIVER_IEP,
82 MPP_DRIVER_IEP2,
83 MPP_DRIVER_JPGDEC,
84 MPP_DRIVER_RKVDEC2,
85 MPP_DRIVER_RKVENC2,
86 MPP_DRIVER_BUTT,
87 };
88
89 /**
90 * Command type: keep the same as user space
91 */
92 enum MPP_DEV_COMMAND_TYPE {
93 MPP_CMD_QUERY_BASE = 0,
94 MPP_CMD_QUERY_HW_SUPPORT = MPP_CMD_QUERY_BASE + 0,
95 MPP_CMD_QUERY_HW_ID = MPP_CMD_QUERY_BASE + 1,
96 MPP_CMD_QUERY_CMD_SUPPORT = MPP_CMD_QUERY_BASE + 2,
97 MPP_CMD_QUERY_BUTT,
98
99 MPP_CMD_INIT_BASE = 0x100,
100 MPP_CMD_INIT_CLIENT_TYPE = MPP_CMD_INIT_BASE + 0,
101 MPP_CMD_INIT_DRIVER_DATA = MPP_CMD_INIT_BASE + 1,
102 MPP_CMD_INIT_TRANS_TABLE = MPP_CMD_INIT_BASE + 2,
103 MPP_CMD_INIT_BUTT,
104
105 MPP_CMD_SEND_BASE = 0x200,
106 MPP_CMD_SET_REG_WRITE = MPP_CMD_SEND_BASE + 0,
107 MPP_CMD_SET_REG_READ = MPP_CMD_SEND_BASE + 1,
108 MPP_CMD_SET_REG_ADDR_OFFSET = MPP_CMD_SEND_BASE + 2,
109 MPP_CMD_SET_RCB_INFO = MPP_CMD_SEND_BASE + 3,
110 MPP_CMD_SEND_BUTT,
111
112 MPP_CMD_POLL_BASE = 0x300,
113 MPP_CMD_POLL_HW_FINISH = MPP_CMD_POLL_BASE + 0,
114 MPP_CMD_POLL_BUTT,
115
116 MPP_CMD_CONTROL_BASE = 0x400,
117 MPP_CMD_RESET_SESSION = MPP_CMD_CONTROL_BASE + 0,
118 MPP_CMD_TRANS_FD_TO_IOVA = MPP_CMD_CONTROL_BASE + 1,
119 MPP_CMD_RELEASE_FD = MPP_CMD_CONTROL_BASE + 2,
120 MPP_CMD_SEND_CODEC_INFO = MPP_CMD_CONTROL_BASE + 3,
121 MPP_CMD_CONTROL_BUTT,
122
123 MPP_CMD_BUTT,
124 };
125
126 enum MPP_CLOCK_MODE {
127 CLK_MODE_BASE = 0,
128 CLK_MODE_DEFAULT = CLK_MODE_BASE,
129 CLK_MODE_DEBUG,
130 CLK_MODE_REDUCE,
131 CLK_MODE_NORMAL,
132 CLK_MODE_ADVANCED,
133 CLK_MODE_BUTT,
134 };
135
136 enum MPP_RESET_TYPE {
137 RST_TYPE_BASE = 0,
138 RST_TYPE_A = RST_TYPE_BASE,
139 RST_TYPE_H,
140 RST_TYPE_NIU_A,
141 RST_TYPE_NIU_H,
142 RST_TYPE_CORE,
143 RST_TYPE_CABAC,
144 RST_TYPE_HEVC_CABAC,
145 RST_TYPE_BUTT,
146 };
147
148 enum ENC_INFO_TYPE {
149 ENC_INFO_BASE = 0,
150 ENC_INFO_WIDTH,
151 ENC_INFO_HEIGHT,
152 ENC_INFO_FORMAT,
153 ENC_INFO_FPS_IN,
154 ENC_INFO_FPS_OUT,
155 ENC_INFO_RC_MODE,
156 ENC_INFO_BITRATE,
157 ENC_INFO_GOP_SIZE,
158 ENC_INFO_FPS_CALC,
159 ENC_INFO_PROFILE,
160
161 ENC_INFO_BUTT,
162 };
163
164 enum DEC_INFO_TYPE {
165 DEC_INFO_BASE = 0,
166 DEC_INFO_WIDTH,
167 DEC_INFO_HEIGHT,
168 DEC_INFO_FORMAT,
169 DEC_INFO_BITDEPTH,
170 DEC_INFO_FPS,
171
172 DEC_INFO_BUTT,
173 };
174
175 enum CODEC_INFO_FLAGS {
176 CODEC_INFO_FLAG_NULL = 0,
177 CODEC_INFO_FLAG_NUMBER,
178 CODEC_INFO_FLAG_STRING,
179
180 CODEC_INFO_FLAG_BUTT,
181 };
182
183 /* data common struct for parse out */
184 struct mpp_request {
185 __u32 cmd;
186 __u32 flags;
187 __u32 size;
188 __u32 offset;
189 void __user *data;
190 };
191
192 /* struct use to collect task set and poll message */
193 struct mpp_task_msgs {
194 u32 flags;
195 u32 req_cnt;
196 struct mpp_request reqs[MPP_MAX_MSG_NUM];
197 u32 set_cnt;
198 u32 poll_cnt;
199 };
200
201 struct mpp_grf_info {
202 u32 offset;
203 u32 val;
204 struct regmap *grf;
205 };
206
207 /**
208 * struct for hardware info
209 */
210 struct mpp_hw_info {
211 /* register number */
212 u32 reg_num;
213 /* hardware id */
214 int reg_id;
215 u32 hw_id;
216 /* start index of register */
217 u32 reg_start;
218 /* end index of register */
219 u32 reg_end;
220 /* register of enable hardware */
221 int reg_en;
222 };
223
224 struct mpp_trans_info {
225 const int count;
226 const u16 * const table;
227 };
228
229 struct reg_offset_elem {
230 u32 index;
231 u32 offset;
232 };
233
234 struct reg_offset_info {
235 u32 cnt;
236 struct reg_offset_elem elem[MPP_MAX_REG_TRANS_NUM];
237 };
238
239 struct codec_info_elem {
240 __u32 type;
241 __u32 flag;
242 __u64 data;
243 };
244
245 struct mpp_clk_info {
246 struct clk *clk;
247
248 /* debug rate, from debug */
249 u32 debug_rate_hz;
250 /* normal rate, from dtsi */
251 u32 normal_rate_hz;
252 /* high performance rate, from dtsi */
253 u32 advanced_rate_hz;
254
255 u32 default_rate_hz;
256 u32 reduce_rate_hz;
257 /* record last used rate */
258 u32 used_rate_hz;
259 };
260
261 struct mpp_dev_var {
262 enum MPP_DEVICE_TYPE device_type;
263
264 /* info for each hardware */
265 struct mpp_hw_info *hw_info;
266 struct mpp_trans_info *trans_info;
267 struct mpp_hw_ops *hw_ops;
268 struct mpp_dev_ops *dev_ops;
269 };
270
271 struct mpp_mem_region {
272 struct list_head reg_link;
273 /* address for iommu */
274 dma_addr_t iova;
275 unsigned long len;
276 u32 reg_idx;
277 void *hdl;
278 int fd;
279 /* whether is dup import entity */
280 bool is_dup;
281 };
282
283 struct mpp_dma_session;
284
285 struct mpp_taskqueue;
286
287 struct mpp_dev {
288 struct device *dev;
289 const struct mpp_dev_var *var;
290 struct mpp_hw_ops *hw_ops;
291 struct mpp_dev_ops *dev_ops;
292
293 /* per-device work for attached taskqueue */
294 struct kthread_work work;
295 /* the flag for get/get/reduce freq */
296 bool auto_freq_en;
297 /* the flag for pmu idle request before device reset */
298 bool skip_idle;
299
300 /*
301 * The task capacity is the task queue length that hardware can accept.
302 * Default 1 means normal hardware can only accept one task at once.
303 */
304 u32 task_capacity;
305
306 int irq;
307 u32 irq_status;
308
309 void __iomem *reg_base;
310 struct mpp_grf_info *grf_info;
311 struct mpp_iommu_info *iommu_info;
312
313 atomic_t reset_request;
314 atomic_t session_index;
315 atomic_t task_count;
316 atomic_t task_index;
317 /* current task in running */
318 struct mpp_task *cur_task;
319 /* set session max buffers */
320 u32 session_max_buffers;
321 struct mpp_taskqueue *queue;
322 struct mpp_reset_group *reset_group;
323 /* point to MPP Service */
324 struct platform_device *pdev_srv;
325 struct mpp_service *srv;
326
327 /* multi-core data */
328 struct list_head queue_link;
329 s32 core_id;
330 };
331
332 struct mpp_task;
333
334 struct mpp_session {
335 enum MPP_DEVICE_TYPE device_type;
336 u32 index;
337 /* the session related device private data */
338 struct mpp_service *srv;
339 struct mpp_dev *mpp;
340 struct mpp_dma_session *dma;
341
342 /* lock for session task pending list */
343 struct mutex pending_lock;
344 /* task pending list in session */
345 struct list_head pending_list;
346
347 pid_t pid;
348 atomic_t task_count;
349 atomic_t release_request;
350 /* trans info set by user */
351 int trans_count;
352 u16 trans_table[MPP_MAX_REG_TRANS_NUM];
353 u32 msg_flags;
354 /* link to mpp_service session_list */
355 struct list_head service_link;
356 /* link to mpp_workqueue session_attach / session_detach */
357 struct list_head session_link;
358 /* private data */
359 void *priv;
360
361 /*
362 * session handler from mpp_dev_ops
363 * process_task - handle messages of sending task
364 * wait_result - handle messages of polling task
365 * deinit - handle session deinit
366 */
367 int (*process_task)(struct mpp_session *session,
368 struct mpp_task_msgs *msgs);
369 int (*wait_result)(struct mpp_session *session,
370 struct mpp_task_msgs *msgs);
371 void (*deinit)(struct mpp_session *session);
372 };
373
374 /* task state in work thread */
375 enum mpp_task_state {
376 TASK_STATE_PENDING = 0,
377 TASK_STATE_RUNNING = 1,
378 TASK_STATE_START = 2,
379 TASK_STATE_HANDLE = 3,
380 TASK_STATE_IRQ = 4,
381 TASK_STATE_FINISH = 5,
382 TASK_STATE_TIMEOUT = 6,
383 TASK_STATE_DONE = 7,
384
385 TASK_STATE_PREPARE = 8,
386 TASK_STATE_ABORT = 9,
387 TASK_STATE_ABORT_READY = 10,
388 TASK_STATE_PROC_DONE = 11,
389 };
390
391 /* The context for the a task */
392 struct mpp_task {
393 /* context belong to */
394 struct mpp_session *session;
395
396 /* link to pending list in session */
397 struct list_head pending_link;
398 /* link to done list in session */
399 struct list_head done_link;
400 /* link to list in taskqueue */
401 struct list_head queue_link;
402 /* The DMA buffer used in this task */
403 struct list_head mem_region_list;
404 u32 mem_count;
405 struct mpp_mem_region mem_regions[MPP_MAX_REG_TRANS_NUM];
406
407 /* state in the taskqueue */
408 unsigned long state;
409 atomic_t abort_request;
410 /* delayed work for hardware timeout */
411 struct delayed_work timeout_work;
412 struct kref ref;
413
414 /* record context running start time */
415 struct timespec64 start;
416 /* hardware info for current task */
417 struct mpp_hw_info *hw_info;
418 u32 task_index;
419 u32 *reg;
420 /* event for session wait thread */
421 wait_queue_head_t wait;
422
423 /* for multi-core */
424 struct mpp_dev *mpp;
425 s32 core_id;
426 };
427
428 struct mpp_taskqueue {
429 /* kworker for attached taskqueue */
430 struct kthread_worker worker;
431 /* task for work queue */
432 struct task_struct *kworker_task;
433
434 /* lock for session attach and session_detach */
435 struct mutex session_lock;
436 /* link to session session_link for attached sessions */
437 struct list_head session_attach;
438 /* link to session session_link for detached sessions */
439 struct list_head session_detach;
440 u32 detach_count;
441
442 /* lock for pending list */
443 struct mutex pending_lock;
444 struct list_head pending_list;
445 /* lock for running list */
446 spinlock_t running_lock;
447 struct list_head running_list;
448
449 /* point to MPP Service */
450 struct mpp_service *srv;
451 /* lock for mmu list */
452 struct mutex mmu_lock;
453 struct list_head mmu_list;
454 /* lock for dev list */
455 struct mutex dev_lock;
456 struct list_head dev_list;
457 /*
458 * task_capacity in taskqueue is the minimum task capacity of the
459 * device task capacity which is attached to the taskqueue
460 */
461 u32 task_capacity;
462
463 /* multi-core task distribution */
464 atomic_t reset_request;
465 struct mpp_dev *cores[MPP_MAX_CORE_NUM];
466 unsigned long core_idle;
467 u32 core_count;
468 };
469
470 struct mpp_reset_group {
471 /* the flag for whether use rw_sem */
472 u32 rw_sem_on;
473 struct rw_semaphore rw_sem;
474 struct reset_control *resets[RST_TYPE_BUTT];
475 /* for set rw_sem */
476 struct mpp_taskqueue *queue;
477 };
478
479 struct mpp_service {
480 struct class *cls;
481 struct device *dev;
482 dev_t dev_id;
483 struct cdev mpp_cdev;
484 struct device *child_dev;
485 #ifdef CONFIG_ROCKCHIP_MPP_PROC_FS
486 struct proc_dir_entry *procfs;
487 #endif
488 unsigned long hw_support;
489 atomic_t shutdown_request;
490 /* follows for device probe */
491 struct mpp_grf_info grf_infos[MPP_DRIVER_BUTT];
492 struct platform_driver *sub_drivers[MPP_DRIVER_BUTT];
493 /* follows for attach service */
494 struct mpp_dev *sub_devices[MPP_DEVICE_BUTT];
495 u32 taskqueue_cnt;
496 struct mpp_taskqueue *task_queues[MPP_DEVICE_BUTT];
497 u32 reset_group_cnt;
498 struct mpp_reset_group *reset_groups[MPP_DEVICE_BUTT];
499
500 /* lock for session list */
501 struct mutex session_lock;
502 struct list_head session_list;
503 u32 session_count;
504 };
505
506 /*
507 * struct mpp_hw_ops - context specific operations for device
508 * @init Do something when hardware probe.
509 * @exit Do something when hardware remove.
510 * @clk_on Enable clocks.
511 * @clk_off Disable clocks.
512 * @get_freq Get special freq for setting.
513 * @set_freq Set freq to hardware.
514 * @reduce_freq Reduce freq when hardware is not running.
515 * @reset When error, reset hardware.
516 */
517 struct mpp_hw_ops {
518 int (*init)(struct mpp_dev *mpp);
519 int (*exit)(struct mpp_dev *mpp);
520 int (*clk_on)(struct mpp_dev *mpp);
521 int (*clk_off)(struct mpp_dev *mpp);
522 int (*get_freq)(struct mpp_dev *mpp,
523 struct mpp_task *mpp_task);
524 int (*set_freq)(struct mpp_dev *mpp,
525 struct mpp_task *mpp_task);
526 int (*reduce_freq)(struct mpp_dev *mpp);
527 int (*reset)(struct mpp_dev *mpp);
528 int (*set_grf)(struct mpp_dev *mpp);
529 };
530
531 /*
532 * struct mpp_dev_ops - context specific operations for task
533 * @alloc_task Alloc and set task.
534 * @prepare Check HW status for determining run next task or not.
535 * @run Start a single {en,de}coding run. Set registers to hardware.
536 * @irq Deal with hardware interrupt top-half.
537 * @isr Deal with hardware interrupt bottom-half.
538 * @finish Read back processing results and additional data from hardware.
539 * @result Read status to userspace.
540 * @free_task Release the resource allocate which alloc.
541 * @ioctl Special cammand from userspace.
542 * @init_session extra initialization on session init.
543 * @free_session extra cleanup on session deinit.
544 * @dump_session information dump for session.
545 * @dump_dev information dump for hardware device.
546 */
547 struct mpp_dev_ops {
548 int (*process_task)(struct mpp_session *session,
549 struct mpp_task_msgs *msgs);
550 int (*wait_result)(struct mpp_session *session,
551 struct mpp_task_msgs *msgs);
552 void (*deinit)(struct mpp_session *session);
553 void (*task_worker)(struct kthread_work *work_s);
554
555 void *(*alloc_task)(struct mpp_session *session,
556 struct mpp_task_msgs *msgs);
557 void *(*prepare)(struct mpp_dev *mpp, struct mpp_task *task);
558 int (*run)(struct mpp_dev *mpp, struct mpp_task *task);
559 int (*irq)(struct mpp_dev *mpp);
560 int (*isr)(struct mpp_dev *mpp);
561 int (*finish)(struct mpp_dev *mpp, struct mpp_task *task);
562 int (*result)(struct mpp_dev *mpp, struct mpp_task *task,
563 struct mpp_task_msgs *msgs);
564 int (*free_task)(struct mpp_session *session,
565 struct mpp_task *task);
566 int (*ioctl)(struct mpp_session *session, struct mpp_request *req);
567 int (*init_session)(struct mpp_session *session);
568 int (*free_session)(struct mpp_session *session);
569 int (*dump_session)(struct mpp_session *session, struct seq_file *seq);
570 int (*dump_dev)(struct mpp_dev *mpp);
571 };
572
573 struct mpp_taskqueue *mpp_taskqueue_init(struct device *dev);
574
575 struct mpp_mem_region *
576 mpp_task_attach_fd(struct mpp_task *task, int fd);
577 int mpp_translate_reg_address(struct mpp_session *session,
578 struct mpp_task *task, int fmt,
579 u32 *reg, struct reg_offset_info *off_inf);
580
581 int mpp_check_req(struct mpp_request *req, int base,
582 int max_size, u32 off_s, u32 off_e);
583 int mpp_extract_reg_offset_info(struct reg_offset_info *off_inf,
584 struct mpp_request *req);
585 int mpp_query_reg_offset_info(struct reg_offset_info *off_inf,
586 u32 index);
587 int mpp_translate_reg_offset_info(struct mpp_task *task,
588 struct reg_offset_info *off_inf,
589 u32 *reg);
590 int mpp_task_init(struct mpp_session *session,
591 struct mpp_task *task);
592 int mpp_task_finish(struct mpp_session *session,
593 struct mpp_task *task);
594 int mpp_task_finalize(struct mpp_session *session,
595 struct mpp_task *task);
596 int mpp_task_dump_mem_region(struct mpp_dev *mpp,
597 struct mpp_task *task);
598 int mpp_task_dump_reg(struct mpp_dev *mpp,
599 struct mpp_task *task);
600 int mpp_task_dump_hw_reg(struct mpp_dev *mpp,
601 struct mpp_task *task);
602 void mpp_free_task(struct kref *ref);
603
604 int mpp_session_deinit(struct mpp_session *session);
605
606 int mpp_dev_probe(struct mpp_dev *mpp,
607 struct platform_device *pdev);
608 int mpp_dev_remove(struct mpp_dev *mpp);
609 int mpp_dev_register_srv(struct mpp_dev *mpp, struct mpp_service *srv);
610
611 int mpp_power_on(struct mpp_dev *mpp);
612 int mpp_power_off(struct mpp_dev *mpp);
613 int mpp_dev_reset(struct mpp_dev *mpp);
614
615 irqreturn_t mpp_dev_irq(int irq, void *param);
616 irqreturn_t mpp_dev_isr_sched(int irq, void *param);
617
618 struct reset_control *mpp_reset_control_get(struct mpp_dev *mpp,
619 enum MPP_RESET_TYPE type,
620 const char *name);
621
622 u32 mpp_get_grf(struct mpp_grf_info *grf_info);
623 bool mpp_grf_is_changed(struct mpp_grf_info *grf_info);
624 int mpp_set_grf(struct mpp_grf_info *grf_info);
625
626 int mpp_time_record(struct mpp_task *task);
627 int mpp_time_diff(struct mpp_task *task);
628
629 int mpp_write_req(struct mpp_dev *mpp, u32 *regs,
630 u32 start_idx, u32 end_idx, u32 en_idx);
631 int mpp_read_req(struct mpp_dev *mpp, u32 *regs,
632 u32 start_idx, u32 end_idx);
633
634 int mpp_get_clk_info(struct mpp_dev *mpp,
635 struct mpp_clk_info *clk_info,
636 const char *name);
637 int mpp_set_clk_info_rate_hz(struct mpp_clk_info *clk_info,
638 enum MPP_CLOCK_MODE mode,
639 unsigned long val);
640 unsigned long mpp_get_clk_info_rate_hz(struct mpp_clk_info *clk_info,
641 enum MPP_CLOCK_MODE mode);
642 int mpp_clk_set_rate(struct mpp_clk_info *clk_info,
643 enum MPP_CLOCK_MODE mode);
644
mpp_write(struct mpp_dev * mpp,u32 reg,u32 val)645 static inline int mpp_write(struct mpp_dev *mpp, u32 reg, u32 val)
646 {
647 int idx = reg / sizeof(u32);
648
649 mpp_debug(DEBUG_SET_REG,
650 "write reg[%03d]: %04x: 0x%08x\n", idx, reg, val);
651 writel(val, mpp->reg_base + reg);
652
653 return 0;
654 }
655
mpp_write_relaxed(struct mpp_dev * mpp,u32 reg,u32 val)656 static inline int mpp_write_relaxed(struct mpp_dev *mpp, u32 reg, u32 val)
657 {
658 int idx = reg / sizeof(u32);
659
660 mpp_debug(DEBUG_SET_REG,
661 "write reg[%03d]: %04x: 0x%08x\n", idx, reg, val);
662 writel_relaxed(val, mpp->reg_base + reg);
663
664 return 0;
665 }
666
mpp_read(struct mpp_dev * mpp,u32 reg)667 static inline u32 mpp_read(struct mpp_dev *mpp, u32 reg)
668 {
669 u32 val = 0;
670 int idx = reg / sizeof(u32);
671
672 val = readl(mpp->reg_base + reg);
673 mpp_debug(DEBUG_GET_REG,
674 "read reg[%03d]: %04x: 0x%08x\n", idx, reg, val);
675
676 return val;
677 }
678
mpp_read_relaxed(struct mpp_dev * mpp,u32 reg)679 static inline u32 mpp_read_relaxed(struct mpp_dev *mpp, u32 reg)
680 {
681 u32 val = 0;
682 int idx = reg / sizeof(u32);
683
684 val = readl_relaxed(mpp->reg_base + reg);
685 mpp_debug(DEBUG_GET_REG,
686 "read reg[%03d] %04x: 0x%08x\n", idx, reg, val);
687
688 return val;
689 }
690
mpp_safe_reset(struct reset_control * rst)691 static inline int mpp_safe_reset(struct reset_control *rst)
692 {
693 if (rst)
694 reset_control_assert(rst);
695
696 return 0;
697 }
698
mpp_safe_unreset(struct reset_control * rst)699 static inline int mpp_safe_unreset(struct reset_control *rst)
700 {
701 if (rst)
702 reset_control_deassert(rst);
703
704 return 0;
705 }
706
mpp_clk_safe_enable(struct clk * clk)707 static inline int mpp_clk_safe_enable(struct clk *clk)
708 {
709 if (clk)
710 clk_prepare_enable(clk);
711
712 return 0;
713 }
714
mpp_clk_safe_disable(struct clk * clk)715 static inline int mpp_clk_safe_disable(struct clk *clk)
716 {
717 if (clk)
718 clk_disable_unprepare(clk);
719
720 return 0;
721 }
722
mpp_reset_down_read(struct mpp_reset_group * group)723 static inline int mpp_reset_down_read(struct mpp_reset_group *group)
724 {
725 if (group && group->rw_sem_on)
726 down_read(&group->rw_sem);
727
728 return 0;
729 }
730
mpp_reset_up_read(struct mpp_reset_group * group)731 static inline int mpp_reset_up_read(struct mpp_reset_group *group)
732 {
733 if (group && group->rw_sem_on)
734 up_read(&group->rw_sem);
735
736 return 0;
737 }
738
mpp_reset_down_write(struct mpp_reset_group * group)739 static inline int mpp_reset_down_write(struct mpp_reset_group *group)
740 {
741 if (group && group->rw_sem_on)
742 down_write(&group->rw_sem);
743
744 return 0;
745 }
746
mpp_reset_up_write(struct mpp_reset_group * group)747 static inline int mpp_reset_up_write(struct mpp_reset_group *group)
748 {
749 if (group && group->rw_sem_on)
750 up_write(&group->rw_sem);
751
752 return 0;
753 }
754
mpp_pmu_idle_request(struct mpp_dev * mpp,bool idle)755 static inline int mpp_pmu_idle_request(struct mpp_dev *mpp, bool idle)
756 {
757 if (mpp->skip_idle)
758 return 0;
759
760 return rockchip_pmu_idle_request(mpp->dev, idle);
761 }
762
763 #ifdef CONFIG_ROCKCHIP_MPP_PROC_FS
764 struct proc_dir_entry *
765 mpp_procfs_create_u32(const char *name, umode_t mode,
766 struct proc_dir_entry *parent, void *data);
767 #else
768 static inline struct proc_dir_entry *
mpp_procfs_create_u32(const char * name,umode_t mode,struct proc_dir_entry * parent,void * data)769 mpp_procfs_create_u32(const char *name, umode_t mode,
770 struct proc_dir_entry *parent, void *data)
771 {
772 return 0;
773 }
774 #endif
775
776 #ifdef CONFIG_ROCKCHIP_MPP_PROC_FS
777 extern const char *mpp_device_name[MPP_DEVICE_BUTT];
778 extern const char *enc_info_item_name[ENC_INFO_BUTT];
779 #endif
780
781 extern const struct file_operations rockchip_mpp_fops;
782
783 extern struct platform_driver rockchip_rkvdec_driver;
784 extern struct platform_driver rockchip_rkvenc_driver;
785 extern struct platform_driver rockchip_vdpu1_driver;
786 extern struct platform_driver rockchip_vepu1_driver;
787 extern struct platform_driver rockchip_vdpu2_driver;
788 extern struct platform_driver rockchip_vepu2_driver;
789 extern struct platform_driver rockchip_vepu22_driver;
790 extern struct platform_driver rockchip_iep2_driver;
791 extern struct platform_driver rockchip_jpgdec_driver;
792 extern struct platform_driver rockchip_rkvdec2_driver;
793 extern struct platform_driver rockchip_rkvenc2_driver;
794
795 #endif
796