1 /* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) 2 * 3 * Rockchip isp2 driver 4 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 5 */ 6 7 #ifndef _UAPI_RKISP2_CONFIG_H 8 #define _UAPI_RKISP2_CONFIG_H 9 10 #include <linux/types.h> 11 #include <linux/v4l2-controls.h> 12 13 #define RKISP_API_VERSION KERNEL_VERSION(1, 8, 0) 14 15 /****************ISP SUBDEV IOCTL*****************************/ 16 17 #define RKISP_CMD_TRIGGER_READ_BACK \ 18 _IOW('V', BASE_VIDIOC_PRIVATE + 0, struct isp2x_csi_trigger) 19 20 #define RKISP_CMD_GET_SHARED_BUF \ 21 _IOR('V', BASE_VIDIOC_PRIVATE + 2, struct rkisp_thunderboot_resmem) 22 23 #define RKISP_CMD_FREE_SHARED_BUF \ 24 _IO('V', BASE_VIDIOC_PRIVATE + 3) 25 26 #define RKISP_CMD_GET_LDCHBUF_INFO \ 27 _IOR('V', BASE_VIDIOC_PRIVATE + 4, struct rkisp_ldchbuf_info) 28 29 #define RKISP_CMD_SET_LDCHBUF_SIZE \ 30 _IOW('V', BASE_VIDIOC_PRIVATE + 5, struct rkisp_ldchbuf_size) 31 32 #define RKISP_CMD_GET_SHM_BUFFD \ 33 _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct rkisp_thunderboot_shmem) 34 35 #define RKISP_CMD_GET_FBCBUF_FD \ 36 _IOR('V', BASE_VIDIOC_PRIVATE + 7, struct isp2x_buf_idxfd) 37 38 #define RKISP_CMD_GET_MESHBUF_INFO \ 39 _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct rkisp_meshbuf_info) 40 41 #define RKISP_CMD_SET_MESHBUF_SIZE \ 42 _IOW('V', BASE_VIDIOC_PRIVATE + 9, struct rkisp_meshbuf_size) 43 44 /****************ISP VIDEO IOCTL******************************/ 45 46 #define RKISP_CMD_GET_CSI_MEMORY_MODE \ 47 _IOR('V', BASE_VIDIOC_PRIVATE + 100, int) 48 49 #define RKISP_CMD_SET_CSI_MEMORY_MODE \ 50 _IOW('V', BASE_VIDIOC_PRIVATE + 101, int) 51 52 #define RKISP_CMD_GET_CMSK \ 53 _IOR('V', BASE_VIDIOC_PRIVATE + 102, struct rkisp_cmsk_cfg) 54 55 #define RKISP_CMD_SET_CMSK \ 56 _IOW('V', BASE_VIDIOC_PRIVATE + 103, struct rkisp_cmsk_cfg) 57 58 /*************************************************************/ 59 60 #define ISP2X_ID_DPCC (0) 61 #define ISP2X_ID_BLS (1) 62 #define ISP2X_ID_SDG (2) 63 #define ISP2X_ID_SIHST (3) 64 #define ISP2X_ID_LSC (4) 65 #define ISP2X_ID_AWB_GAIN (5) 66 #define ISP2X_ID_BDM (7) 67 #define ISP2X_ID_CCM (8) 68 #define ISP2X_ID_GOC (9) 69 #define ISP2X_ID_CPROC (10) 70 #define ISP2X_ID_SIAF (11) 71 #define ISP2X_ID_SIAWB (12) 72 #define ISP2X_ID_IE (13) 73 #define ISP2X_ID_YUVAE (14) 74 #define ISP2X_ID_WDR (15) 75 #define ISP2X_ID_RK_IESHARP (16) 76 #define ISP2X_ID_RAWAF (17) 77 #define ISP2X_ID_RAWAE0 (18) 78 #define ISP2X_ID_RAWAE1 (19) 79 #define ISP2X_ID_RAWAE2 (20) 80 #define ISP2X_ID_RAWAE3 (21) 81 #define ISP2X_ID_RAWAWB (22) 82 #define ISP2X_ID_RAWHIST0 (23) 83 #define ISP2X_ID_RAWHIST1 (24) 84 #define ISP2X_ID_RAWHIST2 (25) 85 #define ISP2X_ID_RAWHIST3 (26) 86 #define ISP2X_ID_HDRMGE (27) 87 #define ISP2X_ID_RAWNR (28) 88 #define ISP2X_ID_HDRTMO (29) 89 #define ISP2X_ID_GIC (30) 90 #define ISP2X_ID_DHAZ (31) 91 #define ISP2X_ID_3DLUT (32) 92 #define ISP2X_ID_LDCH (33) 93 #define ISP2X_ID_GAIN (34) 94 #define ISP2X_ID_DEBAYER (35) 95 #define ISP2X_ID_MAX (36) 96 97 #define ISP2X_MODULE_DPCC BIT_ULL(ISP2X_ID_DPCC) 98 #define ISP2X_MODULE_BLS BIT_ULL(ISP2X_ID_BLS) 99 #define ISP2X_MODULE_SDG BIT_ULL(ISP2X_ID_SDG) 100 #define ISP2X_MODULE_SIHST BIT_ULL(ISP2X_ID_SIHST) 101 #define ISP2X_MODULE_LSC BIT_ULL(ISP2X_ID_LSC) 102 #define ISP2X_MODULE_AWB_GAIN BIT_ULL(ISP2X_ID_AWB_GAIN) 103 #define ISP2X_MODULE_BDM BIT_ULL(ISP2X_ID_BDM) 104 #define ISP2X_MODULE_CCM BIT_ULL(ISP2X_ID_CCM) 105 #define ISP2X_MODULE_GOC BIT_ULL(ISP2X_ID_GOC) 106 #define ISP2X_MODULE_CPROC BIT_ULL(ISP2X_ID_CPROC) 107 #define ISP2X_MODULE_SIAF BIT_ULL(ISP2X_ID_SIAF) 108 #define ISP2X_MODULE_SIAWB BIT_ULL(ISP2X_ID_SIAWB) 109 #define ISP2X_MODULE_IE BIT_ULL(ISP2X_ID_IE) 110 #define ISP2X_MODULE_YUVAE BIT_ULL(ISP2X_ID_YUVAE) 111 #define ISP2X_MODULE_WDR BIT_ULL(ISP2X_ID_WDR) 112 #define ISP2X_MODULE_RK_IESHARP BIT_ULL(ISP2X_ID_RK_IESHARP) 113 #define ISP2X_MODULE_RAWAF BIT_ULL(ISP2X_ID_RAWAF) 114 #define ISP2X_MODULE_RAWAE0 BIT_ULL(ISP2X_ID_RAWAE0) 115 #define ISP2X_MODULE_RAWAE1 BIT_ULL(ISP2X_ID_RAWAE1) 116 #define ISP2X_MODULE_RAWAE2 BIT_ULL(ISP2X_ID_RAWAE2) 117 #define ISP2X_MODULE_RAWAE3 BIT_ULL(ISP2X_ID_RAWAE3) 118 #define ISP2X_MODULE_RAWAWB BIT_ULL(ISP2X_ID_RAWAWB) 119 #define ISP2X_MODULE_RAWHIST0 BIT_ULL(ISP2X_ID_RAWHIST0) 120 #define ISP2X_MODULE_RAWHIST1 BIT_ULL(ISP2X_ID_RAWHIST1) 121 #define ISP2X_MODULE_RAWHIST2 BIT_ULL(ISP2X_ID_RAWHIST2) 122 #define ISP2X_MODULE_RAWHIST3 BIT_ULL(ISP2X_ID_RAWHIST3) 123 #define ISP2X_MODULE_HDRMGE BIT_ULL(ISP2X_ID_HDRMGE) 124 #define ISP2X_MODULE_RAWNR BIT_ULL(ISP2X_ID_RAWNR) 125 #define ISP2X_MODULE_HDRTMO BIT_ULL(ISP2X_ID_HDRTMO) 126 #define ISP2X_MODULE_GIC BIT_ULL(ISP2X_ID_GIC) 127 #define ISP2X_MODULE_DHAZ BIT_ULL(ISP2X_ID_DHAZ) 128 #define ISP2X_MODULE_3DLUT BIT_ULL(ISP2X_ID_3DLUT) 129 #define ISP2X_MODULE_LDCH BIT_ULL(ISP2X_ID_LDCH) 130 #define ISP2X_MODULE_GAIN BIT_ULL(ISP2X_ID_GAIN) 131 #define ISP2X_MODULE_DEBAYER BIT_ULL(ISP2X_ID_DEBAYER) 132 133 /* 134 * Measurement types 135 */ 136 #define ISP2X_STAT_SIAWB BIT(0) 137 #define ISP2X_STAT_YUVAE BIT(1) 138 #define ISP2X_STAT_SIAF BIT(2) 139 #define ISP2X_STAT_SIHST BIT(3) 140 #define ISP2X_STAT_EMB_DATA BIT(4) 141 #define ISP2X_STAT_RAWAWB BIT(5) 142 #define ISP2X_STAT_RAWAF BIT(6) 143 #define ISP2X_STAT_RAWAE0 BIT(7) 144 #define ISP2X_STAT_RAWAE1 BIT(8) 145 #define ISP2X_STAT_RAWAE2 BIT(9) 146 #define ISP2X_STAT_RAWAE3 BIT(10) 147 #define ISP2X_STAT_RAWHST0 BIT(11) 148 #define ISP2X_STAT_RAWHST1 BIT(12) 149 #define ISP2X_STAT_RAWHST2 BIT(13) 150 #define ISP2X_STAT_RAWHST3 BIT(14) 151 #define ISP2X_STAT_BLS BIT(15) 152 #define ISP2X_STAT_HDRTMO BIT(16) 153 #define ISP2X_STAT_DHAZ BIT(17) 154 155 #define ISP2X_LSC_GRAD_TBL_SIZE 8 156 #define ISP2X_LSC_SIZE_TBL_SIZE 8 157 #define ISP2X_LSC_DATA_TBL_SIZE 290 158 159 #define ISP2X_DEGAMMA_CURVE_SIZE 17 160 161 #define ISP2X_GAIN_HDRMGE_GAIN_NUM 3 162 #define ISP2X_GAIN_IDX_NUM 15 163 #define ISP2X_GAIN_LUT_NUM 17 164 165 #define ISP2X_AWB_MAX_GRID 1 166 #define ISP2X_RAWAWB_SUM_NUM 7 167 #define ISP2X_RAWAWB_MULWD_NUM 8 168 #define ISP2X_RAWAWB_RAMDATA_NUM 225 169 170 #define ISP2X_RAWAEBIG_SUBWIN_NUM 4 171 #define ISP2X_RAWAEBIG_MEAN_NUM 225 172 #define ISP2X_RAWAELITE_MEAN_NUM 25 173 #define ISP2X_YUVAE_SUBWIN_NUM 4 174 #define ISP2X_YUVAE_MEAN_NUM 225 175 176 #define ISP2X_RAWHISTBIG_SUBWIN_NUM 225 177 #define ISP2X_RAWHISTLITE_SUBWIN_NUM 25 178 #define ISP2X_SIHIST_WIN_NUM 1 179 #define ISP2X_HIST_WEIGHT_NUM 225 180 #define ISP2X_HIST_BIN_N_MAX 256 181 #define ISP2X_SIHIST_BIN_N_MAX 32 182 183 #define ISP2X_RAWAF_WIN_NUM 2 184 #define ISP2X_RAWAF_LINE_NUM 5 185 #define ISP2X_RAWAF_GAMMA_NUM 17 186 #define ISP2X_RAWAF_SUMDATA_ROW 15 187 #define ISP2X_RAWAF_SUMDATA_COLUMN 15 188 #define ISP2X_RAWAF_SUMDATA_NUM 225 189 #define ISP2X_AFM_MAX_WINDOWS 3 190 191 #define ISP2X_DPCC_PDAF_POINT_NUM 16 192 193 #define ISP2X_HDRMGE_L_CURVE_NUM 17 194 #define ISP2X_HDRMGE_E_CURVE_NUM 17 195 196 #define ISP2X_RAWNR_LUMA_RATION_NUM 8 197 198 #define ISP2X_HDRTMO_MINMAX_NUM 32 199 200 #define ISP2X_GIC_SIGMA_Y_NUM 15 201 202 #define ISP2X_CCM_CURVE_NUM 17 203 204 /* WDR */ 205 #define ISP2X_WDR_SIZE 48 206 207 #define ISP2X_DHAZ_CONV_COEFF_NUM 6 208 #define ISP2X_DHAZ_HIST_IIR_NUM 64 209 210 #define ISP2X_GAMMA_OUT_MAX_SAMPLES 45 211 212 #define ISP2X_MIPI_LUMA_MEAN_MAX 16 213 #define ISP2X_MIPI_RAW_MAX 3 214 #define ISP2X_RAW0_Y_STATE (1 << 0) 215 #define ISP2X_RAW1_Y_STATE (1 << 1) 216 #define ISP2X_RAW2_Y_STATE (1 << 2) 217 218 #define ISP2X_3DLUT_DATA_NUM 729 219 220 #define ISP2X_LDCH_MESH_XY_NUM 0x80000 221 #define ISP2X_LDCH_BUF_NUM 2 222 223 #define ISP2X_THUNDERBOOT_VIDEO_BUF_NUM 30 224 225 #define ISP2X_FBCBUF_FD_NUM 64 226 227 #define ISP2X_MESH_BUF_NUM 2 228 229 enum isp2x_mesh_buf_stat { 230 MESH_BUF_INIT = 0, 231 MESH_BUF_WAIT2CHIP, 232 MESH_BUF_CHIPINUSE, 233 }; 234 235 struct rkisp_meshbuf_info { 236 u64 module_id; 237 u32 unite_isp_id; 238 s32 buf_fd[ISP2X_MESH_BUF_NUM]; 239 u32 buf_size[ISP2X_MESH_BUF_NUM]; 240 } __attribute__ ((packed)); 241 242 struct rkisp_meshbuf_size { 243 u64 module_id; 244 u32 unite_isp_id; 245 u32 meas_width; 246 u32 meas_height; 247 } __attribute__ ((packed)); 248 249 struct isp2x_mesh_head { 250 enum isp2x_mesh_buf_stat stat; 251 u32 data_oft; 252 } __attribute__ ((packed)); 253 254 #define RKISP_CMSK_WIN_MAX 8 255 #define RKISP_CMSK_MOSAIC_MODE 0 256 #define RKISP_CMSK_COVER_MODE 1 257 258 /* struct rkisp_cmsk_win 259 * Priacy Mask Window configture, support 8 windows, and 260 * support for mainpath and selfpath output stream channel. 261 * 262 * mode: 0:mosaic mode, 1:cover mode 263 * win_index: window index 0~7. windows overlap, priority win7 > win0. 264 * cover_color_y: cover mode effective, share for stream channel when same win_index. 265 * cover_color_u: cover mode effective, share for stream channel when same win_index. 266 * cover_color_v: cover mode effective, share for stream channel when same win_index. 267 * 268 * h_offs: window horizontal offset, share for stream channel when same win_index. 2 align. 269 * v_offs: window vertical offset, share for stream channel when same win_index. 2 align. 270 * h_size: window horizontal size, share for stream channel when same win_index. 8 align. 271 * v_size: window vertical size, share for stream channel when same win_index. 8 align. 272 */ 273 struct rkisp_cmsk_win { 274 unsigned char mode; 275 unsigned char win_en; 276 277 unsigned char cover_color_y; 278 unsigned char cover_color_u; 279 unsigned char cover_color_v; 280 281 unsigned short h_offs; 282 unsigned short v_offs; 283 unsigned short h_size; 284 unsigned short v_size; 285 } __attribute__ ((packed)); 286 287 /* struct rkisp_cmsk_cfg 288 * win: priacy mask window 289 * width_ro: isp full resolution, h_offs + h_size <= width_ro. 290 * height_ro: isp full resolution, v_offs + v_size <= height_ro. 291 */ 292 struct rkisp_cmsk_cfg { 293 struct rkisp_cmsk_win win[RKISP_CMSK_WIN_MAX]; 294 unsigned int width_ro; 295 unsigned int height_ro; 296 } __attribute__ ((packed)); 297 298 /* trigger event mode 299 * T_TRY: trigger maybe with retry 300 * T_TRY_YES: trigger to retry 301 * T_TRY_NO: trigger no to retry 302 * 303 * T_START_X1: isp read one frame 304 * T_START_X2: isp read hdr two frame 305 * T_START_X3: isp read hdr three frame 306 */ 307 enum isp2x_trigger_mode { 308 T_TRY = BIT(0), 309 T_TRY_YES = BIT(1), 310 T_TRY_NO = BIT(2), 311 312 T_START_X1 = BIT(4), 313 T_START_X2 = BIT(5), 314 T_START_X3 = BIT(6), 315 }; 316 317 struct isp2x_csi_trigger { 318 /* timestamp in ns */ 319 u64 sof_timestamp; 320 u64 frame_timestamp; 321 u32 frame_id; 322 int times; 323 enum isp2x_trigger_mode mode; 324 } __attribute__ ((packed)); 325 326 /* isp csi dmatx/dmarx memory mode 327 * 0: raw12/raw10/raw8 8bit memory compact 328 * 1: raw12/raw10 16bit memory one pixel 329 * big endian for rv1126/rv1109 330 * |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 331 * | 3| 2| 1| 0| -| -| -| -|11|10| 9| 8| 7| 6| 5| 4| 332 * little align for rk356x 333 * |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 334 * | -| -| -| -|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 335 * 2: raw12/raw10 16bit memory one pixel 336 * big align for rv1126/rv1109/rk356x 337 * |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 338 * |11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| -| -| -| -| 339 */ 340 enum isp_csi_memory { 341 CSI_MEM_COMPACT = 0, 342 CSI_MEM_WORD_BIG_END = 1, 343 CSI_MEM_WORD_LITTLE_ALIGN = 1, 344 CSI_MEM_WORD_BIG_ALIGN = 2, 345 }; 346 347 struct isp2x_ispgain_buf { 348 u32 gain_dmaidx; 349 u32 mfbc_dmaidx; 350 u32 gain_size; 351 u32 mfbc_size; 352 u32 frame_id; 353 } __attribute__ ((packed)); 354 355 struct isp2x_buf_idxfd { 356 u32 buf_num; 357 u32 index[ISP2X_FBCBUF_FD_NUM]; 358 s32 dmafd[ISP2X_FBCBUF_FD_NUM]; 359 } __attribute__ ((packed)); 360 361 struct isp2x_window { 362 u16 h_offs; 363 u16 v_offs; 364 u16 h_size; 365 u16 v_size; 366 } __attribute__ ((packed)); 367 368 struct isp2x_bls_fixed_val { 369 s16 r; 370 s16 gr; 371 s16 gb; 372 s16 b; 373 } __attribute__ ((packed)); 374 375 struct isp2x_bls_cfg { 376 u8 enable_auto; 377 u8 en_windows; 378 struct isp2x_window bls_window1; 379 struct isp2x_window bls_window2; 380 u8 bls_samples; 381 struct isp2x_bls_fixed_val fixed_val; 382 } __attribute__ ((packed)); 383 384 struct isp2x_bls_stat { 385 u16 meas_r; 386 u16 meas_gr; 387 u16 meas_gb; 388 u16 meas_b; 389 } __attribute__ ((packed)); 390 391 struct isp2x_dpcc_pdaf_point { 392 u8 y; 393 u8 x; 394 } __attribute__ ((packed)); 395 396 struct isp2x_dpcc_cfg { 397 //mode 0x0000 398 u8 stage1_enable; 399 u8 grayscale_mode; 400 401 //output_mode 0x0004 402 u8 sw_rk_out_sel; 403 u8 sw_dpcc_output_sel; 404 u8 stage1_rb_3x3; 405 u8 stage1_g_3x3; 406 u8 stage1_incl_rb_center; 407 u8 stage1_incl_green_center; 408 409 //set_use 0x0008 410 u8 stage1_use_fix_set; 411 u8 stage1_use_set_3; 412 u8 stage1_use_set_2; 413 u8 stage1_use_set_1; 414 415 //methods_set_1 0x000c 416 u8 sw_rk_red_blue1_en; 417 u8 rg_red_blue1_enable; 418 u8 rnd_red_blue1_enable; 419 u8 ro_red_blue1_enable; 420 u8 lc_red_blue1_enable; 421 u8 pg_red_blue1_enable; 422 u8 sw_rk_green1_en; 423 u8 rg_green1_enable; 424 u8 rnd_green1_enable; 425 u8 ro_green1_enable; 426 u8 lc_green1_enable; 427 u8 pg_green1_enable; 428 429 //methods_set_2 0x0010 430 u8 sw_rk_red_blue2_en; 431 u8 rg_red_blue2_enable; 432 u8 rnd_red_blue2_enable; 433 u8 ro_red_blue2_enable; 434 u8 lc_red_blue2_enable; 435 u8 pg_red_blue2_enable; 436 u8 sw_rk_green2_en; 437 u8 rg_green2_enable; 438 u8 rnd_green2_enable; 439 u8 ro_green2_enable; 440 u8 lc_green2_enable; 441 u8 pg_green2_enable; 442 443 //methods_set_3 0x0014 444 u8 sw_rk_red_blue3_en; 445 u8 rg_red_blue3_enable; 446 u8 rnd_red_blue3_enable; 447 u8 ro_red_blue3_enable; 448 u8 lc_red_blue3_enable; 449 u8 pg_red_blue3_enable; 450 u8 sw_rk_green3_en; 451 u8 rg_green3_enable; 452 u8 rnd_green3_enable; 453 u8 ro_green3_enable; 454 u8 lc_green3_enable; 455 u8 pg_green3_enable; 456 457 //line_thresh_1 0x0018 458 u8 sw_mindis1_rb; 459 u8 sw_mindis1_g; 460 u8 line_thr_1_rb; 461 u8 line_thr_1_g; 462 463 //line_mad_fac_1 0x001c 464 u8 sw_dis_scale_min1; 465 u8 sw_dis_scale_max1; 466 u8 line_mad_fac_1_rb; 467 u8 line_mad_fac_1_g; 468 469 //pg_fac_1 0x0020 470 u8 pg_fac_1_rb; 471 u8 pg_fac_1_g; 472 473 //rnd_thresh_1 0x0024 474 u8 rnd_thr_1_rb; 475 u8 rnd_thr_1_g; 476 477 //rg_fac_1 0x0028 478 u8 rg_fac_1_rb; 479 u8 rg_fac_1_g; 480 481 //line_thresh_2 0x002c 482 u8 sw_mindis2_rb; 483 u8 sw_mindis2_g; 484 u8 line_thr_2_rb; 485 u8 line_thr_2_g; 486 487 //line_mad_fac_2 0x0030 488 u8 sw_dis_scale_min2; 489 u8 sw_dis_scale_max2; 490 u8 line_mad_fac_2_rb; 491 u8 line_mad_fac_2_g; 492 493 //pg_fac_2 0x0034 494 u8 pg_fac_2_rb; 495 u8 pg_fac_2_g; 496 497 //rnd_thresh_2 0x0038 498 u8 rnd_thr_2_rb; 499 u8 rnd_thr_2_g; 500 501 //rg_fac_2 0x003c 502 u8 rg_fac_2_rb; 503 u8 rg_fac_2_g; 504 505 //line_thresh_3 0x0040 506 u8 sw_mindis3_rb; 507 u8 sw_mindis3_g; 508 u8 line_thr_3_rb; 509 u8 line_thr_3_g; 510 511 //line_mad_fac_3 0x0044 512 u8 sw_dis_scale_min3; 513 u8 sw_dis_scale_max3; 514 u8 line_mad_fac_3_rb; 515 u8 line_mad_fac_3_g; 516 517 //pg_fac_3 0x0048 518 u8 pg_fac_3_rb; 519 u8 pg_fac_3_g; 520 521 //rnd_thresh_3 0x004c 522 u8 rnd_thr_3_rb; 523 u8 rnd_thr_3_g; 524 525 //rg_fac_3 0x0050 526 u8 rg_fac_3_rb; 527 u8 rg_fac_3_g; 528 529 //ro_limits 0x0054 530 u8 ro_lim_3_rb; 531 u8 ro_lim_3_g; 532 u8 ro_lim_2_rb; 533 u8 ro_lim_2_g; 534 u8 ro_lim_1_rb; 535 u8 ro_lim_1_g; 536 537 //rnd_offs 0x0058 538 u8 rnd_offs_3_rb; 539 u8 rnd_offs_3_g; 540 u8 rnd_offs_2_rb; 541 u8 rnd_offs_2_g; 542 u8 rnd_offs_1_rb; 543 u8 rnd_offs_1_g; 544 545 //bpt_ctrl 0x005c 546 u8 bpt_rb_3x3; 547 u8 bpt_g_3x3; 548 u8 bpt_incl_rb_center; 549 u8 bpt_incl_green_center; 550 u8 bpt_use_fix_set; 551 u8 bpt_use_set_3; 552 u8 bpt_use_set_2; 553 u8 bpt_use_set_1; 554 u8 bpt_cor_en; 555 u8 bpt_det_en; 556 557 //bpt_number 0x0060 558 u16 bp_number; 559 560 //bpt_addr 0x0064 561 u16 bp_table_addr; 562 563 //bpt_data 0x0068 564 u16 bpt_v_addr; 565 u16 bpt_h_addr; 566 567 //bp_cnt 0x006c 568 u32 bp_cnt; 569 570 //pdaf_en 0x0070 571 u8 sw_pdaf_en; 572 573 //pdaf_point_en 0x0074 574 u8 pdaf_point_en[ISP2X_DPCC_PDAF_POINT_NUM]; 575 576 //pdaf_offset 0x0078 577 u16 pdaf_offsety; 578 u16 pdaf_offsetx; 579 580 //pdaf_wrap 0x007c 581 u16 pdaf_wrapy; 582 u16 pdaf_wrapx; 583 584 //pdaf_scope 0x0080 585 u16 pdaf_wrapy_num; 586 u16 pdaf_wrapx_num; 587 588 //pdaf_point_0 0x0084 589 struct isp2x_dpcc_pdaf_point point[ISP2X_DPCC_PDAF_POINT_NUM]; 590 591 //pdaf_forward_med 0x00a4 592 u8 pdaf_forward_med; 593 } __attribute__ ((packed)); 594 595 struct isp2x_hdrmge_curve { 596 u16 curve_1[ISP2X_HDRMGE_L_CURVE_NUM]; 597 u16 curve_0[ISP2X_HDRMGE_L_CURVE_NUM]; 598 } __attribute__ ((packed)); 599 600 struct isp2x_hdrmge_cfg { 601 u8 mode; 602 603 u16 gain0_inv; 604 u16 gain0; 605 606 u16 gain1_inv; 607 u16 gain1; 608 609 u8 gain2; 610 611 u8 lm_dif_0p15; 612 u8 lm_dif_0p9; 613 u8 ms_diff_0p15; 614 u8 ms_dif_0p8; 615 616 struct isp2x_hdrmge_curve curve; 617 u16 e_y[ISP2X_HDRMGE_E_CURVE_NUM]; 618 } __attribute__ ((packed)); 619 620 struct isp2x_rawnr_cfg { 621 u8 gauss_en; 622 u8 log_bypass; 623 624 u16 filtpar0; 625 u16 filtpar1; 626 u16 filtpar2; 627 628 u32 dgain0; 629 u32 dgain1; 630 u32 dgain2; 631 632 u16 luration[ISP2X_RAWNR_LUMA_RATION_NUM]; 633 u16 lulevel[ISP2X_RAWNR_LUMA_RATION_NUM]; 634 635 u32 gauss; 636 u16 sigma; 637 u16 pix_diff; 638 639 u32 thld_diff; 640 641 u8 gas_weig_scl2; 642 u8 gas_weig_scl1; 643 u16 thld_chanelw; 644 645 u16 lamda; 646 647 u16 fixw0; 648 u16 fixw1; 649 u16 fixw2; 650 u16 fixw3; 651 652 u32 wlamda0; 653 u32 wlamda1; 654 u32 wlamda2; 655 656 u16 rgain_filp; 657 u16 bgain_filp; 658 } __attribute__ ((packed)); 659 660 struct isp2x_lsc_cfg { 661 u16 r_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 662 u16 gr_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 663 u16 gb_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 664 u16 b_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 665 666 u16 x_grad_tbl[ISP2X_LSC_GRAD_TBL_SIZE]; 667 u16 y_grad_tbl[ISP2X_LSC_GRAD_TBL_SIZE]; 668 669 u16 x_size_tbl[ISP2X_LSC_SIZE_TBL_SIZE]; 670 u16 y_size_tbl[ISP2X_LSC_SIZE_TBL_SIZE]; 671 } __attribute__ ((packed)); 672 673 enum isp2x_goc_mode { 674 ISP2X_GOC_MODE_LOGARITHMIC, 675 ISP2X_GOC_MODE_EQUIDISTANT 676 }; 677 678 struct isp2x_goc_cfg { 679 enum isp2x_goc_mode mode; 680 u8 gamma_y[17]; 681 } __attribute__ ((packed)); 682 683 struct isp2x_hdrtmo_predict { 684 u8 global_tmo; 685 s32 iir_max; 686 s32 global_tmo_strength; 687 688 u8 scene_stable; 689 s32 k_rolgmean; 690 s32 iir; 691 } __attribute__ ((packed)); 692 693 struct isp2x_hdrtmo_cfg { 694 u16 cnt_vsize; 695 u8 gain_ld_off2; 696 u8 gain_ld_off1; 697 u8 big_en; 698 u8 nobig_en; 699 u8 newhst_en; 700 u8 cnt_mode; 701 702 u16 expl_lgratio; 703 u8 lgscl_ratio; 704 u8 cfg_alpha; 705 706 u16 set_gainoff; 707 u16 set_palpha; 708 709 u16 set_lgmax; 710 u16 set_lgmin; 711 712 u8 set_weightkey; 713 u16 set_lgmean; 714 715 u16 set_lgrange1; 716 u16 set_lgrange0; 717 718 u16 set_lgavgmax; 719 720 u8 clipgap1_i; 721 u8 clipgap0_i; 722 u8 clipratio1; 723 u8 clipratio0; 724 u8 ratiol; 725 726 u16 lgscl_inv; 727 u16 lgscl; 728 729 u16 lgmax; 730 731 u16 hist_low; 732 u16 hist_min; 733 734 u8 hist_shift; 735 u16 hist_0p3; 736 u16 hist_high; 737 738 u16 palpha_lwscl; 739 u16 palpha_lw0p5; 740 u16 palpha_0p18; 741 742 u16 maxgain; 743 u16 maxpalpha; 744 745 struct isp2x_hdrtmo_predict predict; 746 } __attribute__ ((packed)); 747 748 struct isp2x_hdrtmo_stat { 749 u16 lglow; 750 u16 lgmin; 751 u16 lghigh; 752 u16 lgmax; 753 u16 weightkey; 754 u16 lgmean; 755 u16 lgrange1; 756 u16 lgrange0; 757 u16 palpha; 758 u16 lgavgmax; 759 u16 linecnt; 760 u32 min_max[ISP2X_HDRTMO_MINMAX_NUM]; 761 } __attribute__ ((packed)); 762 763 struct isp2x_gic_cfg { 764 u8 edge_open; 765 766 u16 regmingradthrdark2; 767 u16 regmingradthrdark1; 768 u16 regminbusythre; 769 770 u16 regdarkthre; 771 u16 regmaxcorvboth; 772 u16 regdarktthrehi; 773 774 u8 regkgrad2dark; 775 u8 regkgrad1dark; 776 u8 regstrengthglobal_fix; 777 u8 regdarkthrestep; 778 u8 regkgrad2; 779 u8 regkgrad1; 780 u8 reggbthre; 781 782 u16 regmaxcorv; 783 u16 regmingradthr2; 784 u16 regmingradthr1; 785 786 u8 gr_ratio; 787 u16 dnloscale; 788 u16 dnhiscale; 789 u8 reglumapointsstep; 790 791 u16 gvaluelimitlo; 792 u16 gvaluelimithi; 793 u8 fusionratiohilimt1; 794 795 u8 regstrength_fix; 796 797 u16 sigma_y[ISP2X_GIC_SIGMA_Y_NUM]; 798 799 u8 noise_cut_en; 800 u16 noise_coe_a; 801 802 u16 noise_coe_b; 803 u16 diff_clip; 804 } __attribute__ ((packed)); 805 806 struct isp2x_debayer_cfg { 807 u8 filter_c_en; 808 u8 filter_g_en; 809 810 u8 thed1; 811 u8 thed0; 812 u8 dist_scale; 813 u8 max_ratio; 814 u8 clip_en; 815 816 s8 filter1_coe5; 817 s8 filter1_coe4; 818 s8 filter1_coe3; 819 s8 filter1_coe2; 820 s8 filter1_coe1; 821 822 s8 filter2_coe5; 823 s8 filter2_coe4; 824 s8 filter2_coe3; 825 s8 filter2_coe2; 826 s8 filter2_coe1; 827 828 u16 hf_offset; 829 u8 gain_offset; 830 u8 offset; 831 832 u8 shift_num; 833 u8 order_max; 834 u8 order_min; 835 } __attribute__ ((packed)); 836 837 struct isp2x_ccm_cfg { 838 s16 coeff0_r; 839 s16 coeff1_r; 840 s16 coeff2_r; 841 s16 offset_r; 842 843 s16 coeff0_g; 844 s16 coeff1_g; 845 s16 coeff2_g; 846 s16 offset_g; 847 848 s16 coeff0_b; 849 s16 coeff1_b; 850 s16 coeff2_b; 851 s16 offset_b; 852 853 u16 coeff0_y; 854 u16 coeff1_y; 855 u16 coeff2_y; 856 857 u16 alp_y[ISP2X_CCM_CURVE_NUM]; 858 859 u8 bound_bit; 860 } __attribute__ ((packed)); 861 862 struct isp2x_gammaout_cfg { 863 u8 equ_segm; 864 u16 offset; 865 u16 gamma_y[ISP2X_GAMMA_OUT_MAX_SAMPLES]; 866 } __attribute__ ((packed)); 867 868 enum isp2x_wdr_mode { 869 ISP2X_WDR_MODE_BLOCK, 870 ISP2X_WDR_MODE_GLOBAL 871 }; 872 873 struct isp2x_wdr_cfg { 874 enum isp2x_wdr_mode mode; 875 unsigned int c_wdr[ISP2X_WDR_SIZE]; 876 } __attribute__ ((packed)); 877 878 struct isp2x_dhaz_cfg { 879 u8 enhance_en; 880 u8 hist_chn; 881 u8 hpara_en; 882 u8 hist_en; 883 u8 dc_en; 884 u8 big_en; 885 u8 nobig_en; 886 887 u8 yblk_th; 888 u8 yhist_th; 889 u8 dc_max_th; 890 u8 dc_min_th; 891 892 u16 wt_max; 893 u8 bright_max; 894 u8 bright_min; 895 896 u8 tmax_base; 897 u8 dark_th; 898 u8 air_max; 899 u8 air_min; 900 901 u16 tmax_max; 902 u16 tmax_off; 903 904 u8 hist_th_off; 905 u8 hist_gratio; 906 907 u16 hist_min; 908 u16 hist_k; 909 910 u16 enhance_value; 911 u16 hist_scale; 912 913 u16 iir_wt_sigma; 914 u16 iir_sigma; 915 u16 stab_fnum; 916 917 u16 iir_tmax_sigma; 918 u16 iir_air_sigma; 919 920 u16 cfg_wt; 921 u16 cfg_air; 922 u16 cfg_alpha; 923 924 u16 cfg_gratio; 925 u16 cfg_tmax; 926 927 u16 dc_weitcur; 928 u16 dc_thed; 929 930 u8 sw_dhaz_dc_bf_h3; 931 u8 sw_dhaz_dc_bf_h2; 932 u8 sw_dhaz_dc_bf_h1; 933 u8 sw_dhaz_dc_bf_h0; 934 935 u8 sw_dhaz_dc_bf_h5; 936 u8 sw_dhaz_dc_bf_h4; 937 938 u16 air_weitcur; 939 u16 air_thed; 940 941 u8 air_bf_h2; 942 u8 air_bf_h1; 943 u8 air_bf_h0; 944 945 u8 gaus_h2; 946 u8 gaus_h1; 947 u8 gaus_h0; 948 949 u8 conv_t0[ISP2X_DHAZ_CONV_COEFF_NUM]; 950 u8 conv_t1[ISP2X_DHAZ_CONV_COEFF_NUM]; 951 u8 conv_t2[ISP2X_DHAZ_CONV_COEFF_NUM]; 952 } __attribute__ ((packed)); 953 954 struct isp2x_dhaz_stat { 955 u16 dhaz_adp_air_base; 956 u16 dhaz_adp_wt; 957 958 u16 dhaz_adp_gratio; 959 u16 dhaz_adp_tmax; 960 961 u16 h_r_iir[ISP2X_DHAZ_HIST_IIR_NUM]; 962 u16 h_g_iir[ISP2X_DHAZ_HIST_IIR_NUM]; 963 u16 h_b_iir[ISP2X_DHAZ_HIST_IIR_NUM]; 964 } __attribute__ ((packed)); 965 966 struct isp2x_cproc_cfg { 967 u8 c_out_range; 968 u8 y_in_range; 969 u8 y_out_range; 970 u8 contrast; 971 u8 brightness; 972 u8 sat; 973 u8 hue; 974 } __attribute__ ((packed)); 975 976 struct isp2x_ie_cfg { 977 u16 effect; 978 u16 color_sel; 979 u16 eff_mat_1; 980 u16 eff_mat_2; 981 u16 eff_mat_3; 982 u16 eff_mat_4; 983 u16 eff_mat_5; 984 u16 eff_tint; 985 } __attribute__ ((packed)); 986 987 struct isp2x_rkiesharp_cfg { 988 u8 coring_thr; 989 u8 full_range; 990 u8 switch_avg; 991 u8 yavg_thr[4]; 992 u8 delta1[5]; 993 u8 delta2[5]; 994 u8 maxnumber[5]; 995 u8 minnumber[5]; 996 u8 gauss_flat_coe[9]; 997 u8 gauss_noise_coe[9]; 998 u8 gauss_other_coe[9]; 999 u8 line1_filter_coe[6]; 1000 u8 line2_filter_coe[9]; 1001 u8 line3_filter_coe[6]; 1002 u16 grad_seq[4]; 1003 u8 sharp_factor[5]; 1004 u8 uv_gauss_flat_coe[15]; 1005 u8 uv_gauss_noise_coe[15]; 1006 u8 uv_gauss_other_coe[15]; 1007 u8 lap_mat_coe[9]; 1008 } __attribute__ ((packed)); 1009 1010 struct isp2x_superimp_cfg { 1011 u8 transparency_mode; 1012 u8 ref_image; 1013 1014 u16 offset_x; 1015 u16 offset_y; 1016 1017 u8 y_comp; 1018 u8 cb_comp; 1019 u8 cr_comp; 1020 } __attribute__ ((packed)); 1021 1022 struct isp2x_gamma_corr_curve { 1023 u16 gamma_y[ISP2X_DEGAMMA_CURVE_SIZE]; 1024 } __attribute__ ((packed)); 1025 1026 struct isp2x_gamma_curve_x_axis_pnts { 1027 u32 gamma_dx0; 1028 u32 gamma_dx1; 1029 } __attribute__ ((packed)); 1030 1031 struct isp2x_sdg_cfg { 1032 struct isp2x_gamma_corr_curve curve_r; 1033 struct isp2x_gamma_corr_curve curve_g; 1034 struct isp2x_gamma_corr_curve curve_b; 1035 struct isp2x_gamma_curve_x_axis_pnts xa_pnts; 1036 } __attribute__ ((packed)); 1037 1038 struct isp2x_bdm_config { 1039 unsigned char demosaic_th; 1040 } __attribute__ ((packed)); 1041 1042 struct isp2x_gain_cfg { 1043 u8 dhaz_en; 1044 u8 wdr_en; 1045 u8 tmo_en; 1046 u8 lsc_en; 1047 u8 mge_en; 1048 1049 u32 mge_gain[ISP2X_GAIN_HDRMGE_GAIN_NUM]; 1050 u16 idx[ISP2X_GAIN_IDX_NUM]; 1051 u16 lut[ISP2X_GAIN_LUT_NUM]; 1052 } __attribute__ ((packed)); 1053 1054 struct isp2x_3dlut_cfg { 1055 u8 bypass_en; 1056 u32 actual_size; // word unit 1057 u16 lut_r[ISP2X_3DLUT_DATA_NUM]; 1058 u16 lut_g[ISP2X_3DLUT_DATA_NUM]; 1059 u16 lut_b[ISP2X_3DLUT_DATA_NUM]; 1060 } __attribute__ ((packed)); 1061 1062 enum isp2x_ldch_buf_stat { 1063 LDCH_BUF_INIT = 0, 1064 LDCH_BUF_WAIT2CHIP, 1065 LDCH_BUF_CHIPINUSE, 1066 }; 1067 1068 struct rkisp_ldchbuf_info { 1069 s32 buf_fd[ISP2X_LDCH_BUF_NUM]; 1070 u32 buf_size[ISP2X_LDCH_BUF_NUM]; 1071 } __attribute__ ((packed)); 1072 1073 struct rkisp_ldchbuf_size { 1074 u32 meas_width; 1075 u32 meas_height; 1076 } __attribute__ ((packed)); 1077 1078 struct isp2x_ldch_head { 1079 enum isp2x_ldch_buf_stat stat; 1080 u32 data_oft; 1081 } __attribute__ ((packed)); 1082 1083 struct isp2x_ldch_cfg { 1084 u32 hsize; 1085 u32 vsize; 1086 s32 buf_fd; 1087 } __attribute__ ((packed)); 1088 1089 struct isp2x_awb_gain_cfg { 1090 u16 gain_red; 1091 u16 gain_green_r; 1092 u16 gain_blue; 1093 u16 gain_green_b; 1094 } __attribute__ ((packed)); 1095 1096 struct isp2x_siawb_meas_cfg { 1097 struct isp2x_window awb_wnd; 1098 u8 awb_mode; 1099 u8 max_y; 1100 u8 min_y; 1101 u8 max_csum; 1102 u8 min_c; 1103 u8 frames; 1104 u8 awb_ref_cr; 1105 u8 awb_ref_cb; 1106 u8 enable_ymax_cmp; 1107 } __attribute__ ((packed)); 1108 1109 struct isp2x_rawawb_meas_cfg { 1110 u8 rawawb_sel; 1111 u8 sw_rawawb_light_num; //CTRL 1112 u8 sw_rawawb_wind_size; //CTRL 1113 u8 sw_rawawb_c_range; //CTRL 1114 u8 sw_rawawb_y_range; //CTRL 1115 u8 sw_rawawb_3dyuv_ls_idx3; //CTRL 1116 u8 sw_rawawb_3dyuv_ls_idx2; //CTRL 1117 u8 sw_rawawb_3dyuv_ls_idx1; //CTRL 1118 u8 sw_rawawb_3dyuv_ls_idx0; //CTRL 1119 u8 sw_rawawb_xy_en; //CTRL 1120 u8 sw_rawawb_uv_en; //CTRL 1121 u8 sw_rawlsc_bypass_en; //CTRL 1122 u8 sw_rawawb_blk_measure_mode; //BLK_CTRL 1123 u8 sw_rawawb_store_wp_flag_ls_idx2; //BLK_CTRL 1124 u8 sw_rawawb_store_wp_flag_ls_idx1; //BLK_CTRL 1125 u8 sw_rawawb_store_wp_flag_ls_idx0; //BLK_CTRL 1126 u16 sw_rawawb_store_wp_th0; //BLK_CTRL 1127 u16 sw_rawawb_store_wp_th1; //BLK_CTRL 1128 u16 sw_rawawb_store_wp_th2; //RAW_CTRL 1129 u16 sw_rawawb_v_offs; //WIN_OFFS 1130 u16 sw_rawawb_h_offs; //WIN_OFFS 1131 u16 sw_rawawb_v_size; //WIN_SIZE 1132 u16 sw_rawawb_h_size; //WIN_SIZE 1133 u16 sw_rawawb_g_max; //LIMIT_RG_MAX 1134 u16 sw_rawawb_r_max; //LIMIT_RG_MAX 1135 u16 sw_rawawb_y_max; //LIMIT_BY_MAX 1136 u16 sw_rawawb_b_max; //LIMIT_BY_MAX 1137 u16 sw_rawawb_g_min; //LIMIT_RG_MIN 1138 u16 sw_rawawb_r_min; //LIMIT_RG_MIN 1139 u16 sw_rawawb_y_min; //LIMIT_BY_MIN 1140 u16 sw_rawawb_b_min; //LIMIT_BY_MIN 1141 u16 sw_rawawb_coeff_y_g; //RGB2Y_0 1142 u16 sw_rawawb_coeff_y_r; //RGB2Y_0 1143 u16 sw_rawawb_coeff_y_b; //RGB2Y_1 1144 u16 sw_rawawb_coeff_u_g; //RGB2U_0 1145 u16 sw_rawawb_coeff_u_r; //RGB2U_0 1146 u16 sw_rawawb_coeff_u_b; //RGB2U_1 1147 u16 sw_rawawb_coeff_v_g; //RGB2V_0 1148 u16 sw_rawawb_coeff_v_r; //RGB2V_0 1149 u16 sw_rawawb_coeff_v_b; //RGB2V_1 1150 u16 sw_rawawb_vertex0_v_0; //UV_DETC_VERTEX0_0 1151 u16 sw_rawawb_vertex0_u_0; //UV_DETC_VERTEX0_0 1152 u16 sw_rawawb_vertex1_v_0; //UV_DETC_VERTEX1_0 1153 u16 sw_rawawb_vertex1_u_0; //UV_DETC_VERTEX1_0 1154 u16 sw_rawawb_vertex2_v_0; //UV_DETC_VERTEX2_0 1155 u16 sw_rawawb_vertex2_u_0; //UV_DETC_VERTEX2_0 1156 u16 sw_rawawb_vertex3_v_0; //UV_DETC_VERTEX3_0 1157 u16 sw_rawawb_vertex3_u_0; //UV_DETC_VERTEX3_0 1158 u32 sw_rawawb_islope01_0; //UV_DETC_ISLOPE01_0 1159 u32 sw_rawawb_islope12_0; //UV_DETC_ISLOPE12_0 1160 u32 sw_rawawb_islope23_0; //UV_DETC_ISLOPE23_0 1161 u32 sw_rawawb_islope30_0; //UV_DETC_ISLOPE30_0 1162 u16 sw_rawawb_vertex0_v_1; //UV_DETC_VERTEX0_1 1163 u16 sw_rawawb_vertex0_u_1; //UV_DETC_VERTEX0_1 1164 u16 sw_rawawb_vertex1_v_1; //UV_DETC_VERTEX1_1 1165 u16 sw_rawawb_vertex1_u_1; //UV_DETC_VERTEX1_1 1166 u16 sw_rawawb_vertex2_v_1; //UV_DETC_VERTEX2_1 1167 u16 sw_rawawb_vertex2_u_1; //UV_DETC_VERTEX2_1 1168 u16 sw_rawawb_vertex3_v_1; //UV_DETC_VERTEX3_1 1169 u16 sw_rawawb_vertex3_u_1; //UV_DETC_VERTEX3_1 1170 u32 sw_rawawb_islope01_1; //UV_DETC_ISLOPE01_1 1171 u32 sw_rawawb_islope12_1; //UV_DETC_ISLOPE12_1 1172 u32 sw_rawawb_islope23_1; //UV_DETC_ISLOPE23_1 1173 u32 sw_rawawb_islope30_1; //UV_DETC_ISLOPE30_1 1174 u16 sw_rawawb_vertex0_v_2; //UV_DETC_VERTEX0_2 1175 u16 sw_rawawb_vertex0_u_2; //UV_DETC_VERTEX0_2 1176 u16 sw_rawawb_vertex1_v_2; //UV_DETC_VERTEX1_2 1177 u16 sw_rawawb_vertex1_u_2; //UV_DETC_VERTEX1_2 1178 u16 sw_rawawb_vertex2_v_2; //UV_DETC_VERTEX2_2 1179 u16 sw_rawawb_vertex2_u_2; //UV_DETC_VERTEX2_2 1180 u16 sw_rawawb_vertex3_v_2; //UV_DETC_VERTEX3_2 1181 u16 sw_rawawb_vertex3_u_2; //UV_DETC_VERTEX3_2 1182 u32 sw_rawawb_islope01_2; //UV_DETC_ISLOPE01_2 1183 u32 sw_rawawb_islope12_2; //UV_DETC_ISLOPE12_2 1184 u32 sw_rawawb_islope23_2; //UV_DETC_ISLOPE23_2 1185 u32 sw_rawawb_islope30_2; //UV_DETC_ISLOPE30_2 1186 u16 sw_rawawb_vertex0_v_3; //UV_DETC_VERTEX0_3 1187 u16 sw_rawawb_vertex0_u_3; //UV_DETC_VERTEX0_3 1188 u16 sw_rawawb_vertex1_v_3; //UV_DETC_VERTEX1_3 1189 u16 sw_rawawb_vertex1_u_3; //UV_DETC_VERTEX1_3 1190 u16 sw_rawawb_vertex2_v_3; //UV_DETC_VERTEX2_3 1191 u16 sw_rawawb_vertex2_u_3; //UV_DETC_VERTEX2_3 1192 u16 sw_rawawb_vertex3_v_3; //UV_DETC_VERTEX3_3 1193 u16 sw_rawawb_vertex3_u_3; //UV_DETC_VERTEX3_3 1194 u32 sw_rawawb_islope01_3; //UV_DETC_ISLOPE01_3 1195 u32 sw_rawawb_islope12_3; //UV_DETC_ISLOPE12_3 1196 u32 sw_rawawb_islope23_3; //UV_DETC_ISLOPE23_3 1197 u32 sw_rawawb_islope30_3; //UV_DETC_ISLOPE30_3 1198 u16 sw_rawawb_vertex0_v_4; //UV_DETC_VERTEX0_4 1199 u16 sw_rawawb_vertex0_u_4; //UV_DETC_VERTEX0_4 1200 u16 sw_rawawb_vertex1_v_4; //UV_DETC_VERTEX1_4 1201 u16 sw_rawawb_vertex1_u_4; //UV_DETC_VERTEX1_4 1202 u16 sw_rawawb_vertex2_v_4; //UV_DETC_VERTEX2_4 1203 u16 sw_rawawb_vertex2_u_4; //UV_DETC_VERTEX2_4 1204 u16 sw_rawawb_vertex3_v_4; //UV_DETC_VERTEX3_4 1205 u16 sw_rawawb_vertex3_u_4; //UV_DETC_VERTEX3_4 1206 u32 sw_rawawb_islope01_4; //UV_DETC_ISLOPE01_4 1207 u32 sw_rawawb_islope12_4; //UV_DETC_ISLOPE12_4 1208 u32 sw_rawawb_islope23_4; //UV_DETC_ISLOPE23_4 1209 u32 sw_rawawb_islope30_4; //UV_DETC_ISLOPE30_4 1210 u16 sw_rawawb_vertex0_v_5; //UV_DETC_VERTEX0_5 1211 u16 sw_rawawb_vertex0_u_5; //UV_DETC_VERTEX0_5 1212 u16 sw_rawawb_vertex1_v_5; //UV_DETC_VERTEX1_5 1213 u16 sw_rawawb_vertex1_u_5; //UV_DETC_VERTEX1_5 1214 u16 sw_rawawb_vertex2_v_5; //UV_DETC_VERTEX2_5 1215 u16 sw_rawawb_vertex2_u_5; //UV_DETC_VERTEX2_5 1216 u16 sw_rawawb_vertex3_v_5; //UV_DETC_VERTEX3_5 1217 u16 sw_rawawb_vertex3_u_5; //UV_DETC_VERTEX3_5 1218 u32 sw_rawawb_islope01_5; //UV_DETC_ISLOPE01_5 1219 u32 sw_rawawb_islope12_5; //UV_DETC_ISLOPE10_5 1220 u32 sw_rawawb_islope23_5; //UV_DETC_ISLOPE23_5 1221 u32 sw_rawawb_islope30_5; //UV_DETC_ISLOPE30_5 1222 u16 sw_rawawb_vertex0_v_6; //UV_DETC_VERTEX0_6 1223 u16 sw_rawawb_vertex0_u_6; //UV_DETC_VERTEX0_6 1224 u16 sw_rawawb_vertex1_v_6; //UV_DETC_VERTEX1_6 1225 u16 sw_rawawb_vertex1_u_6; //UV_DETC_VERTEX1_6 1226 u16 sw_rawawb_vertex2_v_6; //UV_DETC_VERTEX2_6 1227 u16 sw_rawawb_vertex2_u_6; //UV_DETC_VERTEX2_6 1228 u16 sw_rawawb_vertex3_v_6; //UV_DETC_VERTEX3_6 1229 u16 sw_rawawb_vertex3_u_6; //UV_DETC_VERTEX3_6 1230 u32 sw_rawawb_islope01_6; //UV_DETC_ISLOPE01_6 1231 u32 sw_rawawb_islope12_6; //UV_DETC_ISLOPE10_6 1232 u32 sw_rawawb_islope23_6; //UV_DETC_ISLOPE23_6 1233 u32 sw_rawawb_islope30_6; //UV_DETC_ISLOPE30_6 1234 u32 sw_rawawb_b_uv_0; //YUV_DETC_B_UV_0 1235 u32 sw_rawawb_slope_vtcuv_0; //YUV_DETC_SLOPE_VTCUV_0 1236 u32 sw_rawawb_inv_dslope_0; //YUV_DETC_INV_DSLOPE_0 1237 u32 sw_rawawb_slope_ydis_0; //YUV_DETC_SLOPE_YDIS_0 1238 u32 sw_rawawb_b_ydis_0; //YUV_DETC_B_YDIS_0 1239 u32 sw_rawawb_b_uv_1; //YUV_DETC_B_UV_1 1240 u32 sw_rawawb_slope_vtcuv_1; //YUV_DETC_SLOPE_VTCUV_1 1241 u32 sw_rawawb_inv_dslope_1; //YUV_DETC_INV_DSLOPE_1 1242 u32 sw_rawawb_slope_ydis_1; //YUV_DETC_SLOPE_YDIS_1 1243 u32 sw_rawawb_b_ydis_1; //YUV_DETC_B_YDIS_1 1244 u32 sw_rawawb_b_uv_2; //YUV_DETC_B_UV_2 1245 u32 sw_rawawb_slope_vtcuv_2; //YUV_DETC_SLOPE_VTCUV_2 1246 u32 sw_rawawb_inv_dslope_2; //YUV_DETC_INV_DSLOPE_2 1247 u32 sw_rawawb_slope_ydis_2; //YUV_DETC_SLOPE_YDIS_2 1248 u32 sw_rawawb_b_ydis_2; //YUV_DETC_B_YDIS_2 1249 u32 sw_rawawb_b_uv_3; //YUV_DETC_B_UV_3 1250 u32 sw_rawawb_slope_vtcuv_3; //YUV_DETC_SLOPE_VTCUV_3 1251 u32 sw_rawawb_inv_dslope_3; //YUV_DETC_INV_DSLOPE_3 1252 u32 sw_rawawb_slope_ydis_3; //YUV_DETC_SLOPE_YDIS_3 1253 u32 sw_rawawb_b_ydis_3; //YUV_DETC_B_YDIS_3 1254 u32 sw_rawawb_ref_u; //YUV_DETC_REF_U 1255 u8 sw_rawawb_ref_v_3; //YUV_DETC_REF_V_1 1256 u8 sw_rawawb_ref_v_2; //YUV_DETC_REF_V_1 1257 u8 sw_rawawb_ref_v_1; //YUV_DETC_REF_V_1 1258 u8 sw_rawawb_ref_v_0; //YUV_DETC_REF_V_1 1259 u16 sw_rawawb_dis1_0; //YUV_DETC_DIS01_0 1260 u16 sw_rawawb_dis0_0; //YUV_DETC_DIS01_0 1261 u16 sw_rawawb_dis3_0; //YUV_DETC_DIS23_0 1262 u16 sw_rawawb_dis2_0; //YUV_DETC_DIS23_0 1263 u16 sw_rawawb_dis5_0; //YUV_DETC_DIS45_0 1264 u16 sw_rawawb_dis4_0; //YUV_DETC_DIS45_0 1265 u8 sw_rawawb_th3_0; //YUV_DETC_TH03_0 1266 u8 sw_rawawb_th2_0; //YUV_DETC_TH03_0 1267 u8 sw_rawawb_th1_0; //YUV_DETC_TH03_0 1268 u8 sw_rawawb_th0_0; //YUV_DETC_TH03_0 1269 u8 sw_rawawb_th5_0; //YUV_DETC_TH45_0 1270 u8 sw_rawawb_th4_0; //YUV_DETC_TH45_0 1271 u16 sw_rawawb_dis1_1; //YUV_DETC_DIS01_1 1272 u16 sw_rawawb_dis0_1; //YUV_DETC_DIS01_1 1273 u16 sw_rawawb_dis3_1; //YUV_DETC_DIS23_1 1274 u16 sw_rawawb_dis2_1; //YUV_DETC_DIS23_1 1275 u16 sw_rawawb_dis5_1; //YUV_DETC_DIS45_1 1276 u16 sw_rawawb_dis4_1; //YUV_DETC_DIS45_1 1277 u8 sw_rawawb_th3_1; //YUV_DETC_TH03_1 1278 u8 sw_rawawb_th2_1; //YUV_DETC_TH03_1 1279 u8 sw_rawawb_th1_1; //YUV_DETC_TH03_1 1280 u8 sw_rawawb_th0_1; //YUV_DETC_TH03_1 1281 u8 sw_rawawb_th5_1; //YUV_DETC_TH45_1 1282 u8 sw_rawawb_th4_1; //YUV_DETC_TH45_1 1283 u16 sw_rawawb_dis1_2; //YUV_DETC_DIS01_2 1284 u16 sw_rawawb_dis0_2; //YUV_DETC_DIS01_2 1285 u16 sw_rawawb_dis3_2; //YUV_DETC_DIS23_2 1286 u16 sw_rawawb_dis2_2; //YUV_DETC_DIS23_2 1287 u16 sw_rawawb_dis5_2; //YUV_DETC_DIS45_2 1288 u16 sw_rawawb_dis4_2; //YUV_DETC_DIS45_2 1289 u8 sw_rawawb_th3_2; //YUV_DETC_TH03_2 1290 u8 sw_rawawb_th2_2; //YUV_DETC_TH03_2 1291 u8 sw_rawawb_th1_2; //YUV_DETC_TH03_2 1292 u8 sw_rawawb_th0_2; //YUV_DETC_TH03_2 1293 u8 sw_rawawb_th5_2; //YUV_DETC_TH45_2 1294 u8 sw_rawawb_th4_2; //YUV_DETC_TH45_2 1295 u16 sw_rawawb_dis1_3; //YUV_DETC_DIS01_3 1296 u16 sw_rawawb_dis0_3; //YUV_DETC_DIS01_3 1297 u16 sw_rawawb_dis3_3; //YUV_DETC_DIS23_3 1298 u16 sw_rawawb_dis2_3; //YUV_DETC_DIS23_3 1299 u16 sw_rawawb_dis5_3; //YUV_DETC_DIS45_3 1300 u16 sw_rawawb_dis4_3; //YUV_DETC_DIS45_3 1301 u8 sw_rawawb_th3_3; //YUV_DETC_TH03_3 1302 u8 sw_rawawb_th2_3; //YUV_DETC_TH03_3 1303 u8 sw_rawawb_th1_3; //YUV_DETC_TH03_3 1304 u8 sw_rawawb_th0_3; //YUV_DETC_TH03_3 1305 u8 sw_rawawb_th5_3; //YUV_DETC_TH45_3 1306 u8 sw_rawawb_th4_3; //YUV_DETC_TH45_3 1307 u16 sw_rawawb_wt1; //RGB2XY_WT01 1308 u16 sw_rawawb_wt0; //RGB2XY_WT01 1309 u16 sw_rawawb_wt2; //RGB2XY_WT2 1310 u16 sw_rawawb_mat0_y; //RGB2XY_MAT0_XY 1311 u16 sw_rawawb_mat0_x; //RGB2XY_MAT0_XY 1312 u16 sw_rawawb_mat1_y; //RGB2XY_MAT1_XY 1313 u16 sw_rawawb_mat1_x; //RGB2XY_MAT1_XY 1314 u16 sw_rawawb_mat2_y; //RGB2XY_MAT2_XY 1315 u16 sw_rawawb_mat2_x; //RGB2XY_MAT2_XY 1316 u16 sw_rawawb_nor_x1_0; //XY_DETC_NOR_X_0 1317 u16 sw_rawawb_nor_x0_0; //XY_DETC_NOR_X_0 1318 u16 sw_rawawb_nor_y1_0; //XY_DETC_NOR_Y_0 1319 u16 sw_rawawb_nor_y0_0; //XY_DETC_NOR_Y_0 1320 u16 sw_rawawb_big_x1_0; //XY_DETC_BIG_X_0 1321 u16 sw_rawawb_big_x0_0; //XY_DETC_BIG_X_0 1322 u16 sw_rawawb_big_y1_0; //XY_DETC_BIG_Y_0 1323 u16 sw_rawawb_big_y0_0; //XY_DETC_BIG_Y_0 1324 u16 sw_rawawb_sma_x1_0; //XY_DETC_SMA_X_0 1325 u16 sw_rawawb_sma_x0_0; //XY_DETC_SMA_X_0 1326 u16 sw_rawawb_sma_y1_0; //XY_DETC_SMA_Y_0 1327 u16 sw_rawawb_sma_y0_0; //XY_DETC_SMA_Y_0 1328 u16 sw_rawawb_nor_x1_1; //XY_DETC_NOR_X_1 1329 u16 sw_rawawb_nor_x0_1; //XY_DETC_NOR_X_1 1330 u16 sw_rawawb_nor_y1_1; //XY_DETC_NOR_Y_1 1331 u16 sw_rawawb_nor_y0_1; //XY_DETC_NOR_Y_1 1332 u16 sw_rawawb_big_x1_1; //XY_DETC_BIG_X_1 1333 u16 sw_rawawb_big_x0_1; //XY_DETC_BIG_X_1 1334 u16 sw_rawawb_big_y1_1; //XY_DETC_BIG_Y_1 1335 u16 sw_rawawb_big_y0_1; //XY_DETC_BIG_Y_1 1336 u16 sw_rawawb_sma_x1_1; //XY_DETC_SMA_X_1 1337 u16 sw_rawawb_sma_x0_1; //XY_DETC_SMA_X_1 1338 u16 sw_rawawb_sma_y1_1; //XY_DETC_SMA_Y_1 1339 u16 sw_rawawb_sma_y0_1; //XY_DETC_SMA_Y_1 1340 u16 sw_rawawb_nor_x1_2; //XY_DETC_NOR_X_2 1341 u16 sw_rawawb_nor_x0_2; //XY_DETC_NOR_X_2 1342 u16 sw_rawawb_nor_y1_2; //XY_DETC_NOR_Y_2 1343 u16 sw_rawawb_nor_y0_2; //XY_DETC_NOR_Y_2 1344 u16 sw_rawawb_big_x1_2; //XY_DETC_BIG_X_2 1345 u16 sw_rawawb_big_x0_2; //XY_DETC_BIG_X_2 1346 u16 sw_rawawb_big_y1_2; //XY_DETC_BIG_Y_2 1347 u16 sw_rawawb_big_y0_2; //XY_DETC_BIG_Y_2 1348 u16 sw_rawawb_sma_x1_2; //XY_DETC_SMA_X_2 1349 u16 sw_rawawb_sma_x0_2; //XY_DETC_SMA_X_2 1350 u16 sw_rawawb_sma_y1_2; //XY_DETC_SMA_Y_2 1351 u16 sw_rawawb_sma_y0_2; //XY_DETC_SMA_Y_2 1352 u16 sw_rawawb_nor_x1_3; //XY_DETC_NOR_X_3 1353 u16 sw_rawawb_nor_x0_3; //XY_DETC_NOR_X_3 1354 u16 sw_rawawb_nor_y1_3; //XY_DETC_NOR_Y_3 1355 u16 sw_rawawb_nor_y0_3; //XY_DETC_NOR_Y_3 1356 u16 sw_rawawb_big_x1_3; //XY_DETC_BIG_X_3 1357 u16 sw_rawawb_big_x0_3; //XY_DETC_BIG_X_3 1358 u16 sw_rawawb_big_y1_3; //XY_DETC_BIG_Y_3 1359 u16 sw_rawawb_big_y0_3; //XY_DETC_BIG_Y_3 1360 u16 sw_rawawb_sma_x1_3; //XY_DETC_SMA_X_3 1361 u16 sw_rawawb_sma_x0_3; //XY_DETC_SMA_X_3 1362 u16 sw_rawawb_sma_y1_3; //XY_DETC_SMA_Y_3 1363 u16 sw_rawawb_sma_y0_3; //XY_DETC_SMA_Y_3 1364 u16 sw_rawawb_nor_x1_4; //XY_DETC_NOR_X_4 1365 u16 sw_rawawb_nor_x0_4; //XY_DETC_NOR_X_4 1366 u16 sw_rawawb_nor_y1_4; //XY_DETC_NOR_Y_4 1367 u16 sw_rawawb_nor_y0_4; //XY_DETC_NOR_Y_4 1368 u16 sw_rawawb_big_x1_4; //XY_DETC_BIG_X_4 1369 u16 sw_rawawb_big_x0_4; //XY_DETC_BIG_X_4 1370 u16 sw_rawawb_big_y1_4; //XY_DETC_BIG_Y_4 1371 u16 sw_rawawb_big_y0_4; //XY_DETC_BIG_Y_4 1372 u16 sw_rawawb_sma_x1_4; //XY_DETC_SMA_X_4 1373 u16 sw_rawawb_sma_x0_4; //XY_DETC_SMA_X_4 1374 u16 sw_rawawb_sma_y1_4; //XY_DETC_SMA_Y_4 1375 u16 sw_rawawb_sma_y0_4; //XY_DETC_SMA_Y_4 1376 u16 sw_rawawb_nor_x1_5; //XY_DETC_NOR_X_5 1377 u16 sw_rawawb_nor_x0_5; //XY_DETC_NOR_X_5 1378 u16 sw_rawawb_nor_y1_5; //XY_DETC_NOR_Y_5 1379 u16 sw_rawawb_nor_y0_5; //XY_DETC_NOR_Y_5 1380 u16 sw_rawawb_big_x1_5; //XY_DETC_BIG_X_5 1381 u16 sw_rawawb_big_x0_5; //XY_DETC_BIG_X_5 1382 u16 sw_rawawb_big_y1_5; //XY_DETC_BIG_Y_5 1383 u16 sw_rawawb_big_y0_5; //XY_DETC_BIG_Y_5 1384 u16 sw_rawawb_sma_x1_5; //XY_DETC_SMA_X_5 1385 u16 sw_rawawb_sma_x0_5; //XY_DETC_SMA_X_5 1386 u16 sw_rawawb_sma_y1_5; //XY_DETC_SMA_Y_5 1387 u16 sw_rawawb_sma_y0_5; //XY_DETC_SMA_Y_5 1388 u16 sw_rawawb_nor_x1_6; //XY_DETC_NOR_X_6 1389 u16 sw_rawawb_nor_x0_6; //XY_DETC_NOR_X_6 1390 u16 sw_rawawb_nor_y1_6; //XY_DETC_NOR_Y_6 1391 u16 sw_rawawb_nor_y0_6; //XY_DETC_NOR_Y_6 1392 u16 sw_rawawb_big_x1_6; //XY_DETC_BIG_X_6 1393 u16 sw_rawawb_big_x0_6; //XY_DETC_BIG_X_6 1394 u16 sw_rawawb_big_y1_6; //XY_DETC_BIG_Y_6 1395 u16 sw_rawawb_big_y0_6; //XY_DETC_BIG_Y_6 1396 u16 sw_rawawb_sma_x1_6; //XY_DETC_SMA_X_6 1397 u16 sw_rawawb_sma_x0_6; //XY_DETC_SMA_X_6 1398 u16 sw_rawawb_sma_y1_6; //XY_DETC_SMA_Y_6 1399 u16 sw_rawawb_sma_y0_6; //XY_DETC_SMA_Y_6 1400 u8 sw_rawawb_multiwindow_en; //MULTIWINDOW_EXC_CTRL 1401 u8 sw_rawawb_exc_wp_region6_domain; //MULTIWINDOW_EXC_CTRL 1402 u8 sw_rawawb_exc_wp_region6_measen; //MULTIWINDOW_EXC_CTRL 1403 u8 sw_rawawb_exc_wp_region6_excen; //MULTIWINDOW_EXC_CTRL 1404 u8 sw_rawawb_exc_wp_region5_domain; //MULTIWINDOW_EXC_CTRL 1405 u8 sw_rawawb_exc_wp_region5_measen; //MULTIWINDOW_EXC_CTRL 1406 u8 sw_rawawb_exc_wp_region5_excen; //MULTIWINDOW_EXC_CTRL 1407 u8 sw_rawawb_exc_wp_region4_domain; //MULTIWINDOW_EXC_CTRL 1408 u8 sw_rawawb_exc_wp_region4_measen; //MULTIWINDOW_EXC_CTRL 1409 u8 sw_rawawb_exc_wp_region4_excen; //MULTIWINDOW_EXC_CTRL 1410 u8 sw_rawawb_exc_wp_region3_domain; //MULTIWINDOW_EXC_CTRL 1411 u8 sw_rawawb_exc_wp_region3_measen; //MULTIWINDOW_EXC_CTRL 1412 u8 sw_rawawb_exc_wp_region3_excen; //MULTIWINDOW_EXC_CTRL 1413 u8 sw_rawawb_exc_wp_region2_domain; //MULTIWINDOW_EXC_CTRL 1414 u8 sw_rawawb_exc_wp_region2_measen; //MULTIWINDOW_EXC_CTRL 1415 u8 sw_rawawb_exc_wp_region2_excen; //MULTIWINDOW_EXC_CTRL 1416 u8 sw_rawawb_exc_wp_region1_domain; //MULTIWINDOW_EXC_CTRL 1417 u8 sw_rawawb_exc_wp_region1_measen; //MULTIWINDOW_EXC_CTRL 1418 u8 sw_rawawb_exc_wp_region1_excen; //MULTIWINDOW_EXC_CTRL 1419 u8 sw_rawawb_exc_wp_region0_domain; //MULTIWINDOW_EXC_CTRL 1420 u8 sw_rawawb_exc_wp_region0_measen; //MULTIWINDOW_EXC_CTRL 1421 u8 sw_rawawb_exc_wp_region0_excen; //MULTIWINDOW_EXC_CTRL 1422 u16 sw_rawawb_multiwindow0_v_offs; //MULTIWINDOW0_OFFS 1423 u16 sw_rawawb_multiwindow0_h_offs; //MULTIWINDOW0_OFFS 1424 u16 sw_rawawb_multiwindow0_v_size; //MULTIWINDOW0_SIZE 1425 u16 sw_rawawb_multiwindow0_h_size; //MULTIWINDOW0_SIZE 1426 u16 sw_rawawb_multiwindow1_v_offs; //MULTIWINDOW1_OFFS 1427 u16 sw_rawawb_multiwindow1_h_offs; //MULTIWINDOW1_OFFS 1428 u16 sw_rawawb_multiwindow1_v_size; //MULTIWINDOW1_SIZE 1429 u16 sw_rawawb_multiwindow1_h_size; //MULTIWINDOW1_SIZE 1430 u16 sw_rawawb_multiwindow2_v_offs; //MULTIWINDOW2_OFFS 1431 u16 sw_rawawb_multiwindow2_h_offs; //MULTIWINDOW2_OFFS 1432 u16 sw_rawawb_multiwindow2_v_size; //MULTIWINDOW2_SIZE 1433 u16 sw_rawawb_multiwindow2_h_size; //MULTIWINDOW2_SIZE 1434 u16 sw_rawawb_multiwindow3_v_offs; //MULTIWINDOW3_OFFS 1435 u16 sw_rawawb_multiwindow3_h_offs; //MULTIWINDOW3_OFFS 1436 u16 sw_rawawb_multiwindow3_v_size; //MULTIWINDOW3_SIZE 1437 u16 sw_rawawb_multiwindow3_h_size; //MULTIWINDOW3_SIZE 1438 u16 sw_rawawb_multiwindow4_v_offs; //MULTIWINDOW4_OFFS 1439 u16 sw_rawawb_multiwindow4_h_offs; //MULTIWINDOW4_OFFS 1440 u16 sw_rawawb_multiwindow4_v_size; //MULTIWINDOW4_SIZE 1441 u16 sw_rawawb_multiwindow4_h_size; //MULTIWINDOW4_SIZE 1442 u16 sw_rawawb_multiwindow5_v_offs; //MULTIWINDOW5_OFFS 1443 u16 sw_rawawb_multiwindow5_h_offs; //MULTIWINDOW5_OFFS 1444 u16 sw_rawawb_multiwindow5_v_size; //MULTIWINDOW5_SIZE 1445 u16 sw_rawawb_multiwindow5_h_size; //MULTIWINDOW5_SIZE 1446 u16 sw_rawawb_multiwindow6_v_offs; //MULTIWINDOW6_OFFS 1447 u16 sw_rawawb_multiwindow6_h_offs; //MULTIWINDOW6_OFFS 1448 u16 sw_rawawb_multiwindow6_v_size; //MULTIWINDOW6_SIZE 1449 u16 sw_rawawb_multiwindow6_h_size; //MULTIWINDOW6_SIZE 1450 u16 sw_rawawb_multiwindow7_v_offs; //MULTIWINDOW7_OFFS 1451 u16 sw_rawawb_multiwindow7_h_offs; //MULTIWINDOW7_OFFS 1452 u16 sw_rawawb_multiwindow7_v_size; //MULTIWINDOW7_SIZE 1453 u16 sw_rawawb_multiwindow7_h_size; //MULTIWINDOW7_SIZE 1454 u16 sw_rawawb_exc_wp_region0_xu1; //EXC_WP_REGION0_XU 1455 u16 sw_rawawb_exc_wp_region0_xu0; //EXC_WP_REGION0_XU 1456 u16 sw_rawawb_exc_wp_region0_yv1; //EXC_WP_REGION0_YV 1457 u16 sw_rawawb_exc_wp_region0_yv0; //EXC_WP_REGION0_YV 1458 u16 sw_rawawb_exc_wp_region1_xu1; //EXC_WP_REGION1_XU 1459 u16 sw_rawawb_exc_wp_region1_xu0; //EXC_WP_REGION1_XU 1460 u16 sw_rawawb_exc_wp_region1_yv1; //EXC_WP_REGION1_YV 1461 u16 sw_rawawb_exc_wp_region1_yv0; //EXC_WP_REGION1_YV 1462 u16 sw_rawawb_exc_wp_region2_xu1; //EXC_WP_REGION2_XU 1463 u16 sw_rawawb_exc_wp_region2_xu0; //EXC_WP_REGION2_XU 1464 u16 sw_rawawb_exc_wp_region2_yv1; //EXC_WP_REGION2_YV 1465 u16 sw_rawawb_exc_wp_region2_yv0; //EXC_WP_REGION2_YV 1466 u16 sw_rawawb_exc_wp_region3_xu1; //EXC_WP_REGION3_XU 1467 u16 sw_rawawb_exc_wp_region3_xu0; //EXC_WP_REGION3_XU 1468 u16 sw_rawawb_exc_wp_region3_yv1; //EXC_WP_REGION3_YV 1469 u16 sw_rawawb_exc_wp_region3_yv0; //EXC_WP_REGION3_YV 1470 u16 sw_rawawb_exc_wp_region4_xu1; //EXC_WP_REGION4_XU 1471 u16 sw_rawawb_exc_wp_region4_xu0; //EXC_WP_REGION4_XU 1472 u16 sw_rawawb_exc_wp_region4_yv1; //EXC_WP_REGION4_YV 1473 u16 sw_rawawb_exc_wp_region4_yv0; //EXC_WP_REGION4_YV 1474 u16 sw_rawawb_exc_wp_region5_xu1; //EXC_WP_REGION5_XU 1475 u16 sw_rawawb_exc_wp_region5_xu0; //EXC_WP_REGION5_XU 1476 u16 sw_rawawb_exc_wp_region5_yv1; //EXC_WP_REGION5_YV 1477 u16 sw_rawawb_exc_wp_region5_yv0; //EXC_WP_REGION5_YV 1478 u16 sw_rawawb_exc_wp_region6_xu1; //EXC_WP_REGION6_XU 1479 u16 sw_rawawb_exc_wp_region6_xu0; //EXC_WP_REGION6_XU 1480 u16 sw_rawawb_exc_wp_region6_yv1; //EXC_WP_REGION6_YV 1481 u16 sw_rawawb_exc_wp_region6_yv0; //EXC_WP_REGION6_YV 1482 } __attribute__ ((packed)); 1483 1484 struct isp2x_rawaebig_meas_cfg { 1485 u8 rawae_sel; 1486 u8 wnd_num; 1487 u8 subwin_en[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1488 struct isp2x_window win; 1489 struct isp2x_window subwin[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1490 } __attribute__ ((packed)); 1491 1492 struct isp2x_rawaelite_meas_cfg { 1493 u8 rawae_sel; 1494 u8 wnd_num; 1495 struct isp2x_window win; 1496 } __attribute__ ((packed)); 1497 1498 struct isp2x_yuvae_meas_cfg { 1499 u8 ysel; 1500 u8 wnd_num; 1501 u8 subwin_en[ISP2X_YUVAE_SUBWIN_NUM]; 1502 struct isp2x_window win; 1503 struct isp2x_window subwin[ISP2X_YUVAE_SUBWIN_NUM]; 1504 } __attribute__ ((packed)); 1505 1506 struct isp2x_rawaf_meas_cfg { 1507 u8 rawaf_sel; 1508 u8 num_afm_win; 1509 u8 gaus_en; 1510 u8 gamma_en; 1511 struct isp2x_window win[ISP2X_RAWAF_WIN_NUM]; 1512 u8 line_en[ISP2X_RAWAF_LINE_NUM]; 1513 u8 line_num[ISP2X_RAWAF_LINE_NUM]; 1514 u8 gaus_coe_h2; 1515 u8 gaus_coe_h1; 1516 u8 gaus_coe_h0; 1517 u16 afm_thres; 1518 u8 lum_var_shift[ISP2X_RAWAF_WIN_NUM]; 1519 u8 afm_var_shift[ISP2X_RAWAF_WIN_NUM]; 1520 u16 gamma_y[ISP2X_RAWAF_GAMMA_NUM]; 1521 } __attribute__ ((packed)); 1522 1523 struct isp2x_siaf_win_cfg { 1524 u8 sum_shift; 1525 u8 lum_shift; 1526 struct isp2x_window win; 1527 } __attribute__ ((packed)); 1528 1529 struct isp2x_siaf_cfg { 1530 u8 num_afm_win; 1531 u32 thres; 1532 struct isp2x_siaf_win_cfg afm_win[ISP2X_AFM_MAX_WINDOWS]; 1533 } __attribute__ ((packed)); 1534 1535 struct isp2x_rawhistbig_cfg { 1536 u8 wnd_num; 1537 u8 data_sel; 1538 u8 waterline; 1539 u8 mode; 1540 u8 stepsize; 1541 u8 off; 1542 u8 bcc; 1543 u8 gcc; 1544 u8 rcc; 1545 struct isp2x_window win; 1546 u8 weight[ISP2X_RAWHISTBIG_SUBWIN_NUM]; 1547 } __attribute__ ((packed)); 1548 1549 struct isp2x_rawhistlite_cfg { 1550 u8 data_sel; 1551 u8 waterline; 1552 u8 mode; 1553 u8 stepsize; 1554 u8 off; 1555 u8 bcc; 1556 u8 gcc; 1557 u8 rcc; 1558 struct isp2x_window win; 1559 u8 weight[ISP2X_RAWHISTLITE_SUBWIN_NUM]; 1560 } __attribute__ ((packed)); 1561 1562 struct isp2x_sihst_win_cfg { 1563 u8 data_sel; 1564 u8 waterline; 1565 u8 auto_stop; 1566 u8 mode; 1567 u8 stepsize; 1568 struct isp2x_window win; 1569 } __attribute__ ((packed)); 1570 1571 struct isp2x_sihst_cfg { 1572 u8 wnd_num; 1573 struct isp2x_sihst_win_cfg win_cfg[ISP2X_SIHIST_WIN_NUM]; 1574 u8 hist_weight[ISP2X_HIST_WEIGHT_NUM]; 1575 } __attribute__ ((packed)); 1576 1577 struct isp2x_isp_other_cfg { 1578 struct isp2x_bls_cfg bls_cfg; 1579 struct isp2x_dpcc_cfg dpcc_cfg; 1580 struct isp2x_hdrmge_cfg hdrmge_cfg; 1581 struct isp2x_rawnr_cfg rawnr_cfg; 1582 struct isp2x_lsc_cfg lsc_cfg; 1583 struct isp2x_awb_gain_cfg awb_gain_cfg; 1584 //struct isp2x_goc_cfg goc_cfg; 1585 struct isp2x_gic_cfg gic_cfg; 1586 struct isp2x_debayer_cfg debayer_cfg; 1587 struct isp2x_ccm_cfg ccm_cfg; 1588 struct isp2x_gammaout_cfg gammaout_cfg; 1589 struct isp2x_wdr_cfg wdr_cfg; 1590 struct isp2x_cproc_cfg cproc_cfg; 1591 struct isp2x_ie_cfg ie_cfg; 1592 struct isp2x_rkiesharp_cfg rkiesharp_cfg; 1593 struct isp2x_superimp_cfg superimp_cfg; 1594 struct isp2x_sdg_cfg sdg_cfg; 1595 struct isp2x_bdm_config bdm_cfg; 1596 struct isp2x_hdrtmo_cfg hdrtmo_cfg; 1597 struct isp2x_dhaz_cfg dhaz_cfg; 1598 struct isp2x_gain_cfg gain_cfg; 1599 struct isp2x_3dlut_cfg isp3dlut_cfg; 1600 struct isp2x_ldch_cfg ldch_cfg; 1601 } __attribute__ ((packed)); 1602 1603 struct isp2x_isp_meas_cfg { 1604 struct isp2x_siawb_meas_cfg siawb; 1605 struct isp2x_rawawb_meas_cfg rawawb; 1606 struct isp2x_rawaelite_meas_cfg rawae0; 1607 struct isp2x_rawaebig_meas_cfg rawae1; 1608 struct isp2x_rawaebig_meas_cfg rawae2; 1609 struct isp2x_rawaebig_meas_cfg rawae3; 1610 struct isp2x_yuvae_meas_cfg yuvae; 1611 struct isp2x_rawaf_meas_cfg rawaf; 1612 struct isp2x_siaf_cfg siaf; 1613 struct isp2x_rawhistlite_cfg rawhist0; 1614 struct isp2x_rawhistbig_cfg rawhist1; 1615 struct isp2x_rawhistbig_cfg rawhist2; 1616 struct isp2x_rawhistbig_cfg rawhist3; 1617 struct isp2x_sihst_cfg sihst; 1618 } __attribute__ ((packed)); 1619 1620 struct sensor_exposure_s { 1621 u32 fine_integration_time; 1622 u32 coarse_integration_time; 1623 u32 analog_gain_code_global; 1624 u32 digital_gain_global; 1625 u32 isp_digital_gain; 1626 } __attribute__ ((packed)); 1627 1628 struct sensor_exposure_cfg { 1629 struct sensor_exposure_s linear_exp; 1630 struct sensor_exposure_s hdr_exp[3]; 1631 } __attribute__ ((packed)); 1632 1633 struct isp2x_isp_params_cfg { 1634 u64 module_en_update; 1635 u64 module_ens; 1636 u64 module_cfg_update; 1637 1638 u32 frame_id; 1639 struct isp2x_isp_meas_cfg meas; 1640 struct isp2x_isp_other_cfg others; 1641 struct sensor_exposure_cfg exposure; 1642 } __attribute__ ((packed)); 1643 1644 struct isp2x_siawb_meas { 1645 u32 cnt; 1646 u8 mean_y_or_g; 1647 u8 mean_cb_or_b; 1648 u8 mean_cr_or_r; 1649 } __attribute__ ((packed)); 1650 1651 struct isp2x_siawb_stat { 1652 struct isp2x_siawb_meas awb_mean[ISP2X_AWB_MAX_GRID]; 1653 } __attribute__ ((packed)); 1654 1655 struct isp2x_rawawb_ramdata { 1656 u32 wp; 1657 u32 r; 1658 u32 g; 1659 u32 b; 1660 }; 1661 1662 struct isp2x_rawawb_meas_stat { 1663 u32 ro_rawawb_sum_r_nor[ISP2X_RAWAWB_SUM_NUM]; //SUM_R_NOR_0 1664 u32 ro_rawawb_sum_g_nor[ISP2X_RAWAWB_SUM_NUM]; //SUM_G_NOR_0 1665 u32 ro_rawawb_sum_b_nor[ISP2X_RAWAWB_SUM_NUM]; //SUM_B_NOR_0 1666 u32 ro_rawawb_wp_num_nor[ISP2X_RAWAWB_SUM_NUM]; //WP_NUM_NOR_0 1667 u32 ro_rawawb_sum_r_big[ISP2X_RAWAWB_SUM_NUM]; //SUM_R_BIG_0 1668 u32 ro_rawawb_sum_g_big[ISP2X_RAWAWB_SUM_NUM]; //SUM_G_BIG_0 1669 u32 ro_rawawb_sum_b_big[ISP2X_RAWAWB_SUM_NUM]; //SUM_B_BIG_0 1670 u32 ro_rawawb_wp_num_big[ISP2X_RAWAWB_SUM_NUM]; //WP_NUM_BIG_0 1671 u32 ro_rawawb_sum_r_sma[ISP2X_RAWAWB_SUM_NUM]; //SUM_R_SMA_0 1672 u32 ro_rawawb_sum_g_sma[ISP2X_RAWAWB_SUM_NUM]; //SUM_G_SMA_0 1673 u32 ro_rawawb_sum_b_sma[ISP2X_RAWAWB_SUM_NUM]; //SUM_B_SMA_0 1674 u32 ro_rawawb_wp_num_sma[ISP2X_RAWAWB_SUM_NUM]; 1675 u32 ro_sum_r_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_R_NOR_MULTIWINDOW_0 1676 u32 ro_sum_g_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_G_NOR_MULTIWINDOW_0 1677 u32 ro_sum_b_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_B_NOR_MULTIWINDOW_0 1678 u32 ro_wp_nm_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //WP_NM_NOR_MULTIWINDOW_0 1679 u32 ro_sum_r_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_R_BIG_MULTIWINDOW_0 1680 u32 ro_sum_g_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_G_BIG_MULTIWINDOW_0 1681 u32 ro_sum_b_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_B_BIG_MULTIWINDOW_0 1682 u32 ro_wp_nm_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //WP_NM_BIG_MULTIWINDOW_0 1683 u32 ro_sum_r_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_R_SMA_MULTIWINDOW_0 1684 u32 ro_sum_g_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_G_SMA_MULTIWINDOW_0 1685 u32 ro_sum_b_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_B_SMA_MULTIWINDOW_0 1686 u32 ro_wp_nm_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //WP_NM_SMA_MULTIWINDOW_0 1687 u32 ro_sum_r_exc[ISP2X_RAWAWB_SUM_NUM]; 1688 u32 ro_sum_g_exc[ISP2X_RAWAWB_SUM_NUM]; 1689 u32 ro_sum_b_exc[ISP2X_RAWAWB_SUM_NUM]; 1690 u32 ro_wp_nm_exc[ISP2X_RAWAWB_SUM_NUM]; 1691 struct isp2x_rawawb_ramdata ramdata[ISP2X_RAWAWB_RAMDATA_NUM]; 1692 } __attribute__ ((packed)); 1693 1694 struct isp2x_rawae_meas_data { 1695 u16 channelr_xy; 1696 u16 channelb_xy; 1697 u16 channelg_xy; 1698 }; 1699 1700 struct isp2x_rawaebig_stat { 1701 u32 sumr[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1702 u32 sumg[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1703 u32 sumb[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1704 struct isp2x_rawae_meas_data data[ISP2X_RAWAEBIG_MEAN_NUM]; 1705 } __attribute__ ((packed)); 1706 1707 struct isp2x_rawaelite_stat { 1708 struct isp2x_rawae_meas_data data[ISP2X_RAWAELITE_MEAN_NUM]; 1709 } __attribute__ ((packed)); 1710 1711 struct isp2x_yuvae_stat { 1712 u32 ro_yuvae_sumy[ISP2X_YUVAE_SUBWIN_NUM]; 1713 u8 mean[ISP2X_YUVAE_MEAN_NUM]; 1714 } __attribute__ ((packed)); 1715 1716 struct isp2x_rawaf_stat { 1717 u32 int_state; 1718 u32 afm_sum[ISP2X_RAWAF_WIN_NUM]; 1719 u32 afm_lum[ISP2X_RAWAF_WIN_NUM]; 1720 u32 ramdata[ISP2X_RAWAF_SUMDATA_NUM]; 1721 } __attribute__ ((packed)); 1722 1723 struct isp2x_siaf_meas_val { 1724 u32 sum; 1725 u32 lum; 1726 } __attribute__ ((packed)); 1727 1728 struct isp2x_siaf_stat { 1729 struct isp2x_siaf_meas_val win[ISP2X_AFM_MAX_WINDOWS]; 1730 } __attribute__ ((packed)); 1731 1732 struct isp2x_rawhistbig_stat { 1733 u32 hist_bin[ISP2X_HIST_BIN_N_MAX]; 1734 } __attribute__ ((packed)); 1735 1736 struct isp2x_rawhistlite_stat { 1737 u32 hist_bin[ISP2X_HIST_BIN_N_MAX]; 1738 } __attribute__ ((packed)); 1739 1740 struct isp2x_sihst_win_stat { 1741 u32 hist_bins[ISP2X_SIHIST_BIN_N_MAX]; 1742 } __attribute__ ((packed)); 1743 1744 struct isp2x_sihst_stat { 1745 struct isp2x_sihst_win_stat win_stat[ISP2X_SIHIST_WIN_NUM]; 1746 } __attribute__ ((packed)); 1747 1748 struct isp2x_stat { 1749 struct isp2x_siawb_stat siawb; 1750 struct isp2x_rawawb_meas_stat rawawb; 1751 struct isp2x_rawaelite_stat rawae0; 1752 struct isp2x_rawaebig_stat rawae1; 1753 struct isp2x_rawaebig_stat rawae2; 1754 struct isp2x_rawaebig_stat rawae3; 1755 struct isp2x_yuvae_stat yuvae; 1756 struct isp2x_rawaf_stat rawaf; 1757 struct isp2x_siaf_stat siaf; 1758 struct isp2x_rawhistlite_stat rawhist0; 1759 struct isp2x_rawhistbig_stat rawhist1; 1760 struct isp2x_rawhistbig_stat rawhist2; 1761 struct isp2x_rawhistbig_stat rawhist3; 1762 struct isp2x_sihst_stat sihst; 1763 1764 struct isp2x_bls_stat bls; 1765 struct isp2x_hdrtmo_stat hdrtmo; 1766 struct isp2x_dhaz_stat dhaz; 1767 } __attribute__ ((packed)); 1768 1769 /** 1770 * struct rkisp_isp2x_stat_buffer - Rockchip ISP2 Statistics Meta Data 1771 * 1772 * @meas_type: measurement types (CIFISP_STAT_ definitions) 1773 * @frame_id: frame ID for sync 1774 * @params: statistics data 1775 */ 1776 struct rkisp_isp2x_stat_buffer { 1777 unsigned int meas_type; 1778 unsigned int frame_id; 1779 struct isp2x_stat params; 1780 } __attribute__ ((packed)); 1781 1782 /** 1783 * struct rkisp_mipi_luma - statistics mipi y statistic 1784 * 1785 * @exp_mean: Mean luminance value of block xx 1786 * 1787 * Image is divided into 5x5 blocks. 1788 */ 1789 struct rkisp_mipi_luma { 1790 unsigned int exp_mean[ISP2X_MIPI_LUMA_MEAN_MAX]; 1791 } __attribute__ ((packed)); 1792 1793 /** 1794 * struct rkisp_isp2x_luma_buffer - Rockchip ISP1 Statistics Mipi Luma 1795 * 1796 * @meas_type: measurement types (CIFISP_STAT_ definitions) 1797 * @frame_id: frame ID for sync 1798 * @params: statistics data 1799 */ 1800 struct rkisp_isp2x_luma_buffer { 1801 unsigned int meas_type; 1802 unsigned int frame_id; 1803 struct rkisp_mipi_luma luma[ISP2X_MIPI_RAW_MAX]; 1804 } __attribute__ ((packed)); 1805 1806 /** 1807 * struct rkisp_thunderboot_video_buf 1808 */ 1809 struct rkisp_thunderboot_video_buf { 1810 u32 index; 1811 u32 frame_id; 1812 u32 timestamp; 1813 u32 time_reg; 1814 u32 gain_reg; 1815 u32 bufaddr; 1816 u32 bufsize; 1817 } __attribute__ ((packed)); 1818 1819 /** 1820 * struct rkisp_thunderboot_resmem_head 1821 */ 1822 struct rkisp_thunderboot_resmem_head { 1823 u16 enable; 1824 u16 complete; 1825 u16 frm_total; 1826 u16 hdr_mode; 1827 u16 width; 1828 u16 height; 1829 u32 bus_fmt; 1830 1831 struct rkisp_thunderboot_video_buf l_buf[ISP2X_THUNDERBOOT_VIDEO_BUF_NUM]; 1832 struct rkisp_thunderboot_video_buf m_buf[ISP2X_THUNDERBOOT_VIDEO_BUF_NUM]; 1833 struct rkisp_thunderboot_video_buf s_buf[ISP2X_THUNDERBOOT_VIDEO_BUF_NUM]; 1834 } __attribute__ ((packed)); 1835 1836 /** 1837 * struct rkisp_thunderboot_resmem - shared buffer for thunderboot with risc-v side 1838 */ 1839 struct rkisp_thunderboot_resmem { 1840 u32 resmem_padr; 1841 u32 resmem_size; 1842 } __attribute__ ((packed)); 1843 1844 /** 1845 * struct rkisp_thunderboot_shmem 1846 */ 1847 struct rkisp_thunderboot_shmem { 1848 u32 shm_start; 1849 u32 shm_size; 1850 s32 shm_fd; 1851 } __attribute__ ((packed)); 1852 1853 #endif /* _UAPI_RKISP2_CONFIG_H */ 1854