1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_vcn.h"
28 #include "amdgpu_pm.h"
29 #include "soc15.h"
30 #include "soc15d.h"
31 #include "soc15_common.h"
32
33 #include "vcn/vcn_1_0_offset.h"
34 #include "vcn/vcn_1_0_sh_mask.h"
35 #include "hdp/hdp_4_0_offset.h"
36 #include "mmhub/mmhub_9_1_offset.h"
37 #include "mmhub/mmhub_9_1_sh_mask.h"
38
39 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
40 #include "jpeg_v1_0.h"
41 #include "vcn_v1_0.h"
42
43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0 0x05ab
44 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX 1
45 #define mmUVD_REG_XX_MASK_1_0 0x05ac
46 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1
47
48 static int vcn_v1_0_stop(struct amdgpu_device *adev);
49 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
50 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
51 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
52 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
53 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
54 int inst_idx, struct dpg_pause_state *new_state);
55
56 static void vcn_v1_0_idle_work_handler(struct work_struct *work);
57 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
58
59 /**
60 * vcn_v1_0_early_init - set function pointers
61 *
62 * @handle: amdgpu_device pointer
63 *
64 * Set ring and irq function pointers
65 */
vcn_v1_0_early_init(void * handle)66 static int vcn_v1_0_early_init(void *handle)
67 {
68 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
69
70 adev->vcn.num_vcn_inst = 1;
71 adev->vcn.num_enc_rings = 2;
72
73 vcn_v1_0_set_dec_ring_funcs(adev);
74 vcn_v1_0_set_enc_ring_funcs(adev);
75 vcn_v1_0_set_irq_funcs(adev);
76
77 jpeg_v1_0_early_init(handle);
78
79 return 0;
80 }
81
82 /**
83 * vcn_v1_0_sw_init - sw init for VCN block
84 *
85 * @handle: amdgpu_device pointer
86 *
87 * Load firmware and sw initialization
88 */
vcn_v1_0_sw_init(void * handle)89 static int vcn_v1_0_sw_init(void *handle)
90 {
91 struct amdgpu_ring *ring;
92 int i, r;
93 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
94
95 /* VCN DEC TRAP */
96 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
97 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq);
98 if (r)
99 return r;
100
101 /* VCN ENC TRAP */
102 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
103 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
104 &adev->vcn.inst->irq);
105 if (r)
106 return r;
107 }
108
109 r = amdgpu_vcn_sw_init(adev);
110 if (r)
111 return r;
112
113 /* Override the work func */
114 adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler;
115
116 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
117 const struct common_firmware_header *hdr;
118 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
119 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
120 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
121 adev->firmware.fw_size +=
122 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
123 dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
124 }
125
126 r = amdgpu_vcn_resume(adev);
127 if (r)
128 return r;
129
130 ring = &adev->vcn.inst->ring_dec;
131 sprintf(ring->name, "vcn_dec");
132 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
133 AMDGPU_RING_PRIO_DEFAULT);
134 if (r)
135 return r;
136
137 adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 =
138 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
139 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 =
140 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
141 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 =
142 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
143 adev->vcn.internal.cmd = adev->vcn.inst->external.cmd =
144 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
145 adev->vcn.internal.nop = adev->vcn.inst->external.nop =
146 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
147
148 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
149 ring = &adev->vcn.inst->ring_enc[i];
150 sprintf(ring->name, "vcn_enc%d", i);
151 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
152 AMDGPU_RING_PRIO_DEFAULT);
153 if (r)
154 return r;
155 }
156
157 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
158
159 r = jpeg_v1_0_sw_init(handle);
160
161 return r;
162 }
163
164 /**
165 * vcn_v1_0_sw_fini - sw fini for VCN block
166 *
167 * @handle: amdgpu_device pointer
168 *
169 * VCN suspend and free up sw allocation
170 */
vcn_v1_0_sw_fini(void * handle)171 static int vcn_v1_0_sw_fini(void *handle)
172 {
173 int r;
174 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
175
176 r = amdgpu_vcn_suspend(adev);
177 if (r)
178 return r;
179
180 jpeg_v1_0_sw_fini(handle);
181
182 r = amdgpu_vcn_sw_fini(adev);
183
184 return r;
185 }
186
187 /**
188 * vcn_v1_0_hw_init - start and test VCN block
189 *
190 * @handle: amdgpu_device pointer
191 *
192 * Initialize the hardware, boot up the VCPU and do some testing
193 */
vcn_v1_0_hw_init(void * handle)194 static int vcn_v1_0_hw_init(void *handle)
195 {
196 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
197 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
198 int i, r;
199
200 r = amdgpu_ring_test_helper(ring);
201 if (r)
202 goto done;
203
204 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
205 ring = &adev->vcn.inst->ring_enc[i];
206 r = amdgpu_ring_test_helper(ring);
207 if (r)
208 goto done;
209 }
210
211 ring = &adev->jpeg.inst->ring_dec;
212 r = amdgpu_ring_test_helper(ring);
213 if (r)
214 goto done;
215
216 done:
217 if (!r)
218 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
219 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
220
221 return r;
222 }
223
224 /**
225 * vcn_v1_0_hw_fini - stop the hardware block
226 *
227 * @handle: amdgpu_device pointer
228 *
229 * Stop the VCN block, mark ring as not ready any more
230 */
vcn_v1_0_hw_fini(void * handle)231 static int vcn_v1_0_hw_fini(void *handle)
232 {
233 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
234
235 cancel_delayed_work_sync(&adev->vcn.idle_work);
236
237 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
238 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
239 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
240 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
241 }
242
243 return 0;
244 }
245
246 /**
247 * vcn_v1_0_suspend - suspend VCN block
248 *
249 * @handle: amdgpu_device pointer
250 *
251 * HW fini and suspend VCN block
252 */
vcn_v1_0_suspend(void * handle)253 static int vcn_v1_0_suspend(void *handle)
254 {
255 int r;
256 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
257 bool idle_work_unexecuted;
258
259 idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work);
260 if (idle_work_unexecuted) {
261 if (adev->pm.dpm_enabled)
262 amdgpu_dpm_enable_uvd(adev, false);
263 }
264
265 r = vcn_v1_0_hw_fini(adev);
266 if (r)
267 return r;
268
269 r = amdgpu_vcn_suspend(adev);
270
271 return r;
272 }
273
274 /**
275 * vcn_v1_0_resume - resume VCN block
276 *
277 * @handle: amdgpu_device pointer
278 *
279 * Resume firmware and hw init VCN block
280 */
vcn_v1_0_resume(void * handle)281 static int vcn_v1_0_resume(void *handle)
282 {
283 int r;
284 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
285
286 r = amdgpu_vcn_resume(adev);
287 if (r)
288 return r;
289
290 r = vcn_v1_0_hw_init(adev);
291
292 return r;
293 }
294
295 /**
296 * vcn_v1_0_mc_resume_spg_mode - memory controller programming
297 *
298 * @adev: amdgpu_device pointer
299 *
300 * Let the VCN memory controller know it's offsets
301 */
vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device * adev)302 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
303 {
304 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
305 uint32_t offset;
306
307 /* cache window 0: fw */
308 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
309 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
310 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
311 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
312 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
313 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
314 offset = 0;
315 } else {
316 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
317 lower_32_bits(adev->vcn.inst->gpu_addr));
318 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
319 upper_32_bits(adev->vcn.inst->gpu_addr));
320 offset = size;
321 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
322 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
323 }
324
325 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
326
327 /* cache window 1: stack */
328 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
329 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
330 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
331 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
332 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
333 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
334
335 /* cache window 2: context */
336 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
337 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
338 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
339 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
340 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
341 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
342
343 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
344 adev->gfx.config.gb_addr_config);
345 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
346 adev->gfx.config.gb_addr_config);
347 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
348 adev->gfx.config.gb_addr_config);
349 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
350 adev->gfx.config.gb_addr_config);
351 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
352 adev->gfx.config.gb_addr_config);
353 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
354 adev->gfx.config.gb_addr_config);
355 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
356 adev->gfx.config.gb_addr_config);
357 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
358 adev->gfx.config.gb_addr_config);
359 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
360 adev->gfx.config.gb_addr_config);
361 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
362 adev->gfx.config.gb_addr_config);
363 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
364 adev->gfx.config.gb_addr_config);
365 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
366 adev->gfx.config.gb_addr_config);
367 }
368
vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device * adev)369 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
370 {
371 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
372 uint32_t offset;
373
374 /* cache window 0: fw */
375 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
376 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
377 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
378 0xFFFFFFFF, 0);
379 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
380 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi),
381 0xFFFFFFFF, 0);
382 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
383 0xFFFFFFFF, 0);
384 offset = 0;
385 } else {
386 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
387 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
388 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
389 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
390 offset = size;
391 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
392 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
393 }
394
395 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
396
397 /* cache window 1: stack */
398 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
399 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
400 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
401 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
402 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
403 0xFFFFFFFF, 0);
404 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
405 0xFFFFFFFF, 0);
406
407 /* cache window 2: context */
408 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
409 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
410 0xFFFFFFFF, 0);
411 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
412 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
413 0xFFFFFFFF, 0);
414 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
415 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
416 0xFFFFFFFF, 0);
417
418 /* VCN global tiling registers */
419 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
420 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
421 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
422 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
423 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
424 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
425 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
426 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
427 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
428 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
429 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
430 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
431 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
432 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
433 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
434 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
435 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
436 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
437 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
438 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
439 }
440
441 /**
442 * vcn_v1_0_disable_clock_gating - disable VCN clock gating
443 *
444 * @adev: amdgpu_device pointer
445 * @sw: enable SW clock gating
446 *
447 * Disable clock gating for VCN block
448 */
vcn_v1_0_disable_clock_gating(struct amdgpu_device * adev)449 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
450 {
451 uint32_t data;
452
453 /* JPEG disable CGC */
454 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
455
456 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
457 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
458 else
459 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
460
461 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
462 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
463 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
464
465 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
466 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
467 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
468
469 /* UVD disable CGC */
470 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
471 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
472 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
473 else
474 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
475
476 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
477 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
478 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
479
480 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
481 data &= ~(UVD_CGC_GATE__SYS_MASK
482 | UVD_CGC_GATE__UDEC_MASK
483 | UVD_CGC_GATE__MPEG2_MASK
484 | UVD_CGC_GATE__REGS_MASK
485 | UVD_CGC_GATE__RBC_MASK
486 | UVD_CGC_GATE__LMI_MC_MASK
487 | UVD_CGC_GATE__LMI_UMC_MASK
488 | UVD_CGC_GATE__IDCT_MASK
489 | UVD_CGC_GATE__MPRD_MASK
490 | UVD_CGC_GATE__MPC_MASK
491 | UVD_CGC_GATE__LBSI_MASK
492 | UVD_CGC_GATE__LRBBM_MASK
493 | UVD_CGC_GATE__UDEC_RE_MASK
494 | UVD_CGC_GATE__UDEC_CM_MASK
495 | UVD_CGC_GATE__UDEC_IT_MASK
496 | UVD_CGC_GATE__UDEC_DB_MASK
497 | UVD_CGC_GATE__UDEC_MP_MASK
498 | UVD_CGC_GATE__WCB_MASK
499 | UVD_CGC_GATE__VCPU_MASK
500 | UVD_CGC_GATE__SCPU_MASK);
501 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
502
503 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
504 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
505 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
506 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
507 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
508 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
509 | UVD_CGC_CTRL__SYS_MODE_MASK
510 | UVD_CGC_CTRL__UDEC_MODE_MASK
511 | UVD_CGC_CTRL__MPEG2_MODE_MASK
512 | UVD_CGC_CTRL__REGS_MODE_MASK
513 | UVD_CGC_CTRL__RBC_MODE_MASK
514 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
515 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
516 | UVD_CGC_CTRL__IDCT_MODE_MASK
517 | UVD_CGC_CTRL__MPRD_MODE_MASK
518 | UVD_CGC_CTRL__MPC_MODE_MASK
519 | UVD_CGC_CTRL__LBSI_MODE_MASK
520 | UVD_CGC_CTRL__LRBBM_MODE_MASK
521 | UVD_CGC_CTRL__WCB_MODE_MASK
522 | UVD_CGC_CTRL__VCPU_MODE_MASK
523 | UVD_CGC_CTRL__SCPU_MODE_MASK);
524 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
525
526 /* turn on */
527 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
528 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
529 | UVD_SUVD_CGC_GATE__SIT_MASK
530 | UVD_SUVD_CGC_GATE__SMP_MASK
531 | UVD_SUVD_CGC_GATE__SCM_MASK
532 | UVD_SUVD_CGC_GATE__SDB_MASK
533 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
534 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
535 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
536 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
537 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
538 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
539 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
540 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
541 | UVD_SUVD_CGC_GATE__SCLR_MASK
542 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
543 | UVD_SUVD_CGC_GATE__ENT_MASK
544 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
545 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
546 | UVD_SUVD_CGC_GATE__SITE_MASK
547 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
548 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
549 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
550 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
551 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
552 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
553
554 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
555 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
556 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
557 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
558 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
559 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
560 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
561 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
562 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
563 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
564 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
565 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
566 }
567
568 /**
569 * vcn_v1_0_enable_clock_gating - enable VCN clock gating
570 *
571 * @adev: amdgpu_device pointer
572 * @sw: enable SW clock gating
573 *
574 * Enable clock gating for VCN block
575 */
vcn_v1_0_enable_clock_gating(struct amdgpu_device * adev)576 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
577 {
578 uint32_t data = 0;
579
580 /* enable JPEG CGC */
581 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
582 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
583 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
584 else
585 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
586 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
587 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
588 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
589
590 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
591 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
592 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
593
594 /* enable UVD CGC */
595 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
596 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
597 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
598 else
599 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
600 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
601 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
602 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
603
604 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
605 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
606 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
607 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
608 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
609 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
610 | UVD_CGC_CTRL__SYS_MODE_MASK
611 | UVD_CGC_CTRL__UDEC_MODE_MASK
612 | UVD_CGC_CTRL__MPEG2_MODE_MASK
613 | UVD_CGC_CTRL__REGS_MODE_MASK
614 | UVD_CGC_CTRL__RBC_MODE_MASK
615 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
616 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
617 | UVD_CGC_CTRL__IDCT_MODE_MASK
618 | UVD_CGC_CTRL__MPRD_MODE_MASK
619 | UVD_CGC_CTRL__MPC_MODE_MASK
620 | UVD_CGC_CTRL__LBSI_MODE_MASK
621 | UVD_CGC_CTRL__LRBBM_MODE_MASK
622 | UVD_CGC_CTRL__WCB_MODE_MASK
623 | UVD_CGC_CTRL__VCPU_MODE_MASK
624 | UVD_CGC_CTRL__SCPU_MODE_MASK);
625 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
626
627 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
628 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
629 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
630 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
631 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
632 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
633 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
634 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
635 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
636 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
637 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
638 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
639 }
640
vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device * adev,uint8_t sram_sel)641 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
642 {
643 uint32_t reg_data = 0;
644
645 /* disable JPEG CGC */
646 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
647 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
648 else
649 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
650 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
651 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
652 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
653
654 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
655
656 /* enable sw clock gating control */
657 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
658 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
659 else
660 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
661 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
662 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
663 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
664 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
665 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
666 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
667 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
668 UVD_CGC_CTRL__SYS_MODE_MASK |
669 UVD_CGC_CTRL__UDEC_MODE_MASK |
670 UVD_CGC_CTRL__MPEG2_MODE_MASK |
671 UVD_CGC_CTRL__REGS_MODE_MASK |
672 UVD_CGC_CTRL__RBC_MODE_MASK |
673 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
674 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
675 UVD_CGC_CTRL__IDCT_MODE_MASK |
676 UVD_CGC_CTRL__MPRD_MODE_MASK |
677 UVD_CGC_CTRL__MPC_MODE_MASK |
678 UVD_CGC_CTRL__LBSI_MODE_MASK |
679 UVD_CGC_CTRL__LRBBM_MODE_MASK |
680 UVD_CGC_CTRL__WCB_MODE_MASK |
681 UVD_CGC_CTRL__VCPU_MODE_MASK |
682 UVD_CGC_CTRL__SCPU_MODE_MASK);
683 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
684
685 /* turn off clock gating */
686 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
687
688 /* turn on SUVD clock gating */
689 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
690
691 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
692 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
693 }
694
vcn_1_0_disable_static_power_gating(struct amdgpu_device * adev)695 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
696 {
697 uint32_t data = 0;
698
699 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
700 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
701 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
702 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
703 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
704 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
705 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
706 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
707 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
708 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
709 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
710 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
711
712 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
713 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF);
714 } else {
715 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
716 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
717 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
718 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
719 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
720 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
721 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
722 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
723 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
724 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
725 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
726 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
727 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF);
728 }
729
730 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
731
732 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
733 data &= ~0x103;
734 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
735 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
736
737 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
738 }
739
vcn_1_0_enable_static_power_gating(struct amdgpu_device * adev)740 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
741 {
742 uint32_t data = 0;
743
744 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
745 /* Before power off, this indicator has to be turned on */
746 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
747 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
748 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
749 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
750
751
752 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
753 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
754 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
755 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
756 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
757 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
758 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
759 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
760 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
761 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
762 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
763
764 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
765
766 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
767 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
768 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
769 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
770 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
771 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
772 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
773 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
774 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
775 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
776 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
777 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF);
778 }
779 }
780
781 /**
782 * vcn_v1_0_start - start VCN block
783 *
784 * @adev: amdgpu_device pointer
785 *
786 * Setup and start the VCN block
787 */
vcn_v1_0_start_spg_mode(struct amdgpu_device * adev)788 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
789 {
790 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
791 uint32_t rb_bufsz, tmp;
792 uint32_t lmi_swap_cntl;
793 int i, j, r;
794
795 /* disable byte swapping */
796 lmi_swap_cntl = 0;
797
798 vcn_1_0_disable_static_power_gating(adev);
799
800 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
801 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
802
803 /* disable clock gating */
804 vcn_v1_0_disable_clock_gating(adev);
805
806 /* disable interupt */
807 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
808 ~UVD_MASTINT_EN__VCPU_EN_MASK);
809
810 /* initialize VCN memory controller */
811 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
812 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
813 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
814 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
815 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
816 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
817
818 #ifdef __BIG_ENDIAN
819 /* swap (8 in 32) RB and IB */
820 lmi_swap_cntl = 0xa;
821 #endif
822 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
823
824 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
825 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
826 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
827 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
828
829 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
830 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
831 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
832 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
833 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
834
835 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
836 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
837 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
838 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
839 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
840
841 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
842 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
843 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
844 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
845
846 vcn_v1_0_mc_resume_spg_mode(adev);
847
848 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10);
849 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0,
850 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3);
851
852 /* enable VCPU clock */
853 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
854
855 /* boot up the VCPU */
856 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
857 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
858
859 /* enable UMC */
860 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
861 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
862
863 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
864 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
865 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
866 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
867
868 for (i = 0; i < 10; ++i) {
869 uint32_t status;
870
871 for (j = 0; j < 100; ++j) {
872 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
873 if (status & UVD_STATUS__IDLE)
874 break;
875 mdelay(10);
876 }
877 r = 0;
878 if (status & UVD_STATUS__IDLE)
879 break;
880
881 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
882 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
883 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
884 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
885 mdelay(10);
886 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
887 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
888 mdelay(10);
889 r = -1;
890 }
891
892 if (r) {
893 DRM_ERROR("VCN decode not responding, giving up!!!\n");
894 return r;
895 }
896 /* enable master interrupt */
897 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
898 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK);
899
900 /* enable system interrupt for JRBC, TODO: move to set interrupt*/
901 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
902 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
903 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
904
905 /* clear the busy bit of UVD_STATUS */
906 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
907 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
908
909 /* force RBC into idle state */
910 rb_bufsz = order_base_2(ring->ring_size);
911 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
912 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
913 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
914 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
915 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
916 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
917
918 /* set the write pointer delay */
919 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
920
921 /* set the wb address */
922 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
923 (upper_32_bits(ring->gpu_addr) >> 2));
924
925 /* program the RB_BASE for ring buffer */
926 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
927 lower_32_bits(ring->gpu_addr));
928 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
929 upper_32_bits(ring->gpu_addr));
930
931 /* Initialize the ring buffer's read and write pointers */
932 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
933
934 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
935
936 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
937 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
938 lower_32_bits(ring->wptr));
939
940 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
941 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
942
943 ring = &adev->vcn.inst->ring_enc[0];
944 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
945 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
946 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
947 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
948 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
949
950 ring = &adev->vcn.inst->ring_enc[1];
951 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
952 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
953 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
954 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
955 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
956
957 jpeg_v1_0_start(adev, 0);
958
959 return 0;
960 }
961
vcn_v1_0_start_dpg_mode(struct amdgpu_device * adev)962 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
963 {
964 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
965 uint32_t rb_bufsz, tmp;
966 uint32_t lmi_swap_cntl;
967
968 /* disable byte swapping */
969 lmi_swap_cntl = 0;
970
971 vcn_1_0_enable_static_power_gating(adev);
972
973 /* enable dynamic power gating mode */
974 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
975 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
976 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
977 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
978
979 /* enable clock gating */
980 vcn_v1_0_clock_gating_dpg_mode(adev, 0);
981
982 /* enable VCPU clock */
983 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
984 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
985 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
986 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
987
988 /* disable interupt */
989 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
990 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
991
992 /* initialize VCN memory controller */
993 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
994 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
995 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
996 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
997 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
998 UVD_LMI_CTRL__REQ_MODE_MASK |
999 UVD_LMI_CTRL__CRC_RESET_MASK |
1000 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1001 0x00100000L, 0xFFFFFFFF, 0);
1002
1003 #ifdef __BIG_ENDIAN
1004 /* swap (8 in 32) RB and IB */
1005 lmi_swap_cntl = 0xa;
1006 #endif
1007 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
1008
1009 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL,
1010 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
1011
1012 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0,
1013 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1014 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1015 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1016 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
1017
1018 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0,
1019 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1020 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1021 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1022 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
1023
1024 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX,
1025 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1026 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1027 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
1028
1029 vcn_v1_0_mc_resume_dpg_mode(adev);
1030
1031 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
1032 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
1033
1034 /* boot up the VCPU */
1035 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
1036
1037 /* enable UMC */
1038 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2,
1039 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
1040 0xFFFFFFFF, 0);
1041
1042 /* enable master interrupt */
1043 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
1044 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
1045
1046 vcn_v1_0_clock_gating_dpg_mode(adev, 1);
1047 /* setup mmUVD_LMI_CTRL */
1048 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
1049 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1050 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1051 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1052 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1053 UVD_LMI_CTRL__REQ_MODE_MASK |
1054 UVD_LMI_CTRL__CRC_RESET_MASK |
1055 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1056 0x00100000L, 0xFFFFFFFF, 1);
1057
1058 tmp = adev->gfx.config.gb_addr_config;
1059 /* setup VCN global tiling registers */
1060 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1061 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1062
1063 /* enable System Interrupt for JRBC */
1064 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN,
1065 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1);
1066
1067 /* force RBC into idle state */
1068 rb_bufsz = order_base_2(ring->ring_size);
1069 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1070 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1071 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1072 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1073 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1074 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1075
1076 /* set the write pointer delay */
1077 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1078
1079 /* set the wb address */
1080 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1081 (upper_32_bits(ring->gpu_addr) >> 2));
1082
1083 /* program the RB_BASE for ring buffer */
1084 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1085 lower_32_bits(ring->gpu_addr));
1086 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1087 upper_32_bits(ring->gpu_addr));
1088
1089 /* Initialize the ring buffer's read and write pointers */
1090 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1091
1092 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
1093
1094 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1095 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1096 lower_32_bits(ring->wptr));
1097
1098 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1099 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1100
1101 jpeg_v1_0_start(adev, 1);
1102
1103 return 0;
1104 }
1105
vcn_v1_0_start(struct amdgpu_device * adev)1106 static int vcn_v1_0_start(struct amdgpu_device *adev)
1107 {
1108 int r;
1109
1110 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1111 r = vcn_v1_0_start_dpg_mode(adev);
1112 else
1113 r = vcn_v1_0_start_spg_mode(adev);
1114 return r;
1115 }
1116
1117 /**
1118 * vcn_v1_0_stop - stop VCN block
1119 *
1120 * @adev: amdgpu_device pointer
1121 *
1122 * stop the VCN block
1123 */
vcn_v1_0_stop_spg_mode(struct amdgpu_device * adev)1124 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
1125 {
1126 int tmp;
1127
1128 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1129
1130 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1131 UVD_LMI_STATUS__READ_CLEAN_MASK |
1132 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1133 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1134 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1135
1136 /* put VCPU into reset */
1137 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1138 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1139 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1140
1141 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1142 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1143 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1144
1145 /* disable VCPU clock */
1146 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1147 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1148
1149 /* reset LMI UMC/LMI */
1150 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1151 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1152 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1153
1154 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1155 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1156 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1157
1158 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1159
1160 vcn_v1_0_enable_clock_gating(adev);
1161 vcn_1_0_enable_static_power_gating(adev);
1162 return 0;
1163 }
1164
vcn_v1_0_stop_dpg_mode(struct amdgpu_device * adev)1165 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
1166 {
1167 uint32_t tmp;
1168
1169 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
1170 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1171 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1172 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1173
1174 /* wait for read ptr to be equal to write ptr */
1175 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1176 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1177
1178 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1179 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1180
1181 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1182 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF);
1183
1184 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1185 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1186
1187 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1188 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1189 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1190
1191 /* disable dynamic power gating mode */
1192 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1193 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1194
1195 return 0;
1196 }
1197
vcn_v1_0_stop(struct amdgpu_device * adev)1198 static int vcn_v1_0_stop(struct amdgpu_device *adev)
1199 {
1200 int r;
1201
1202 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1203 r = vcn_v1_0_stop_dpg_mode(adev);
1204 else
1205 r = vcn_v1_0_stop_spg_mode(adev);
1206
1207 return r;
1208 }
1209
vcn_v1_0_pause_dpg_mode(struct amdgpu_device * adev,int inst_idx,struct dpg_pause_state * new_state)1210 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
1211 int inst_idx, struct dpg_pause_state *new_state)
1212 {
1213 int ret_code;
1214 uint32_t reg_data = 0;
1215 uint32_t reg_data2 = 0;
1216 struct amdgpu_ring *ring;
1217
1218 /* pause/unpause if state is changed */
1219 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1220 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1221 adev->vcn.inst[inst_idx].pause_state.fw_based,
1222 adev->vcn.inst[inst_idx].pause_state.jpeg,
1223 new_state->fw_based, new_state->jpeg);
1224
1225 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1226 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1227
1228 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1229 ret_code = 0;
1230
1231 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK))
1232 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1233 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1234 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1235
1236 if (!ret_code) {
1237 /* pause DPG non-jpeg */
1238 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1239 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1240 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1241 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1242 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1243
1244 /* Restore */
1245 ring = &adev->vcn.inst->ring_enc[0];
1246 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1247 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1248 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1249 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1250 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1251
1252 ring = &adev->vcn.inst->ring_enc[1];
1253 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1254 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1255 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1256 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1257 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1258
1259 ring = &adev->vcn.inst->ring_dec;
1260 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1261 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1262 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1263 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1264 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1265 }
1266 } else {
1267 /* unpause dpg non-jpeg, no need to wait */
1268 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1269 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1270 }
1271 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1272 }
1273
1274 /* pause/unpause if state is changed */
1275 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {
1276 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1277 adev->vcn.inst[inst_idx].pause_state.fw_based,
1278 adev->vcn.inst[inst_idx].pause_state.jpeg,
1279 new_state->fw_based, new_state->jpeg);
1280
1281 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1282 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1283
1284 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) {
1285 ret_code = 0;
1286
1287 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK))
1288 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1289 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1290 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1291
1292 if (!ret_code) {
1293 /* Make sure JPRG Snoop is disabled before sending the pause */
1294 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
1295 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK;
1296 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);
1297
1298 /* pause DPG jpeg */
1299 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1300 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1301 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1302 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK,
1303 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1304
1305 /* Restore */
1306 ring = &adev->jpeg.inst->ring_dec;
1307 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
1308 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1309 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
1310 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1311 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
1312 lower_32_bits(ring->gpu_addr));
1313 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
1314 upper_32_bits(ring->gpu_addr));
1315 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
1316 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
1317 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1318 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1319
1320 ring = &adev->vcn.inst->ring_dec;
1321 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1322 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1323 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1324 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1325 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1326 }
1327 } else {
1328 /* unpause dpg jpeg, no need to wait */
1329 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1330 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1331 }
1332 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;
1333 }
1334
1335 return 0;
1336 }
1337
vcn_v1_0_is_idle(void * handle)1338 static bool vcn_v1_0_is_idle(void *handle)
1339 {
1340 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1341
1342 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1343 }
1344
vcn_v1_0_wait_for_idle(void * handle)1345 static int vcn_v1_0_wait_for_idle(void *handle)
1346 {
1347 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1348 int ret;
1349
1350 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1351 UVD_STATUS__IDLE);
1352
1353 return ret;
1354 }
1355
vcn_v1_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1356 static int vcn_v1_0_set_clockgating_state(void *handle,
1357 enum amd_clockgating_state state)
1358 {
1359 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1360 bool enable = (state == AMD_CG_STATE_GATE);
1361
1362 if (enable) {
1363 /* wait for STATUS to clear */
1364 if (!vcn_v1_0_is_idle(handle))
1365 return -EBUSY;
1366 vcn_v1_0_enable_clock_gating(adev);
1367 } else {
1368 /* disable HW gating and enable Sw gating */
1369 vcn_v1_0_disable_clock_gating(adev);
1370 }
1371 return 0;
1372 }
1373
1374 /**
1375 * vcn_v1_0_dec_ring_get_rptr - get read pointer
1376 *
1377 * @ring: amdgpu_ring pointer
1378 *
1379 * Returns the current hardware read pointer
1380 */
vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring * ring)1381 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1382 {
1383 struct amdgpu_device *adev = ring->adev;
1384
1385 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1386 }
1387
1388 /**
1389 * vcn_v1_0_dec_ring_get_wptr - get write pointer
1390 *
1391 * @ring: amdgpu_ring pointer
1392 *
1393 * Returns the current hardware write pointer
1394 */
vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring * ring)1395 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1396 {
1397 struct amdgpu_device *adev = ring->adev;
1398
1399 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1400 }
1401
1402 /**
1403 * vcn_v1_0_dec_ring_set_wptr - set write pointer
1404 *
1405 * @ring: amdgpu_ring pointer
1406 *
1407 * Commits the write pointer to the hardware
1408 */
vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring * ring)1409 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1410 {
1411 struct amdgpu_device *adev = ring->adev;
1412
1413 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1414 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1415 lower_32_bits(ring->wptr) | 0x80000000);
1416
1417 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1418 }
1419
1420 /**
1421 * vcn_v1_0_dec_ring_insert_start - insert a start command
1422 *
1423 * @ring: amdgpu_ring pointer
1424 *
1425 * Write a start command to the ring.
1426 */
vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring * ring)1427 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1428 {
1429 struct amdgpu_device *adev = ring->adev;
1430
1431 amdgpu_ring_write(ring,
1432 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1433 amdgpu_ring_write(ring, 0);
1434 amdgpu_ring_write(ring,
1435 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1436 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1437 }
1438
1439 /**
1440 * vcn_v1_0_dec_ring_insert_end - insert a end command
1441 *
1442 * @ring: amdgpu_ring pointer
1443 *
1444 * Write a end command to the ring.
1445 */
vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring * ring)1446 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1447 {
1448 struct amdgpu_device *adev = ring->adev;
1449
1450 amdgpu_ring_write(ring,
1451 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1452 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1453 }
1454
1455 /**
1456 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
1457 *
1458 * @ring: amdgpu_ring pointer
1459 * @fence: fence to emit
1460 *
1461 * Write a fence and a trap command to the ring.
1462 */
vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1463 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1464 unsigned flags)
1465 {
1466 struct amdgpu_device *adev = ring->adev;
1467
1468 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1469
1470 amdgpu_ring_write(ring,
1471 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1472 amdgpu_ring_write(ring, seq);
1473 amdgpu_ring_write(ring,
1474 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1475 amdgpu_ring_write(ring, addr & 0xffffffff);
1476 amdgpu_ring_write(ring,
1477 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1478 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1479 amdgpu_ring_write(ring,
1480 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1481 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1482
1483 amdgpu_ring_write(ring,
1484 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1485 amdgpu_ring_write(ring, 0);
1486 amdgpu_ring_write(ring,
1487 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1488 amdgpu_ring_write(ring, 0);
1489 amdgpu_ring_write(ring,
1490 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1491 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1492 }
1493
1494 /**
1495 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
1496 *
1497 * @ring: amdgpu_ring pointer
1498 * @ib: indirect buffer to execute
1499 *
1500 * Write ring commands to execute the indirect buffer
1501 */
vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1502 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1503 struct amdgpu_job *job,
1504 struct amdgpu_ib *ib,
1505 uint32_t flags)
1506 {
1507 struct amdgpu_device *adev = ring->adev;
1508 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1509
1510 amdgpu_ring_write(ring,
1511 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1512 amdgpu_ring_write(ring, vmid);
1513
1514 amdgpu_ring_write(ring,
1515 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1516 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1517 amdgpu_ring_write(ring,
1518 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1519 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1520 amdgpu_ring_write(ring,
1521 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1522 amdgpu_ring_write(ring, ib->length_dw);
1523 }
1524
vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1525 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
1526 uint32_t reg, uint32_t val,
1527 uint32_t mask)
1528 {
1529 struct amdgpu_device *adev = ring->adev;
1530
1531 amdgpu_ring_write(ring,
1532 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1533 amdgpu_ring_write(ring, reg << 2);
1534 amdgpu_ring_write(ring,
1535 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1536 amdgpu_ring_write(ring, val);
1537 amdgpu_ring_write(ring,
1538 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1539 amdgpu_ring_write(ring, mask);
1540 amdgpu_ring_write(ring,
1541 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1542 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1543 }
1544
vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1545 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1546 unsigned vmid, uint64_t pd_addr)
1547 {
1548 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1549 uint32_t data0, data1, mask;
1550
1551 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1552
1553 /* wait for register write */
1554 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1555 data1 = lower_32_bits(pd_addr);
1556 mask = 0xffffffff;
1557 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1558 }
1559
vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1560 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1561 uint32_t reg, uint32_t val)
1562 {
1563 struct amdgpu_device *adev = ring->adev;
1564
1565 amdgpu_ring_write(ring,
1566 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1567 amdgpu_ring_write(ring, reg << 2);
1568 amdgpu_ring_write(ring,
1569 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1570 amdgpu_ring_write(ring, val);
1571 amdgpu_ring_write(ring,
1572 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1573 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1574 }
1575
1576 /**
1577 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
1578 *
1579 * @ring: amdgpu_ring pointer
1580 *
1581 * Returns the current hardware enc read pointer
1582 */
vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring * ring)1583 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1584 {
1585 struct amdgpu_device *adev = ring->adev;
1586
1587 if (ring == &adev->vcn.inst->ring_enc[0])
1588 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1589 else
1590 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1591 }
1592
1593 /**
1594 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
1595 *
1596 * @ring: amdgpu_ring pointer
1597 *
1598 * Returns the current hardware enc write pointer
1599 */
vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring * ring)1600 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1601 {
1602 struct amdgpu_device *adev = ring->adev;
1603
1604 if (ring == &adev->vcn.inst->ring_enc[0])
1605 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1606 else
1607 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1608 }
1609
1610 /**
1611 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
1612 *
1613 * @ring: amdgpu_ring pointer
1614 *
1615 * Commits the enc write pointer to the hardware
1616 */
vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring * ring)1617 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1618 {
1619 struct amdgpu_device *adev = ring->adev;
1620
1621 if (ring == &adev->vcn.inst->ring_enc[0])
1622 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1623 lower_32_bits(ring->wptr));
1624 else
1625 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
1626 lower_32_bits(ring->wptr));
1627 }
1628
1629 /**
1630 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
1631 *
1632 * @ring: amdgpu_ring pointer
1633 * @fence: fence to emit
1634 *
1635 * Write enc a fence and a trap command to the ring.
1636 */
vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1637 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1638 u64 seq, unsigned flags)
1639 {
1640 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1641
1642 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1643 amdgpu_ring_write(ring, addr);
1644 amdgpu_ring_write(ring, upper_32_bits(addr));
1645 amdgpu_ring_write(ring, seq);
1646 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1647 }
1648
vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring * ring)1649 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1650 {
1651 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1652 }
1653
1654 /**
1655 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
1656 *
1657 * @ring: amdgpu_ring pointer
1658 * @ib: indirect buffer to execute
1659 *
1660 * Write enc ring commands to execute the indirect buffer
1661 */
vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1662 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1663 struct amdgpu_job *job,
1664 struct amdgpu_ib *ib,
1665 uint32_t flags)
1666 {
1667 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1668
1669 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1670 amdgpu_ring_write(ring, vmid);
1671 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1672 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1673 amdgpu_ring_write(ring, ib->length_dw);
1674 }
1675
vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1676 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1677 uint32_t reg, uint32_t val,
1678 uint32_t mask)
1679 {
1680 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1681 amdgpu_ring_write(ring, reg << 2);
1682 amdgpu_ring_write(ring, mask);
1683 amdgpu_ring_write(ring, val);
1684 }
1685
vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)1686 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1687 unsigned int vmid, uint64_t pd_addr)
1688 {
1689 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1690
1691 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1692
1693 /* wait for reg writes */
1694 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1695 vmid * hub->ctx_addr_distance,
1696 lower_32_bits(pd_addr), 0xffffffff);
1697 }
1698
vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1699 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1700 uint32_t reg, uint32_t val)
1701 {
1702 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1703 amdgpu_ring_write(ring, reg << 2);
1704 amdgpu_ring_write(ring, val);
1705 }
1706
vcn_v1_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1707 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
1708 struct amdgpu_irq_src *source,
1709 unsigned type,
1710 enum amdgpu_interrupt_state state)
1711 {
1712 return 0;
1713 }
1714
vcn_v1_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1715 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
1716 struct amdgpu_irq_src *source,
1717 struct amdgpu_iv_entry *entry)
1718 {
1719 DRM_DEBUG("IH: VCN TRAP\n");
1720
1721 switch (entry->src_id) {
1722 case 124:
1723 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1724 break;
1725 case 119:
1726 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1727 break;
1728 case 120:
1729 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1730 break;
1731 default:
1732 DRM_ERROR("Unhandled interrupt: %d %d\n",
1733 entry->src_id, entry->src_data[0]);
1734 break;
1735 }
1736
1737 return 0;
1738 }
1739
vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)1740 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1741 {
1742 struct amdgpu_device *adev = ring->adev;
1743 int i;
1744
1745 WARN_ON(ring->wptr % 2 || count % 2);
1746
1747 for (i = 0; i < count / 2; i++) {
1748 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1749 amdgpu_ring_write(ring, 0);
1750 }
1751 }
1752
vcn_v1_0_set_powergating_state(void * handle,enum amd_powergating_state state)1753 static int vcn_v1_0_set_powergating_state(void *handle,
1754 enum amd_powergating_state state)
1755 {
1756 /* This doesn't actually powergate the VCN block.
1757 * That's done in the dpm code via the SMC. This
1758 * just re-inits the block as necessary. The actual
1759 * gating still happens in the dpm code. We should
1760 * revisit this when there is a cleaner line between
1761 * the smc and the hw blocks
1762 */
1763 int ret;
1764 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1765
1766 if(state == adev->vcn.cur_state)
1767 return 0;
1768
1769 if (state == AMD_PG_STATE_GATE)
1770 ret = vcn_v1_0_stop(adev);
1771 else
1772 ret = vcn_v1_0_start(adev);
1773
1774 if(!ret)
1775 adev->vcn.cur_state = state;
1776 return ret;
1777 }
1778
vcn_v1_0_idle_work_handler(struct work_struct * work)1779 static void vcn_v1_0_idle_work_handler(struct work_struct *work)
1780 {
1781 struct amdgpu_device *adev =
1782 container_of(work, struct amdgpu_device, vcn.idle_work.work);
1783 unsigned int fences = 0, i;
1784
1785 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1786 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1787
1788 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1789 struct dpg_pause_state new_state;
1790
1791 if (fences)
1792 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1793 else
1794 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1795
1796 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec))
1797 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1798 else
1799 new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1800
1801 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1802 }
1803
1804 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec);
1805 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec);
1806
1807 if (fences == 0) {
1808 amdgpu_gfx_off_ctrl(adev, true);
1809 if (adev->pm.dpm_enabled)
1810 amdgpu_dpm_enable_uvd(adev, false);
1811 else
1812 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1813 AMD_PG_STATE_GATE);
1814 } else {
1815 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1816 }
1817 }
1818
vcn_v1_0_ring_begin_use(struct amdgpu_ring * ring)1819 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
1820 {
1821 struct amdgpu_device *adev = ring->adev;
1822 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
1823
1824 mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
1825
1826 if (amdgpu_fence_wait_empty(&ring->adev->jpeg.inst->ring_dec))
1827 DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n");
1828
1829 vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
1830
1831 }
1832
vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring * ring,bool set_clocks)1833 void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
1834 {
1835 struct amdgpu_device *adev = ring->adev;
1836
1837 if (set_clocks) {
1838 amdgpu_gfx_off_ctrl(adev, false);
1839 if (adev->pm.dpm_enabled)
1840 amdgpu_dpm_enable_uvd(adev, true);
1841 else
1842 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1843 AMD_PG_STATE_UNGATE);
1844 }
1845
1846 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1847 struct dpg_pause_state new_state;
1848 unsigned int fences = 0, i;
1849
1850 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1851 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1852
1853 if (fences)
1854 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1855 else
1856 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1857
1858 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec))
1859 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1860 else
1861 new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1862
1863 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
1864 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1865 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
1866 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1867
1868 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1869 }
1870 }
1871
vcn_v1_0_ring_end_use(struct amdgpu_ring * ring)1872 void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
1873 {
1874 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1875 mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);
1876 }
1877
1878 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
1879 .name = "vcn_v1_0",
1880 .early_init = vcn_v1_0_early_init,
1881 .late_init = NULL,
1882 .sw_init = vcn_v1_0_sw_init,
1883 .sw_fini = vcn_v1_0_sw_fini,
1884 .hw_init = vcn_v1_0_hw_init,
1885 .hw_fini = vcn_v1_0_hw_fini,
1886 .suspend = vcn_v1_0_suspend,
1887 .resume = vcn_v1_0_resume,
1888 .is_idle = vcn_v1_0_is_idle,
1889 .wait_for_idle = vcn_v1_0_wait_for_idle,
1890 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,
1891 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,
1892 .soft_reset = NULL /* vcn_v1_0_soft_reset */,
1893 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
1894 .set_clockgating_state = vcn_v1_0_set_clockgating_state,
1895 .set_powergating_state = vcn_v1_0_set_powergating_state,
1896 };
1897
1898 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
1899 .type = AMDGPU_RING_TYPE_VCN_DEC,
1900 .align_mask = 0xf,
1901 .support_64bit_ptrs = false,
1902 .no_user_fence = true,
1903 .vmhub = AMDGPU_MMHUB_0,
1904 .get_rptr = vcn_v1_0_dec_ring_get_rptr,
1905 .get_wptr = vcn_v1_0_dec_ring_get_wptr,
1906 .set_wptr = vcn_v1_0_dec_ring_set_wptr,
1907 .emit_frame_size =
1908 6 + 6 + /* hdp invalidate / flush */
1909 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1910 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1911 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
1912 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
1913 6,
1914 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
1915 .emit_ib = vcn_v1_0_dec_ring_emit_ib,
1916 .emit_fence = vcn_v1_0_dec_ring_emit_fence,
1917 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
1918 .test_ring = amdgpu_vcn_dec_ring_test_ring,
1919 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1920 .insert_nop = vcn_v1_0_dec_ring_insert_nop,
1921 .insert_start = vcn_v1_0_dec_ring_insert_start,
1922 .insert_end = vcn_v1_0_dec_ring_insert_end,
1923 .pad_ib = amdgpu_ring_generic_pad_ib,
1924 .begin_use = vcn_v1_0_ring_begin_use,
1925 .end_use = vcn_v1_0_ring_end_use,
1926 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
1927 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
1928 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1929 };
1930
1931 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
1932 .type = AMDGPU_RING_TYPE_VCN_ENC,
1933 .align_mask = 0x3f,
1934 .nop = VCN_ENC_CMD_NO_OP,
1935 .support_64bit_ptrs = false,
1936 .no_user_fence = true,
1937 .vmhub = AMDGPU_MMHUB_0,
1938 .get_rptr = vcn_v1_0_enc_ring_get_rptr,
1939 .get_wptr = vcn_v1_0_enc_ring_get_wptr,
1940 .set_wptr = vcn_v1_0_enc_ring_set_wptr,
1941 .emit_frame_size =
1942 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1943 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1944 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
1945 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
1946 1, /* vcn_v1_0_enc_ring_insert_end */
1947 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
1948 .emit_ib = vcn_v1_0_enc_ring_emit_ib,
1949 .emit_fence = vcn_v1_0_enc_ring_emit_fence,
1950 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
1951 .test_ring = amdgpu_vcn_enc_ring_test_ring,
1952 .test_ib = amdgpu_vcn_enc_ring_test_ib,
1953 .insert_nop = amdgpu_ring_insert_nop,
1954 .insert_end = vcn_v1_0_enc_ring_insert_end,
1955 .pad_ib = amdgpu_ring_generic_pad_ib,
1956 .begin_use = vcn_v1_0_ring_begin_use,
1957 .end_use = vcn_v1_0_ring_end_use,
1958 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
1959 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
1960 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1961 };
1962
vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device * adev)1963 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
1964 {
1965 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
1966 DRM_INFO("VCN decode is enabled in VM mode\n");
1967 }
1968
vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device * adev)1969 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1970 {
1971 int i;
1972
1973 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1974 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
1975
1976 DRM_INFO("VCN encode is enabled in VM mode\n");
1977 }
1978
1979 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
1980 .set = vcn_v1_0_set_interrupt_state,
1981 .process = vcn_v1_0_process_interrupt,
1982 };
1983
vcn_v1_0_set_irq_funcs(struct amdgpu_device * adev)1984 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
1985 {
1986 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2;
1987 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs;
1988 }
1989
1990 const struct amdgpu_ip_block_version vcn_v1_0_ip_block =
1991 {
1992 .type = AMD_IP_BLOCK_TYPE_VCN,
1993 .major = 1,
1994 .minor = 0,
1995 .rev = 0,
1996 .funcs = &vcn_v1_0_ip_funcs,
1997 };
1998