1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Samsung SoC MIPI DSI Master driver.
4 *
5 * Copyright (c) 2014 Samsung Electronics Co., Ltd
6 *
7 * Contacts: Tomasz Figa <t.figa@samsung.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/component.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/irq.h>
15 #include <linux/of_device.h>
16 #include <linux/of_gpio.h>
17 #include <linux/of_graph.h>
18 #include <linux/phy/phy.h>
19 #include <linux/regulator/consumer.h>
20
21 #include <asm/unaligned.h>
22
23 #include <video/mipi_display.h>
24 #include <video/videomode.h>
25
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_bridge.h>
28 #include <drm/drm_fb_helper.h>
29 #include <drm/drm_mipi_dsi.h>
30 #include <drm/drm_panel.h>
31 #include <drm/drm_print.h>
32 #include <drm/drm_probe_helper.h>
33 #include <drm/drm_simple_kms_helper.h>
34
35 #include "exynos_drm_crtc.h"
36 #include "exynos_drm_drv.h"
37
38 /* returns true iff both arguments logically differs */
39 #define NEQV(a, b) (!(a) ^ !(b))
40
41 /* DSIM_STATUS */
42 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
43 #define DSIM_STOP_STATE_CLK (1 << 8)
44 #define DSIM_TX_READY_HS_CLK (1 << 10)
45 #define DSIM_PLL_STABLE (1 << 31)
46
47 /* DSIM_SWRST */
48 #define DSIM_FUNCRST (1 << 16)
49 #define DSIM_SWRST (1 << 0)
50
51 /* DSIM_TIMEOUT */
52 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
53 #define DSIM_BTA_TIMEOUT(x) ((x) << 16)
54
55 /* DSIM_CLKCTRL */
56 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
57 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
58 #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19)
59 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
60 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
61 #define DSIM_BYTE_CLKEN (1 << 24)
62 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
63 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
64 #define DSIM_PLL_BYPASS (1 << 27)
65 #define DSIM_ESC_CLKEN (1 << 28)
66 #define DSIM_TX_REQUEST_HSCLK (1 << 31)
67
68 /* DSIM_CONFIG */
69 #define DSIM_LANE_EN_CLK (1 << 0)
70 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
71 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
72 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
73 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
74 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
75 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
76 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
77 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
78 #define DSIM_SUB_VC (((x) & 0x3) << 16)
79 #define DSIM_MAIN_VC (((x) & 0x3) << 18)
80 #define DSIM_HSA_MODE (1 << 20)
81 #define DSIM_HBP_MODE (1 << 21)
82 #define DSIM_HFP_MODE (1 << 22)
83 #define DSIM_HSE_MODE (1 << 23)
84 #define DSIM_AUTO_MODE (1 << 24)
85 #define DSIM_VIDEO_MODE (1 << 25)
86 #define DSIM_BURST_MODE (1 << 26)
87 #define DSIM_SYNC_INFORM (1 << 27)
88 #define DSIM_EOT_DISABLE (1 << 28)
89 #define DSIM_MFLUSH_VS (1 << 29)
90 /* This flag is valid only for exynos3250/3472/5260/5430 */
91 #define DSIM_CLKLANE_STOP (1 << 30)
92
93 /* DSIM_ESCMODE */
94 #define DSIM_TX_TRIGGER_RST (1 << 4)
95 #define DSIM_TX_LPDT_LP (1 << 6)
96 #define DSIM_CMD_LPDT_LP (1 << 7)
97 #define DSIM_FORCE_BTA (1 << 16)
98 #define DSIM_FORCE_STOP_STATE (1 << 20)
99 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
100 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
101
102 /* DSIM_MDRESOL */
103 #define DSIM_MAIN_STAND_BY (1 << 31)
104 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
105 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
106
107 /* DSIM_MVPORCH */
108 #define DSIM_CMD_ALLOW(x) ((x) << 28)
109 #define DSIM_STABLE_VFP(x) ((x) << 16)
110 #define DSIM_MAIN_VBP(x) ((x) << 0)
111 #define DSIM_CMD_ALLOW_MASK (0xf << 28)
112 #define DSIM_STABLE_VFP_MASK (0x7ff << 16)
113 #define DSIM_MAIN_VBP_MASK (0x7ff << 0)
114
115 /* DSIM_MHPORCH */
116 #define DSIM_MAIN_HFP(x) ((x) << 16)
117 #define DSIM_MAIN_HBP(x) ((x) << 0)
118 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
119 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
120
121 /* DSIM_MSYNC */
122 #define DSIM_MAIN_VSA(x) ((x) << 22)
123 #define DSIM_MAIN_HSA(x) ((x) << 0)
124 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
125 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
126
127 /* DSIM_SDRESOL */
128 #define DSIM_SUB_STANDY(x) ((x) << 31)
129 #define DSIM_SUB_VRESOL(x) ((x) << 16)
130 #define DSIM_SUB_HRESOL(x) ((x) << 0)
131 #define DSIM_SUB_STANDY_MASK ((0x1) << 31)
132 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
133 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
134
135 /* DSIM_INTSRC */
136 #define DSIM_INT_PLL_STABLE (1 << 31)
137 #define DSIM_INT_SW_RST_RELEASE (1 << 30)
138 #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29)
139 #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28)
140 #define DSIM_INT_BTA (1 << 25)
141 #define DSIM_INT_FRAME_DONE (1 << 24)
142 #define DSIM_INT_RX_TIMEOUT (1 << 21)
143 #define DSIM_INT_BTA_TIMEOUT (1 << 20)
144 #define DSIM_INT_RX_DONE (1 << 18)
145 #define DSIM_INT_RX_TE (1 << 17)
146 #define DSIM_INT_RX_ACK (1 << 16)
147 #define DSIM_INT_RX_ECC_ERR (1 << 15)
148 #define DSIM_INT_RX_CRC_ERR (1 << 14)
149
150 /* DSIM_FIFOCTRL */
151 #define DSIM_RX_DATA_FULL (1 << 25)
152 #define DSIM_RX_DATA_EMPTY (1 << 24)
153 #define DSIM_SFR_HEADER_FULL (1 << 23)
154 #define DSIM_SFR_HEADER_EMPTY (1 << 22)
155 #define DSIM_SFR_PAYLOAD_FULL (1 << 21)
156 #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20)
157 #define DSIM_I80_HEADER_FULL (1 << 19)
158 #define DSIM_I80_HEADER_EMPTY (1 << 18)
159 #define DSIM_I80_PAYLOAD_FULL (1 << 17)
160 #define DSIM_I80_PAYLOAD_EMPTY (1 << 16)
161 #define DSIM_SD_HEADER_FULL (1 << 15)
162 #define DSIM_SD_HEADER_EMPTY (1 << 14)
163 #define DSIM_SD_PAYLOAD_FULL (1 << 13)
164 #define DSIM_SD_PAYLOAD_EMPTY (1 << 12)
165 #define DSIM_MD_HEADER_FULL (1 << 11)
166 #define DSIM_MD_HEADER_EMPTY (1 << 10)
167 #define DSIM_MD_PAYLOAD_FULL (1 << 9)
168 #define DSIM_MD_PAYLOAD_EMPTY (1 << 8)
169 #define DSIM_RX_FIFO (1 << 4)
170 #define DSIM_SFR_FIFO (1 << 3)
171 #define DSIM_I80_FIFO (1 << 2)
172 #define DSIM_SD_FIFO (1 << 1)
173 #define DSIM_MD_FIFO (1 << 0)
174
175 /* DSIM_PHYACCHR */
176 #define DSIM_AFC_EN (1 << 14)
177 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
178
179 /* DSIM_PLLCTRL */
180 #define DSIM_FREQ_BAND(x) ((x) << 24)
181 #define DSIM_PLL_EN (1 << 23)
182 #define DSIM_PLL_P(x) ((x) << 13)
183 #define DSIM_PLL_M(x) ((x) << 4)
184 #define DSIM_PLL_S(x) ((x) << 1)
185
186 /* DSIM_PHYCTRL */
187 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
188 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30)
189 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14)
190
191 /* DSIM_PHYTIMING */
192 #define DSIM_PHYTIMING_LPX(x) ((x) << 8)
193 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
194
195 /* DSIM_PHYTIMING1 */
196 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
197 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
198 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
199 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
200
201 /* DSIM_PHYTIMING2 */
202 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
203 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
204 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)
205
206 #define DSI_MAX_BUS_WIDTH 4
207 #define DSI_NUM_VIRTUAL_CHANNELS 4
208 #define DSI_TX_FIFO_SIZE 2048
209 #define DSI_RX_FIFO_SIZE 256
210 #define DSI_XFER_TIMEOUT_MS 100
211 #define DSI_RX_FIFO_EMPTY 0x30800002
212
213 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
214
215 static const char *const clk_names[5] = { "bus_clk", "sclk_mipi",
216 "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0",
217 "sclk_rgb_vclk_to_dsim0" };
218
219 enum exynos_dsi_transfer_type {
220 EXYNOS_DSI_TX,
221 EXYNOS_DSI_RX,
222 };
223
224 struct exynos_dsi_transfer {
225 struct list_head list;
226 struct completion completed;
227 int result;
228 struct mipi_dsi_packet packet;
229 u16 flags;
230 u16 tx_done;
231
232 u8 *rx_payload;
233 u16 rx_len;
234 u16 rx_done;
235 };
236
237 #define DSIM_STATE_ENABLED BIT(0)
238 #define DSIM_STATE_INITIALIZED BIT(1)
239 #define DSIM_STATE_CMD_LPM BIT(2)
240 #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3)
241
242 struct exynos_dsi_driver_data {
243 const unsigned int *reg_ofs;
244 unsigned int plltmr_reg;
245 unsigned int has_freqband:1;
246 unsigned int has_clklane_stop:1;
247 unsigned int num_clks;
248 unsigned int max_freq;
249 unsigned int wait_for_reset;
250 unsigned int num_bits_resol;
251 const unsigned int *reg_values;
252 };
253
254 struct exynos_dsi {
255 struct drm_encoder encoder;
256 struct mipi_dsi_host dsi_host;
257 struct drm_connector connector;
258 struct drm_panel *panel;
259 struct list_head bridge_chain;
260 struct drm_bridge *out_bridge;
261 struct device *dev;
262
263 void __iomem *reg_base;
264 struct phy *phy;
265 struct clk **clks;
266 struct regulator_bulk_data supplies[2];
267 int irq;
268 int te_gpio;
269
270 u32 pll_clk_rate;
271 u32 burst_clk_rate;
272 u32 esc_clk_rate;
273 u32 lanes;
274 u32 mode_flags;
275 u32 format;
276
277 int state;
278 struct drm_property *brightness;
279 struct completion completed;
280
281 spinlock_t transfer_lock; /* protects transfer_list */
282 struct list_head transfer_list;
283
284 const struct exynos_dsi_driver_data *driver_data;
285 struct device_node *in_bridge_node;
286 };
287
288 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
289 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
290
encoder_to_dsi(struct drm_encoder * e)291 static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e)
292 {
293 return container_of(e, struct exynos_dsi, encoder);
294 }
295
296 enum reg_idx {
297 DSIM_STATUS_REG, /* Status register */
298 DSIM_SWRST_REG, /* Software reset register */
299 DSIM_CLKCTRL_REG, /* Clock control register */
300 DSIM_TIMEOUT_REG, /* Time out register */
301 DSIM_CONFIG_REG, /* Configuration register */
302 DSIM_ESCMODE_REG, /* Escape mode register */
303 DSIM_MDRESOL_REG,
304 DSIM_MVPORCH_REG, /* Main display Vporch register */
305 DSIM_MHPORCH_REG, /* Main display Hporch register */
306 DSIM_MSYNC_REG, /* Main display sync area register */
307 DSIM_INTSRC_REG, /* Interrupt source register */
308 DSIM_INTMSK_REG, /* Interrupt mask register */
309 DSIM_PKTHDR_REG, /* Packet Header FIFO register */
310 DSIM_PAYLOAD_REG, /* Payload FIFO register */
311 DSIM_RXFIFO_REG, /* Read FIFO register */
312 DSIM_FIFOCTRL_REG, /* FIFO status and control register */
313 DSIM_PLLCTRL_REG, /* PLL control register */
314 DSIM_PHYCTRL_REG,
315 DSIM_PHYTIMING_REG,
316 DSIM_PHYTIMING1_REG,
317 DSIM_PHYTIMING2_REG,
318 NUM_REGS
319 };
320
exynos_dsi_write(struct exynos_dsi * dsi,enum reg_idx idx,u32 val)321 static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx,
322 u32 val)
323 {
324
325 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
326 }
327
exynos_dsi_read(struct exynos_dsi * dsi,enum reg_idx idx)328 static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx)
329 {
330 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
331 }
332
333 static const unsigned int exynos_reg_ofs[] = {
334 [DSIM_STATUS_REG] = 0x00,
335 [DSIM_SWRST_REG] = 0x04,
336 [DSIM_CLKCTRL_REG] = 0x08,
337 [DSIM_TIMEOUT_REG] = 0x0c,
338 [DSIM_CONFIG_REG] = 0x10,
339 [DSIM_ESCMODE_REG] = 0x14,
340 [DSIM_MDRESOL_REG] = 0x18,
341 [DSIM_MVPORCH_REG] = 0x1c,
342 [DSIM_MHPORCH_REG] = 0x20,
343 [DSIM_MSYNC_REG] = 0x24,
344 [DSIM_INTSRC_REG] = 0x2c,
345 [DSIM_INTMSK_REG] = 0x30,
346 [DSIM_PKTHDR_REG] = 0x34,
347 [DSIM_PAYLOAD_REG] = 0x38,
348 [DSIM_RXFIFO_REG] = 0x3c,
349 [DSIM_FIFOCTRL_REG] = 0x44,
350 [DSIM_PLLCTRL_REG] = 0x4c,
351 [DSIM_PHYCTRL_REG] = 0x5c,
352 [DSIM_PHYTIMING_REG] = 0x64,
353 [DSIM_PHYTIMING1_REG] = 0x68,
354 [DSIM_PHYTIMING2_REG] = 0x6c,
355 };
356
357 static const unsigned int exynos5433_reg_ofs[] = {
358 [DSIM_STATUS_REG] = 0x04,
359 [DSIM_SWRST_REG] = 0x0C,
360 [DSIM_CLKCTRL_REG] = 0x10,
361 [DSIM_TIMEOUT_REG] = 0x14,
362 [DSIM_CONFIG_REG] = 0x18,
363 [DSIM_ESCMODE_REG] = 0x1C,
364 [DSIM_MDRESOL_REG] = 0x20,
365 [DSIM_MVPORCH_REG] = 0x24,
366 [DSIM_MHPORCH_REG] = 0x28,
367 [DSIM_MSYNC_REG] = 0x2C,
368 [DSIM_INTSRC_REG] = 0x34,
369 [DSIM_INTMSK_REG] = 0x38,
370 [DSIM_PKTHDR_REG] = 0x3C,
371 [DSIM_PAYLOAD_REG] = 0x40,
372 [DSIM_RXFIFO_REG] = 0x44,
373 [DSIM_FIFOCTRL_REG] = 0x4C,
374 [DSIM_PLLCTRL_REG] = 0x94,
375 [DSIM_PHYCTRL_REG] = 0xA4,
376 [DSIM_PHYTIMING_REG] = 0xB4,
377 [DSIM_PHYTIMING1_REG] = 0xB8,
378 [DSIM_PHYTIMING2_REG] = 0xBC,
379 };
380
381 enum reg_value_idx {
382 RESET_TYPE,
383 PLL_TIMER,
384 STOP_STATE_CNT,
385 PHYCTRL_ULPS_EXIT,
386 PHYCTRL_VREG_LP,
387 PHYCTRL_SLEW_UP,
388 PHYTIMING_LPX,
389 PHYTIMING_HS_EXIT,
390 PHYTIMING_CLK_PREPARE,
391 PHYTIMING_CLK_ZERO,
392 PHYTIMING_CLK_POST,
393 PHYTIMING_CLK_TRAIL,
394 PHYTIMING_HS_PREPARE,
395 PHYTIMING_HS_ZERO,
396 PHYTIMING_HS_TRAIL
397 };
398
399 static const unsigned int reg_values[] = {
400 [RESET_TYPE] = DSIM_SWRST,
401 [PLL_TIMER] = 500,
402 [STOP_STATE_CNT] = 0xf,
403 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
404 [PHYCTRL_VREG_LP] = 0,
405 [PHYCTRL_SLEW_UP] = 0,
406 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
407 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
408 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
409 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
410 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
411 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
412 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
413 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
414 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
415 };
416
417 static const unsigned int exynos5422_reg_values[] = {
418 [RESET_TYPE] = DSIM_SWRST,
419 [PLL_TIMER] = 500,
420 [STOP_STATE_CNT] = 0xf,
421 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
422 [PHYCTRL_VREG_LP] = 0,
423 [PHYCTRL_SLEW_UP] = 0,
424 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
425 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
426 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
427 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
428 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
429 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
430 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
431 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
432 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
433 };
434
435 static const unsigned int exynos5433_reg_values[] = {
436 [RESET_TYPE] = DSIM_FUNCRST,
437 [PLL_TIMER] = 22200,
438 [STOP_STATE_CNT] = 0xa,
439 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
440 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
441 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
442 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
443 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
444 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
445 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
446 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
447 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
448 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
449 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
450 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
451 };
452
453 static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
454 .reg_ofs = exynos_reg_ofs,
455 .plltmr_reg = 0x50,
456 .has_freqband = 1,
457 .has_clklane_stop = 1,
458 .num_clks = 2,
459 .max_freq = 1000,
460 .wait_for_reset = 1,
461 .num_bits_resol = 11,
462 .reg_values = reg_values,
463 };
464
465 static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
466 .reg_ofs = exynos_reg_ofs,
467 .plltmr_reg = 0x50,
468 .has_freqband = 1,
469 .has_clklane_stop = 1,
470 .num_clks = 2,
471 .max_freq = 1000,
472 .wait_for_reset = 1,
473 .num_bits_resol = 11,
474 .reg_values = reg_values,
475 };
476
477 static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
478 .reg_ofs = exynos_reg_ofs,
479 .plltmr_reg = 0x58,
480 .num_clks = 2,
481 .max_freq = 1000,
482 .wait_for_reset = 1,
483 .num_bits_resol = 11,
484 .reg_values = reg_values,
485 };
486
487 static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
488 .reg_ofs = exynos5433_reg_ofs,
489 .plltmr_reg = 0xa0,
490 .has_clklane_stop = 1,
491 .num_clks = 5,
492 .max_freq = 1500,
493 .wait_for_reset = 0,
494 .num_bits_resol = 12,
495 .reg_values = exynos5433_reg_values,
496 };
497
498 static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = {
499 .reg_ofs = exynos5433_reg_ofs,
500 .plltmr_reg = 0xa0,
501 .has_clklane_stop = 1,
502 .num_clks = 2,
503 .max_freq = 1500,
504 .wait_for_reset = 1,
505 .num_bits_resol = 12,
506 .reg_values = exynos5422_reg_values,
507 };
508
509 static const struct of_device_id exynos_dsi_of_match[] = {
510 { .compatible = "samsung,exynos3250-mipi-dsi",
511 .data = &exynos3_dsi_driver_data },
512 { .compatible = "samsung,exynos4210-mipi-dsi",
513 .data = &exynos4_dsi_driver_data },
514 { .compatible = "samsung,exynos5410-mipi-dsi",
515 .data = &exynos5_dsi_driver_data },
516 { .compatible = "samsung,exynos5422-mipi-dsi",
517 .data = &exynos5422_dsi_driver_data },
518 { .compatible = "samsung,exynos5433-mipi-dsi",
519 .data = &exynos5433_dsi_driver_data },
520 { }
521 };
522
exynos_dsi_wait_for_reset(struct exynos_dsi * dsi)523 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
524 {
525 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
526 return;
527
528 dev_err(dsi->dev, "timeout waiting for reset\n");
529 }
530
exynos_dsi_reset(struct exynos_dsi * dsi)531 static void exynos_dsi_reset(struct exynos_dsi *dsi)
532 {
533 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
534
535 reinit_completion(&dsi->completed);
536 exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val);
537 }
538
539 #ifndef MHZ
540 #define MHZ (1000*1000)
541 #endif
542
exynos_dsi_pll_find_pms(struct exynos_dsi * dsi,unsigned long fin,unsigned long fout,u8 * p,u16 * m,u8 * s)543 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
544 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
545 {
546 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
547 unsigned long best_freq = 0;
548 u32 min_delta = 0xffffffff;
549 u8 p_min, p_max;
550 u8 _p, best_p;
551 u16 _m, best_m;
552 u8 _s, best_s;
553
554 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
555 p_max = fin / (6 * MHZ);
556
557 for (_p = p_min; _p <= p_max; ++_p) {
558 for (_s = 0; _s <= 5; ++_s) {
559 u64 tmp;
560 u32 delta;
561
562 tmp = (u64)fout * (_p << _s);
563 do_div(tmp, fin);
564 _m = tmp;
565 if (_m < 41 || _m > 125)
566 continue;
567
568 tmp = (u64)_m * fin;
569 do_div(tmp, _p);
570 if (tmp < 500 * MHZ ||
571 tmp > driver_data->max_freq * MHZ)
572 continue;
573
574 tmp = (u64)_m * fin;
575 do_div(tmp, _p << _s);
576
577 delta = abs(fout - tmp);
578 if (delta < min_delta) {
579 best_p = _p;
580 best_m = _m;
581 best_s = _s;
582 min_delta = delta;
583 best_freq = tmp;
584 }
585 }
586 }
587
588 if (best_freq) {
589 *p = best_p;
590 *m = best_m;
591 *s = best_s;
592 }
593
594 return best_freq;
595 }
596
exynos_dsi_set_pll(struct exynos_dsi * dsi,unsigned long freq)597 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
598 unsigned long freq)
599 {
600 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
601 unsigned long fin, fout;
602 int timeout;
603 u8 p, s;
604 u16 m;
605 u32 reg;
606
607 fin = dsi->pll_clk_rate;
608 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
609 if (!fout) {
610 dev_err(dsi->dev,
611 "failed to find PLL PMS for requested frequency\n");
612 return 0;
613 }
614 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
615
616 writel(driver_data->reg_values[PLL_TIMER],
617 dsi->reg_base + driver_data->plltmr_reg);
618
619 reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
620
621 if (driver_data->has_freqband) {
622 static const unsigned long freq_bands[] = {
623 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
624 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
625 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
626 770 * MHZ, 870 * MHZ, 950 * MHZ,
627 };
628 int band;
629
630 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
631 if (fout < freq_bands[band])
632 break;
633
634 dev_dbg(dsi->dev, "band %d\n", band);
635
636 reg |= DSIM_FREQ_BAND(band);
637 }
638
639 exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
640
641 timeout = 1000;
642 do {
643 if (timeout-- == 0) {
644 dev_err(dsi->dev, "PLL failed to stabilize\n");
645 return 0;
646 }
647 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
648 } while ((reg & DSIM_PLL_STABLE) == 0);
649
650 return fout;
651 }
652
exynos_dsi_enable_clock(struct exynos_dsi * dsi)653 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
654 {
655 unsigned long hs_clk, byte_clk, esc_clk;
656 unsigned long esc_div;
657 u32 reg;
658
659 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
660 if (!hs_clk) {
661 dev_err(dsi->dev, "failed to configure DSI PLL\n");
662 return -EFAULT;
663 }
664
665 byte_clk = hs_clk / 8;
666 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
667 esc_clk = byte_clk / esc_div;
668
669 if (esc_clk > 20 * MHZ) {
670 ++esc_div;
671 esc_clk = byte_clk / esc_div;
672 }
673
674 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
675 hs_clk, byte_clk, esc_clk);
676
677 reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
678 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
679 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
680 | DSIM_BYTE_CLK_SRC_MASK);
681 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
682 | DSIM_ESC_PRESCALER(esc_div)
683 | DSIM_LANE_ESC_CLK_EN_CLK
684 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
685 | DSIM_BYTE_CLK_SRC(0)
686 | DSIM_TX_REQUEST_HSCLK;
687 exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
688
689 return 0;
690 }
691
exynos_dsi_set_phy_ctrl(struct exynos_dsi * dsi)692 static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
693 {
694 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
695 const unsigned int *reg_values = driver_data->reg_values;
696 u32 reg;
697
698 if (driver_data->has_freqband)
699 return;
700
701 /* B D-PHY: D-PHY Master & Slave Analog Block control */
702 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
703 reg_values[PHYCTRL_SLEW_UP];
704 exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg);
705
706 /*
707 * T LPX: Transmitted length of any Low-Power state period
708 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
709 * burst
710 */
711 reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
712 exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg);
713
714 /*
715 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
716 * Line state immediately before the HS-0 Line state starting the
717 * HS transmission
718 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
719 * transmitting the Clock.
720 * T CLK_POST: Time that the transmitter continues to send HS clock
721 * after the last associated Data Lane has transitioned to LP Mode
722 * Interval is defined as the period from the end of T HS-TRAIL to
723 * the beginning of T CLK-TRAIL
724 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
725 * the last payload clock bit of a HS transmission burst
726 */
727 reg = reg_values[PHYTIMING_CLK_PREPARE] |
728 reg_values[PHYTIMING_CLK_ZERO] |
729 reg_values[PHYTIMING_CLK_POST] |
730 reg_values[PHYTIMING_CLK_TRAIL];
731
732 exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg);
733
734 /*
735 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
736 * Line state immediately before the HS-0 Line state starting the
737 * HS transmission
738 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
739 * transmitting the Sync sequence.
740 * T HS-TRAIL: Time that the transmitter drives the flipped differential
741 * state after last payload data bit of a HS transmission burst
742 */
743 reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
744 reg_values[PHYTIMING_HS_TRAIL];
745 exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg);
746 }
747
exynos_dsi_disable_clock(struct exynos_dsi * dsi)748 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
749 {
750 u32 reg;
751
752 reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
753 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
754 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
755 exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
756
757 reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG);
758 reg &= ~DSIM_PLL_EN;
759 exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
760 }
761
exynos_dsi_enable_lane(struct exynos_dsi * dsi,u32 lane)762 static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane)
763 {
764 u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG);
765 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
766 DSIM_LANE_EN(lane));
767 exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
768 }
769
exynos_dsi_init_link(struct exynos_dsi * dsi)770 static int exynos_dsi_init_link(struct exynos_dsi *dsi)
771 {
772 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
773 int timeout;
774 u32 reg;
775 u32 lanes_mask;
776
777 /* Initialize FIFO pointers */
778 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
779 reg &= ~0x1f;
780 exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
781
782 usleep_range(9000, 11000);
783
784 reg |= 0x1f;
785 exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
786 usleep_range(9000, 11000);
787
788 /* DSI configuration */
789 reg = 0;
790
791 /*
792 * The first bit of mode_flags specifies display configuration.
793 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
794 * mode, otherwise it will support command mode.
795 */
796 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
797 reg |= DSIM_VIDEO_MODE;
798
799 /*
800 * The user manual describes that following bits are ignored in
801 * command mode.
802 */
803 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
804 reg |= DSIM_MFLUSH_VS;
805 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
806 reg |= DSIM_SYNC_INFORM;
807 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
808 reg |= DSIM_BURST_MODE;
809 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
810 reg |= DSIM_AUTO_MODE;
811 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
812 reg |= DSIM_HSE_MODE;
813 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
814 reg |= DSIM_HFP_MODE;
815 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
816 reg |= DSIM_HBP_MODE;
817 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
818 reg |= DSIM_HSA_MODE;
819 }
820
821 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
822 reg |= DSIM_EOT_DISABLE;
823
824 switch (dsi->format) {
825 case MIPI_DSI_FMT_RGB888:
826 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
827 break;
828 case MIPI_DSI_FMT_RGB666:
829 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
830 break;
831 case MIPI_DSI_FMT_RGB666_PACKED:
832 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
833 break;
834 case MIPI_DSI_FMT_RGB565:
835 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
836 break;
837 default:
838 dev_err(dsi->dev, "invalid pixel format\n");
839 return -EINVAL;
840 }
841
842 /*
843 * Use non-continuous clock mode if the periparal wants and
844 * host controller supports
845 *
846 * In non-continous clock mode, host controller will turn off
847 * the HS clock between high-speed transmissions to reduce
848 * power consumption.
849 */
850 if (driver_data->has_clklane_stop &&
851 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
852 reg |= DSIM_CLKLANE_STOP;
853 }
854 exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
855
856 lanes_mask = BIT(dsi->lanes) - 1;
857 exynos_dsi_enable_lane(dsi, lanes_mask);
858
859 /* Check clock and data lane state are stop state */
860 timeout = 100;
861 do {
862 if (timeout-- == 0) {
863 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
864 return -EFAULT;
865 }
866
867 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
868 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
869 != DSIM_STOP_STATE_DAT(lanes_mask))
870 continue;
871 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
872
873 reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
874 reg &= ~DSIM_STOP_STATE_CNT_MASK;
875 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
876 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg);
877
878 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
879 exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg);
880
881 return 0;
882 }
883
exynos_dsi_set_display_mode(struct exynos_dsi * dsi)884 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
885 {
886 struct drm_display_mode *m = &dsi->encoder.crtc->state->adjusted_mode;
887 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
888 u32 reg;
889
890 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
891 reg = DSIM_CMD_ALLOW(0xf)
892 | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
893 | DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
894 exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg);
895
896 reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
897 | DSIM_MAIN_HBP(m->htotal - m->hsync_end);
898 exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg);
899
900 reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
901 | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);
902 exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg);
903 }
904 reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
905 DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
906
907 exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
908
909 dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
910 }
911
exynos_dsi_set_display_enable(struct exynos_dsi * dsi,bool enable)912 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
913 {
914 u32 reg;
915
916 reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG);
917 if (enable)
918 reg |= DSIM_MAIN_STAND_BY;
919 else
920 reg &= ~DSIM_MAIN_STAND_BY;
921 exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
922 }
923
exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi * dsi)924 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
925 {
926 int timeout = 2000;
927
928 do {
929 u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
930
931 if (!(reg & DSIM_SFR_HEADER_FULL))
932 return 0;
933
934 if (!cond_resched())
935 usleep_range(950, 1050);
936 } while (--timeout);
937
938 return -ETIMEDOUT;
939 }
940
exynos_dsi_set_cmd_lpm(struct exynos_dsi * dsi,bool lpm)941 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
942 {
943 u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
944
945 if (lpm)
946 v |= DSIM_CMD_LPDT_LP;
947 else
948 v &= ~DSIM_CMD_LPDT_LP;
949
950 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
951 }
952
exynos_dsi_force_bta(struct exynos_dsi * dsi)953 static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
954 {
955 u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
956 v |= DSIM_FORCE_BTA;
957 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
958 }
959
exynos_dsi_send_to_fifo(struct exynos_dsi * dsi,struct exynos_dsi_transfer * xfer)960 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
961 struct exynos_dsi_transfer *xfer)
962 {
963 struct device *dev = dsi->dev;
964 struct mipi_dsi_packet *pkt = &xfer->packet;
965 const u8 *payload = pkt->payload + xfer->tx_done;
966 u16 length = pkt->payload_length - xfer->tx_done;
967 bool first = !xfer->tx_done;
968 u32 reg;
969
970 dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
971 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
972
973 if (length > DSI_TX_FIFO_SIZE)
974 length = DSI_TX_FIFO_SIZE;
975
976 xfer->tx_done += length;
977
978 /* Send payload */
979 while (length >= 4) {
980 reg = get_unaligned_le32(payload);
981 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
982 payload += 4;
983 length -= 4;
984 }
985
986 reg = 0;
987 switch (length) {
988 case 3:
989 reg |= payload[2] << 16;
990 fallthrough;
991 case 2:
992 reg |= payload[1] << 8;
993 fallthrough;
994 case 1:
995 reg |= payload[0];
996 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
997 break;
998 }
999
1000 /* Send packet header */
1001 if (!first)
1002 return;
1003
1004 reg = get_unaligned_le32(pkt->header);
1005 if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
1006 dev_err(dev, "waiting for header FIFO timed out\n");
1007 return;
1008 }
1009
1010 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
1011 dsi->state & DSIM_STATE_CMD_LPM)) {
1012 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
1013 dsi->state ^= DSIM_STATE_CMD_LPM;
1014 }
1015
1016 exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg);
1017
1018 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
1019 exynos_dsi_force_bta(dsi);
1020 }
1021
exynos_dsi_read_from_fifo(struct exynos_dsi * dsi,struct exynos_dsi_transfer * xfer)1022 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
1023 struct exynos_dsi_transfer *xfer)
1024 {
1025 u8 *payload = xfer->rx_payload + xfer->rx_done;
1026 bool first = !xfer->rx_done;
1027 struct device *dev = dsi->dev;
1028 u16 length;
1029 u32 reg;
1030
1031 if (first) {
1032 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1033
1034 switch (reg & 0x3f) {
1035 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1036 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1037 if (xfer->rx_len >= 2) {
1038 payload[1] = reg >> 16;
1039 ++xfer->rx_done;
1040 }
1041 fallthrough;
1042 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1043 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1044 payload[0] = reg >> 8;
1045 ++xfer->rx_done;
1046 xfer->rx_len = xfer->rx_done;
1047 xfer->result = 0;
1048 goto clear_fifo;
1049 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1050 dev_err(dev, "DSI Error Report: 0x%04x\n",
1051 (reg >> 8) & 0xffff);
1052 xfer->result = 0;
1053 goto clear_fifo;
1054 }
1055
1056 length = (reg >> 8) & 0xffff;
1057 if (length > xfer->rx_len) {
1058 dev_err(dev,
1059 "response too long (%u > %u bytes), stripping\n",
1060 xfer->rx_len, length);
1061 length = xfer->rx_len;
1062 } else if (length < xfer->rx_len)
1063 xfer->rx_len = length;
1064 }
1065
1066 length = xfer->rx_len - xfer->rx_done;
1067 xfer->rx_done += length;
1068
1069 /* Receive payload */
1070 while (length >= 4) {
1071 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1072 payload[0] = (reg >> 0) & 0xff;
1073 payload[1] = (reg >> 8) & 0xff;
1074 payload[2] = (reg >> 16) & 0xff;
1075 payload[3] = (reg >> 24) & 0xff;
1076 payload += 4;
1077 length -= 4;
1078 }
1079
1080 if (length) {
1081 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1082 switch (length) {
1083 case 3:
1084 payload[2] = (reg >> 16) & 0xff;
1085 fallthrough;
1086 case 2:
1087 payload[1] = (reg >> 8) & 0xff;
1088 fallthrough;
1089 case 1:
1090 payload[0] = reg & 0xff;
1091 }
1092 }
1093
1094 if (xfer->rx_done == xfer->rx_len)
1095 xfer->result = 0;
1096
1097 clear_fifo:
1098 length = DSI_RX_FIFO_SIZE / 4;
1099 do {
1100 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1101 if (reg == DSI_RX_FIFO_EMPTY)
1102 break;
1103 } while (--length);
1104 }
1105
exynos_dsi_transfer_start(struct exynos_dsi * dsi)1106 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
1107 {
1108 unsigned long flags;
1109 struct exynos_dsi_transfer *xfer;
1110 bool start = false;
1111
1112 again:
1113 spin_lock_irqsave(&dsi->transfer_lock, flags);
1114
1115 if (list_empty(&dsi->transfer_list)) {
1116 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1117 return;
1118 }
1119
1120 xfer = list_first_entry(&dsi->transfer_list,
1121 struct exynos_dsi_transfer, list);
1122
1123 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1124
1125 if (xfer->packet.payload_length &&
1126 xfer->tx_done == xfer->packet.payload_length)
1127 /* waiting for RX */
1128 return;
1129
1130 exynos_dsi_send_to_fifo(dsi, xfer);
1131
1132 if (xfer->packet.payload_length || xfer->rx_len)
1133 return;
1134
1135 xfer->result = 0;
1136 complete(&xfer->completed);
1137
1138 spin_lock_irqsave(&dsi->transfer_lock, flags);
1139
1140 list_del_init(&xfer->list);
1141 start = !list_empty(&dsi->transfer_list);
1142
1143 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1144
1145 if (start)
1146 goto again;
1147 }
1148
exynos_dsi_transfer_finish(struct exynos_dsi * dsi)1149 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
1150 {
1151 struct exynos_dsi_transfer *xfer;
1152 unsigned long flags;
1153 bool start = true;
1154
1155 spin_lock_irqsave(&dsi->transfer_lock, flags);
1156
1157 if (list_empty(&dsi->transfer_list)) {
1158 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1159 return false;
1160 }
1161
1162 xfer = list_first_entry(&dsi->transfer_list,
1163 struct exynos_dsi_transfer, list);
1164
1165 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1166
1167 dev_dbg(dsi->dev,
1168 "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
1169 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
1170 xfer->rx_done);
1171
1172 if (xfer->tx_done != xfer->packet.payload_length)
1173 return true;
1174
1175 if (xfer->rx_done != xfer->rx_len)
1176 exynos_dsi_read_from_fifo(dsi, xfer);
1177
1178 if (xfer->rx_done != xfer->rx_len)
1179 return true;
1180
1181 spin_lock_irqsave(&dsi->transfer_lock, flags);
1182
1183 list_del_init(&xfer->list);
1184 start = !list_empty(&dsi->transfer_list);
1185
1186 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1187
1188 if (!xfer->rx_len)
1189 xfer->result = 0;
1190 complete(&xfer->completed);
1191
1192 return start;
1193 }
1194
exynos_dsi_remove_transfer(struct exynos_dsi * dsi,struct exynos_dsi_transfer * xfer)1195 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
1196 struct exynos_dsi_transfer *xfer)
1197 {
1198 unsigned long flags;
1199 bool start;
1200
1201 spin_lock_irqsave(&dsi->transfer_lock, flags);
1202
1203 if (!list_empty(&dsi->transfer_list) &&
1204 xfer == list_first_entry(&dsi->transfer_list,
1205 struct exynos_dsi_transfer, list)) {
1206 list_del_init(&xfer->list);
1207 start = !list_empty(&dsi->transfer_list);
1208 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1209 if (start)
1210 exynos_dsi_transfer_start(dsi);
1211 return;
1212 }
1213
1214 list_del_init(&xfer->list);
1215
1216 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1217 }
1218
exynos_dsi_transfer(struct exynos_dsi * dsi,struct exynos_dsi_transfer * xfer)1219 static int exynos_dsi_transfer(struct exynos_dsi *dsi,
1220 struct exynos_dsi_transfer *xfer)
1221 {
1222 unsigned long flags;
1223 bool stopped;
1224
1225 xfer->tx_done = 0;
1226 xfer->rx_done = 0;
1227 xfer->result = -ETIMEDOUT;
1228 init_completion(&xfer->completed);
1229
1230 spin_lock_irqsave(&dsi->transfer_lock, flags);
1231
1232 stopped = list_empty(&dsi->transfer_list);
1233 list_add_tail(&xfer->list, &dsi->transfer_list);
1234
1235 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1236
1237 if (stopped)
1238 exynos_dsi_transfer_start(dsi);
1239
1240 wait_for_completion_timeout(&xfer->completed,
1241 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1242 if (xfer->result == -ETIMEDOUT) {
1243 struct mipi_dsi_packet *pkt = &xfer->packet;
1244 exynos_dsi_remove_transfer(dsi, xfer);
1245 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
1246 (int)pkt->payload_length, pkt->payload);
1247 return -ETIMEDOUT;
1248 }
1249
1250 /* Also covers hardware timeout condition */
1251 return xfer->result;
1252 }
1253
exynos_dsi_irq(int irq,void * dev_id)1254 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
1255 {
1256 struct exynos_dsi *dsi = dev_id;
1257 u32 status;
1258
1259 status = exynos_dsi_read(dsi, DSIM_INTSRC_REG);
1260 if (!status) {
1261 static unsigned long int j;
1262 if (printk_timed_ratelimit(&j, 500))
1263 dev_warn(dsi->dev, "spurious interrupt\n");
1264 return IRQ_HANDLED;
1265 }
1266 exynos_dsi_write(dsi, DSIM_INTSRC_REG, status);
1267
1268 if (status & DSIM_INT_SW_RST_RELEASE) {
1269 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1270 DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR |
1271 DSIM_INT_SW_RST_RELEASE);
1272 exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask);
1273 complete(&dsi->completed);
1274 return IRQ_HANDLED;
1275 }
1276
1277 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1278 DSIM_INT_PLL_STABLE)))
1279 return IRQ_HANDLED;
1280
1281 if (exynos_dsi_transfer_finish(dsi))
1282 exynos_dsi_transfer_start(dsi);
1283
1284 return IRQ_HANDLED;
1285 }
1286
exynos_dsi_te_irq_handler(int irq,void * dev_id)1287 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
1288 {
1289 struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
1290 struct drm_encoder *encoder = &dsi->encoder;
1291
1292 if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE)
1293 exynos_drm_crtc_te_handler(encoder->crtc);
1294
1295 return IRQ_HANDLED;
1296 }
1297
exynos_dsi_enable_irq(struct exynos_dsi * dsi)1298 static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
1299 {
1300 enable_irq(dsi->irq);
1301
1302 if (gpio_is_valid(dsi->te_gpio))
1303 enable_irq(gpio_to_irq(dsi->te_gpio));
1304 }
1305
exynos_dsi_disable_irq(struct exynos_dsi * dsi)1306 static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
1307 {
1308 if (gpio_is_valid(dsi->te_gpio))
1309 disable_irq(gpio_to_irq(dsi->te_gpio));
1310
1311 disable_irq(dsi->irq);
1312 }
1313
exynos_dsi_init(struct exynos_dsi * dsi)1314 static int exynos_dsi_init(struct exynos_dsi *dsi)
1315 {
1316 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1317
1318 exynos_dsi_reset(dsi);
1319 exynos_dsi_enable_irq(dsi);
1320
1321 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1322 exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1);
1323
1324 exynos_dsi_enable_clock(dsi);
1325 if (driver_data->wait_for_reset)
1326 exynos_dsi_wait_for_reset(dsi);
1327 exynos_dsi_set_phy_ctrl(dsi);
1328 exynos_dsi_init_link(dsi);
1329
1330 return 0;
1331 }
1332
exynos_dsi_register_te_irq(struct exynos_dsi * dsi,struct device * panel)1333 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi,
1334 struct device *panel)
1335 {
1336 int ret;
1337 int te_gpio_irq;
1338
1339 dsi->te_gpio = of_get_named_gpio(panel->of_node, "te-gpios", 0);
1340 if (dsi->te_gpio == -ENOENT)
1341 return 0;
1342
1343 if (!gpio_is_valid(dsi->te_gpio)) {
1344 ret = dsi->te_gpio;
1345 dev_err(dsi->dev, "cannot get te-gpios, %d\n", ret);
1346 goto out;
1347 }
1348
1349 ret = gpio_request(dsi->te_gpio, "te_gpio");
1350 if (ret) {
1351 dev_err(dsi->dev, "gpio request failed with %d\n", ret);
1352 goto out;
1353 }
1354
1355 te_gpio_irq = gpio_to_irq(dsi->te_gpio);
1356
1357 ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
1358 IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi);
1359 if (ret) {
1360 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1361 gpio_free(dsi->te_gpio);
1362 goto out;
1363 }
1364
1365 out:
1366 return ret;
1367 }
1368
exynos_dsi_unregister_te_irq(struct exynos_dsi * dsi)1369 static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
1370 {
1371 if (gpio_is_valid(dsi->te_gpio)) {
1372 free_irq(gpio_to_irq(dsi->te_gpio), dsi);
1373 gpio_free(dsi->te_gpio);
1374 dsi->te_gpio = -ENOENT;
1375 }
1376 }
1377
exynos_dsi_enable(struct drm_encoder * encoder)1378 static void exynos_dsi_enable(struct drm_encoder *encoder)
1379 {
1380 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1381 struct drm_bridge *iter;
1382 int ret;
1383
1384 if (dsi->state & DSIM_STATE_ENABLED)
1385 return;
1386
1387 pm_runtime_get_sync(dsi->dev);
1388 dsi->state |= DSIM_STATE_ENABLED;
1389
1390 if (dsi->panel) {
1391 ret = drm_panel_prepare(dsi->panel);
1392 if (ret < 0)
1393 goto err_put_sync;
1394 } else {
1395 list_for_each_entry_reverse(iter, &dsi->bridge_chain,
1396 chain_node) {
1397 if (iter->funcs->pre_enable)
1398 iter->funcs->pre_enable(iter);
1399 }
1400 }
1401
1402 exynos_dsi_set_display_mode(dsi);
1403 exynos_dsi_set_display_enable(dsi, true);
1404
1405 if (dsi->panel) {
1406 ret = drm_panel_enable(dsi->panel);
1407 if (ret < 0)
1408 goto err_display_disable;
1409 } else {
1410 list_for_each_entry(iter, &dsi->bridge_chain, chain_node) {
1411 if (iter->funcs->enable)
1412 iter->funcs->enable(iter);
1413 }
1414 }
1415
1416 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1417 return;
1418
1419 err_display_disable:
1420 exynos_dsi_set_display_enable(dsi, false);
1421 drm_panel_unprepare(dsi->panel);
1422
1423 err_put_sync:
1424 dsi->state &= ~DSIM_STATE_ENABLED;
1425 pm_runtime_put(dsi->dev);
1426 }
1427
exynos_dsi_disable(struct drm_encoder * encoder)1428 static void exynos_dsi_disable(struct drm_encoder *encoder)
1429 {
1430 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1431 struct drm_bridge *iter;
1432
1433 if (!(dsi->state & DSIM_STATE_ENABLED))
1434 return;
1435
1436 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1437
1438 drm_panel_disable(dsi->panel);
1439
1440 list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) {
1441 if (iter->funcs->disable)
1442 iter->funcs->disable(iter);
1443 }
1444
1445 exynos_dsi_set_display_enable(dsi, false);
1446 drm_panel_unprepare(dsi->panel);
1447
1448 list_for_each_entry(iter, &dsi->bridge_chain, chain_node) {
1449 if (iter->funcs->post_disable)
1450 iter->funcs->post_disable(iter);
1451 }
1452
1453 dsi->state &= ~DSIM_STATE_ENABLED;
1454 pm_runtime_put_sync(dsi->dev);
1455 }
1456
1457 static enum drm_connector_status
exynos_dsi_detect(struct drm_connector * connector,bool force)1458 exynos_dsi_detect(struct drm_connector *connector, bool force)
1459 {
1460 return connector->status;
1461 }
1462
exynos_dsi_connector_destroy(struct drm_connector * connector)1463 static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1464 {
1465 drm_connector_unregister(connector);
1466 drm_connector_cleanup(connector);
1467 connector->dev = NULL;
1468 }
1469
1470 static const struct drm_connector_funcs exynos_dsi_connector_funcs = {
1471 .detect = exynos_dsi_detect,
1472 .fill_modes = drm_helper_probe_single_connector_modes,
1473 .destroy = exynos_dsi_connector_destroy,
1474 .reset = drm_atomic_helper_connector_reset,
1475 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1476 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1477 };
1478
exynos_dsi_get_modes(struct drm_connector * connector)1479 static int exynos_dsi_get_modes(struct drm_connector *connector)
1480 {
1481 struct exynos_dsi *dsi = connector_to_dsi(connector);
1482
1483 if (dsi->panel)
1484 return drm_panel_get_modes(dsi->panel, connector);
1485
1486 return 0;
1487 }
1488
1489 static const struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1490 .get_modes = exynos_dsi_get_modes,
1491 };
1492
exynos_dsi_create_connector(struct drm_encoder * encoder)1493 static int exynos_dsi_create_connector(struct drm_encoder *encoder)
1494 {
1495 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1496 struct drm_connector *connector = &dsi->connector;
1497 struct drm_device *drm = encoder->dev;
1498 int ret;
1499
1500 connector->polled = DRM_CONNECTOR_POLL_HPD;
1501
1502 ret = drm_connector_init(drm, connector, &exynos_dsi_connector_funcs,
1503 DRM_MODE_CONNECTOR_DSI);
1504 if (ret) {
1505 DRM_DEV_ERROR(dsi->dev,
1506 "Failed to initialize connector with drm\n");
1507 return ret;
1508 }
1509
1510 connector->status = connector_status_disconnected;
1511 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1512 drm_connector_attach_encoder(connector, encoder);
1513 if (!drm->registered)
1514 return 0;
1515
1516 connector->funcs->reset(connector);
1517 drm_connector_register(connector);
1518 return 0;
1519 }
1520
1521 static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = {
1522 .enable = exynos_dsi_enable,
1523 .disable = exynos_dsi_disable,
1524 };
1525
1526 MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
1527
exynos_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1528 static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1529 struct mipi_dsi_device *device)
1530 {
1531 struct exynos_dsi *dsi = host_to_dsi(host);
1532 struct drm_encoder *encoder = &dsi->encoder;
1533 struct drm_device *drm = encoder->dev;
1534 struct drm_bridge *out_bridge;
1535
1536 out_bridge = of_drm_find_bridge(device->dev.of_node);
1537 if (out_bridge) {
1538 drm_bridge_attach(encoder, out_bridge, NULL, 0);
1539 dsi->out_bridge = out_bridge;
1540 list_splice_init(&encoder->bridge_chain, &dsi->bridge_chain);
1541 } else {
1542 int ret = exynos_dsi_create_connector(encoder);
1543
1544 if (ret) {
1545 DRM_DEV_ERROR(dsi->dev,
1546 "failed to create connector ret = %d\n",
1547 ret);
1548 drm_encoder_cleanup(encoder);
1549 return ret;
1550 }
1551
1552 dsi->panel = of_drm_find_panel(device->dev.of_node);
1553 if (IS_ERR(dsi->panel))
1554 dsi->panel = NULL;
1555 else
1556 dsi->connector.status = connector_status_connected;
1557 }
1558
1559 /*
1560 * This is a temporary solution and should be made by more generic way.
1561 *
1562 * If attached panel device is for command mode one, dsi should register
1563 * TE interrupt handler.
1564 */
1565 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1566 int ret = exynos_dsi_register_te_irq(dsi, &device->dev);
1567 if (ret)
1568 return ret;
1569 }
1570
1571 mutex_lock(&drm->mode_config.mutex);
1572
1573 dsi->lanes = device->lanes;
1574 dsi->format = device->format;
1575 dsi->mode_flags = device->mode_flags;
1576 exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode =
1577 !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO);
1578
1579 mutex_unlock(&drm->mode_config.mutex);
1580
1581 if (drm->mode_config.poll_enabled)
1582 drm_kms_helper_hotplug_event(drm);
1583
1584 return 0;
1585 }
1586
exynos_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1587 static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
1588 struct mipi_dsi_device *device)
1589 {
1590 struct exynos_dsi *dsi = host_to_dsi(host);
1591 struct drm_device *drm = dsi->encoder.dev;
1592
1593 if (dsi->panel) {
1594 mutex_lock(&drm->mode_config.mutex);
1595 exynos_dsi_disable(&dsi->encoder);
1596 dsi->panel = NULL;
1597 dsi->connector.status = connector_status_disconnected;
1598 mutex_unlock(&drm->mode_config.mutex);
1599 } else {
1600 if (dsi->out_bridge->funcs->detach)
1601 dsi->out_bridge->funcs->detach(dsi->out_bridge);
1602 dsi->out_bridge = NULL;
1603 INIT_LIST_HEAD(&dsi->bridge_chain);
1604 }
1605
1606 if (drm->mode_config.poll_enabled)
1607 drm_kms_helper_hotplug_event(drm);
1608
1609 exynos_dsi_unregister_te_irq(dsi);
1610
1611 return 0;
1612 }
1613
exynos_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1614 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
1615 const struct mipi_dsi_msg *msg)
1616 {
1617 struct exynos_dsi *dsi = host_to_dsi(host);
1618 struct exynos_dsi_transfer xfer;
1619 int ret;
1620
1621 if (!(dsi->state & DSIM_STATE_ENABLED))
1622 return -EINVAL;
1623
1624 if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1625 ret = exynos_dsi_init(dsi);
1626 if (ret)
1627 return ret;
1628 dsi->state |= DSIM_STATE_INITIALIZED;
1629 }
1630
1631 ret = mipi_dsi_create_packet(&xfer.packet, msg);
1632 if (ret < 0)
1633 return ret;
1634
1635 xfer.rx_len = msg->rx_len;
1636 xfer.rx_payload = msg->rx_buf;
1637 xfer.flags = msg->flags;
1638
1639 ret = exynos_dsi_transfer(dsi, &xfer);
1640 return (ret < 0) ? ret : xfer.rx_done;
1641 }
1642
1643 static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1644 .attach = exynos_dsi_host_attach,
1645 .detach = exynos_dsi_host_detach,
1646 .transfer = exynos_dsi_host_transfer,
1647 };
1648
exynos_dsi_of_read_u32(const struct device_node * np,const char * propname,u32 * out_value)1649 static int exynos_dsi_of_read_u32(const struct device_node *np,
1650 const char *propname, u32 *out_value)
1651 {
1652 int ret = of_property_read_u32(np, propname, out_value);
1653
1654 if (ret < 0)
1655 pr_err("%pOF: failed to get '%s' property\n", np, propname);
1656
1657 return ret;
1658 }
1659
1660 enum {
1661 DSI_PORT_IN,
1662 DSI_PORT_OUT
1663 };
1664
exynos_dsi_parse_dt(struct exynos_dsi * dsi)1665 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1666 {
1667 struct device *dev = dsi->dev;
1668 struct device_node *node = dev->of_node;
1669 int ret;
1670
1671 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1672 &dsi->pll_clk_rate);
1673 if (ret < 0)
1674 return ret;
1675
1676 ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency",
1677 &dsi->burst_clk_rate);
1678 if (ret < 0)
1679 return ret;
1680
1681 ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency",
1682 &dsi->esc_clk_rate);
1683 if (ret < 0)
1684 return ret;
1685
1686 dsi->in_bridge_node = of_graph_get_remote_node(node, DSI_PORT_IN, 0);
1687
1688 return 0;
1689 }
1690
exynos_dsi_bind(struct device * dev,struct device * master,void * data)1691 static int exynos_dsi_bind(struct device *dev, struct device *master,
1692 void *data)
1693 {
1694 struct drm_encoder *encoder = dev_get_drvdata(dev);
1695 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1696 struct drm_device *drm_dev = data;
1697 struct drm_bridge *in_bridge;
1698 int ret;
1699
1700 drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_TMDS);
1701
1702 drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs);
1703
1704 ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD);
1705 if (ret < 0)
1706 return ret;
1707
1708 if (dsi->in_bridge_node) {
1709 in_bridge = of_drm_find_bridge(dsi->in_bridge_node);
1710 if (in_bridge)
1711 drm_bridge_attach(encoder, in_bridge, NULL, 0);
1712 }
1713
1714 return mipi_dsi_host_register(&dsi->dsi_host);
1715 }
1716
exynos_dsi_unbind(struct device * dev,struct device * master,void * data)1717 static void exynos_dsi_unbind(struct device *dev, struct device *master,
1718 void *data)
1719 {
1720 struct drm_encoder *encoder = dev_get_drvdata(dev);
1721 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1722
1723 exynos_dsi_disable(encoder);
1724
1725 mipi_dsi_host_unregister(&dsi->dsi_host);
1726 }
1727
1728 static const struct component_ops exynos_dsi_component_ops = {
1729 .bind = exynos_dsi_bind,
1730 .unbind = exynos_dsi_unbind,
1731 };
1732
exynos_dsi_probe(struct platform_device * pdev)1733 static int exynos_dsi_probe(struct platform_device *pdev)
1734 {
1735 struct device *dev = &pdev->dev;
1736 struct resource *res;
1737 struct exynos_dsi *dsi;
1738 int ret, i;
1739
1740 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1741 if (!dsi)
1742 return -ENOMEM;
1743
1744 /* To be checked as invalid one */
1745 dsi->te_gpio = -ENOENT;
1746
1747 init_completion(&dsi->completed);
1748 spin_lock_init(&dsi->transfer_lock);
1749 INIT_LIST_HEAD(&dsi->transfer_list);
1750 INIT_LIST_HEAD(&dsi->bridge_chain);
1751
1752 dsi->dsi_host.ops = &exynos_dsi_ops;
1753 dsi->dsi_host.dev = dev;
1754
1755 dsi->dev = dev;
1756 dsi->driver_data = of_device_get_match_data(dev);
1757
1758 dsi->supplies[0].supply = "vddcore";
1759 dsi->supplies[1].supply = "vddio";
1760 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1761 dsi->supplies);
1762 if (ret)
1763 return dev_err_probe(dev, ret, "failed to get regulators\n");
1764
1765 dsi->clks = devm_kcalloc(dev,
1766 dsi->driver_data->num_clks, sizeof(*dsi->clks),
1767 GFP_KERNEL);
1768 if (!dsi->clks)
1769 return -ENOMEM;
1770
1771 for (i = 0; i < dsi->driver_data->num_clks; i++) {
1772 dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1773 if (IS_ERR(dsi->clks[i])) {
1774 if (strcmp(clk_names[i], "sclk_mipi") == 0) {
1775 dsi->clks[i] = devm_clk_get(dev,
1776 OLD_SCLK_MIPI_CLK_NAME);
1777 if (!IS_ERR(dsi->clks[i]))
1778 continue;
1779 }
1780
1781 dev_info(dev, "failed to get the clock: %s\n",
1782 clk_names[i]);
1783 return PTR_ERR(dsi->clks[i]);
1784 }
1785 }
1786
1787 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1788 dsi->reg_base = devm_ioremap_resource(dev, res);
1789 if (IS_ERR(dsi->reg_base)) {
1790 dev_err(dev, "failed to remap io region\n");
1791 return PTR_ERR(dsi->reg_base);
1792 }
1793
1794 dsi->phy = devm_phy_get(dev, "dsim");
1795 if (IS_ERR(dsi->phy)) {
1796 dev_info(dev, "failed to get dsim phy\n");
1797 return PTR_ERR(dsi->phy);
1798 }
1799
1800 dsi->irq = platform_get_irq(pdev, 0);
1801 if (dsi->irq < 0)
1802 return dsi->irq;
1803
1804 ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1805 exynos_dsi_irq,
1806 IRQF_ONESHOT | IRQF_NO_AUTOEN,
1807 dev_name(dev), dsi);
1808 if (ret) {
1809 dev_err(dev, "failed to request dsi irq\n");
1810 return ret;
1811 }
1812
1813 ret = exynos_dsi_parse_dt(dsi);
1814 if (ret)
1815 return ret;
1816
1817 platform_set_drvdata(pdev, &dsi->encoder);
1818
1819 pm_runtime_enable(dev);
1820
1821 ret = component_add(dev, &exynos_dsi_component_ops);
1822 if (ret)
1823 goto err_disable_runtime;
1824
1825 return 0;
1826
1827 err_disable_runtime:
1828 pm_runtime_disable(dev);
1829 of_node_put(dsi->in_bridge_node);
1830
1831 return ret;
1832 }
1833
exynos_dsi_remove(struct platform_device * pdev)1834 static int exynos_dsi_remove(struct platform_device *pdev)
1835 {
1836 struct exynos_dsi *dsi = platform_get_drvdata(pdev);
1837
1838 of_node_put(dsi->in_bridge_node);
1839
1840 pm_runtime_disable(&pdev->dev);
1841
1842 component_del(&pdev->dev, &exynos_dsi_component_ops);
1843
1844 return 0;
1845 }
1846
exynos_dsi_suspend(struct device * dev)1847 static int __maybe_unused exynos_dsi_suspend(struct device *dev)
1848 {
1849 struct drm_encoder *encoder = dev_get_drvdata(dev);
1850 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1851 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1852 int ret, i;
1853
1854 usleep_range(10000, 20000);
1855
1856 if (dsi->state & DSIM_STATE_INITIALIZED) {
1857 dsi->state &= ~DSIM_STATE_INITIALIZED;
1858
1859 exynos_dsi_disable_clock(dsi);
1860
1861 exynos_dsi_disable_irq(dsi);
1862 }
1863
1864 dsi->state &= ~DSIM_STATE_CMD_LPM;
1865
1866 phy_power_off(dsi->phy);
1867
1868 for (i = driver_data->num_clks - 1; i > -1; i--)
1869 clk_disable_unprepare(dsi->clks[i]);
1870
1871 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1872 if (ret < 0)
1873 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1874
1875 return 0;
1876 }
1877
exynos_dsi_resume(struct device * dev)1878 static int __maybe_unused exynos_dsi_resume(struct device *dev)
1879 {
1880 struct drm_encoder *encoder = dev_get_drvdata(dev);
1881 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1882 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1883 int ret, i;
1884
1885 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1886 if (ret < 0) {
1887 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1888 return ret;
1889 }
1890
1891 for (i = 0; i < driver_data->num_clks; i++) {
1892 ret = clk_prepare_enable(dsi->clks[i]);
1893 if (ret < 0)
1894 goto err_clk;
1895 }
1896
1897 ret = phy_power_on(dsi->phy);
1898 if (ret < 0) {
1899 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1900 goto err_clk;
1901 }
1902
1903 return 0;
1904
1905 err_clk:
1906 while (--i > -1)
1907 clk_disable_unprepare(dsi->clks[i]);
1908 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1909
1910 return ret;
1911 }
1912
1913 static const struct dev_pm_ops exynos_dsi_pm_ops = {
1914 SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL)
1915 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1916 pm_runtime_force_resume)
1917 };
1918
1919 struct platform_driver dsi_driver = {
1920 .probe = exynos_dsi_probe,
1921 .remove = exynos_dsi_remove,
1922 .driver = {
1923 .name = "exynos-dsi",
1924 .owner = THIS_MODULE,
1925 .pm = &exynos_dsi_pm_ops,
1926 .of_match_table = exynos_dsi_of_match,
1927 },
1928 };
1929
1930 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1931 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1932 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1933 MODULE_LICENSE("GPL v2");
1934