1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <linux/console.h>
26 #include <linux/delay.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/vga_switcheroo.h>
31 #include <linux/mmu_notifier.h>
32
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_ioctl.h>
35 #include <drm/drm_vblank.h>
36
37 #include <core/gpuobj.h>
38 #include <core/option.h>
39 #include <core/pci.h>
40 #include <core/tegra.h>
41
42 #include <nvif/driver.h>
43 #include <nvif/fifo.h>
44 #include <nvif/push006c.h>
45 #include <nvif/user.h>
46
47 #include <nvif/class.h>
48 #include <nvif/cl0002.h>
49 #include <nvif/cla06f.h>
50
51 #include "nouveau_drv.h"
52 #include "nouveau_dma.h"
53 #include "nouveau_ttm.h"
54 #include "nouveau_gem.h"
55 #include "nouveau_vga.h"
56 #include "nouveau_led.h"
57 #include "nouveau_hwmon.h"
58 #include "nouveau_acpi.h"
59 #include "nouveau_bios.h"
60 #include "nouveau_ioctl.h"
61 #include "nouveau_abi16.h"
62 #include "nouveau_fbcon.h"
63 #include "nouveau_fence.h"
64 #include "nouveau_debugfs.h"
65 #include "nouveau_usif.h"
66 #include "nouveau_connector.h"
67 #include "nouveau_platform.h"
68 #include "nouveau_svm.h"
69 #include "nouveau_dmem.h"
70
71 MODULE_PARM_DESC(config, "option string to pass to driver core");
72 static char *nouveau_config;
73 module_param_named(config, nouveau_config, charp, 0400);
74
75 MODULE_PARM_DESC(debug, "debug string to pass to driver core");
76 static char *nouveau_debug;
77 module_param_named(debug, nouveau_debug, charp, 0400);
78
79 MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
80 static int nouveau_noaccel = 0;
81 module_param_named(noaccel, nouveau_noaccel, int, 0400);
82
83 MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
84 "0 = disabled, 1 = enabled, 2 = headless)");
85 int nouveau_modeset = -1;
86 module_param_named(modeset, nouveau_modeset, int, 0400);
87
88 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
89 static int nouveau_atomic = 0;
90 module_param_named(atomic, nouveau_atomic, int, 0400);
91
92 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
93 static int nouveau_runtime_pm = -1;
94 module_param_named(runpm, nouveau_runtime_pm, int, 0400);
95
96 static struct drm_driver driver_stub;
97 static struct drm_driver driver_pci;
98 static struct drm_driver driver_platform;
99
100 static u64
nouveau_pci_name(struct pci_dev * pdev)101 nouveau_pci_name(struct pci_dev *pdev)
102 {
103 u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
104 name |= pdev->bus->number << 16;
105 name |= PCI_SLOT(pdev->devfn) << 8;
106 return name | PCI_FUNC(pdev->devfn);
107 }
108
109 static u64
nouveau_platform_name(struct platform_device * platformdev)110 nouveau_platform_name(struct platform_device *platformdev)
111 {
112 return platformdev->id;
113 }
114
115 static u64
nouveau_name(struct drm_device * dev)116 nouveau_name(struct drm_device *dev)
117 {
118 if (dev->pdev)
119 return nouveau_pci_name(dev->pdev);
120 else
121 return nouveau_platform_name(to_platform_device(dev->dev));
122 }
123
124 static inline bool
nouveau_cli_work_ready(struct dma_fence * fence)125 nouveau_cli_work_ready(struct dma_fence *fence)
126 {
127 bool ret = true;
128
129 spin_lock_irq(fence->lock);
130 if (!dma_fence_is_signaled_locked(fence))
131 ret = false;
132 spin_unlock_irq(fence->lock);
133
134 if (ret == true)
135 dma_fence_put(fence);
136 return ret;
137 }
138
139 static void
nouveau_cli_work(struct work_struct * w)140 nouveau_cli_work(struct work_struct *w)
141 {
142 struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
143 struct nouveau_cli_work *work, *wtmp;
144 mutex_lock(&cli->lock);
145 list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
146 if (!work->fence || nouveau_cli_work_ready(work->fence)) {
147 list_del(&work->head);
148 work->func(work);
149 }
150 }
151 mutex_unlock(&cli->lock);
152 }
153
154 static void
nouveau_cli_work_fence(struct dma_fence * fence,struct dma_fence_cb * cb)155 nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
156 {
157 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
158 schedule_work(&work->cli->work);
159 }
160
161 void
nouveau_cli_work_queue(struct nouveau_cli * cli,struct dma_fence * fence,struct nouveau_cli_work * work)162 nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
163 struct nouveau_cli_work *work)
164 {
165 work->fence = dma_fence_get(fence);
166 work->cli = cli;
167 mutex_lock(&cli->lock);
168 list_add_tail(&work->head, &cli->worker);
169 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
170 nouveau_cli_work_fence(fence, &work->cb);
171 mutex_unlock(&cli->lock);
172 }
173
174 static void
nouveau_cli_fini(struct nouveau_cli * cli)175 nouveau_cli_fini(struct nouveau_cli *cli)
176 {
177 /* All our channels are dead now, which means all the fences they
178 * own are signalled, and all callback functions have been called.
179 *
180 * So, after flushing the workqueue, there should be nothing left.
181 */
182 flush_work(&cli->work);
183 WARN_ON(!list_empty(&cli->worker));
184
185 usif_client_fini(cli);
186 nouveau_vmm_fini(&cli->svm);
187 nouveau_vmm_fini(&cli->vmm);
188 nvif_mmu_dtor(&cli->mmu);
189 nvif_device_dtor(&cli->device);
190 mutex_lock(&cli->drm->master.lock);
191 nvif_client_dtor(&cli->base);
192 mutex_unlock(&cli->drm->master.lock);
193 }
194
195 static int
nouveau_cli_init(struct nouveau_drm * drm,const char * sname,struct nouveau_cli * cli)196 nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
197 struct nouveau_cli *cli)
198 {
199 static const struct nvif_mclass
200 mems[] = {
201 { NVIF_CLASS_MEM_GF100, -1 },
202 { NVIF_CLASS_MEM_NV50 , -1 },
203 { NVIF_CLASS_MEM_NV04 , -1 },
204 {}
205 };
206 static const struct nvif_mclass
207 mmus[] = {
208 { NVIF_CLASS_MMU_GF100, -1 },
209 { NVIF_CLASS_MMU_NV50 , -1 },
210 { NVIF_CLASS_MMU_NV04 , -1 },
211 {}
212 };
213 static const struct nvif_mclass
214 vmms[] = {
215 { NVIF_CLASS_VMM_GP100, -1 },
216 { NVIF_CLASS_VMM_GM200, -1 },
217 { NVIF_CLASS_VMM_GF100, -1 },
218 { NVIF_CLASS_VMM_NV50 , -1 },
219 { NVIF_CLASS_VMM_NV04 , -1 },
220 {}
221 };
222 u64 device = nouveau_name(drm->dev);
223 int ret;
224
225 snprintf(cli->name, sizeof(cli->name), "%s", sname);
226 cli->drm = drm;
227 mutex_init(&cli->mutex);
228 usif_client_init(cli);
229
230 INIT_WORK(&cli->work, nouveau_cli_work);
231 INIT_LIST_HEAD(&cli->worker);
232 mutex_init(&cli->lock);
233
234 if (cli == &drm->master) {
235 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug,
236 cli->name, device, &cli->base);
237 } else {
238 mutex_lock(&drm->master.lock);
239 ret = nvif_client_ctor(&drm->master.base, cli->name, device,
240 &cli->base);
241 mutex_unlock(&drm->master.lock);
242 }
243 if (ret) {
244 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret);
245 goto done;
246 }
247
248 ret = nvif_device_ctor(&cli->base.object, "drmDevice", 0, NV_DEVICE,
249 &(struct nv_device_v0) {
250 .device = ~0,
251 }, sizeof(struct nv_device_v0),
252 &cli->device);
253 if (ret) {
254 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret);
255 goto done;
256 }
257
258 ret = nvif_mclass(&cli->device.object, mmus);
259 if (ret < 0) {
260 NV_PRINTK(err, cli, "No supported MMU class\n");
261 goto done;
262 }
263
264 ret = nvif_mmu_ctor(&cli->device.object, "drmMmu", mmus[ret].oclass,
265 &cli->mmu);
266 if (ret) {
267 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret);
268 goto done;
269 }
270
271 ret = nvif_mclass(&cli->mmu.object, vmms);
272 if (ret < 0) {
273 NV_PRINTK(err, cli, "No supported VMM class\n");
274 goto done;
275 }
276
277 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
278 if (ret) {
279 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret);
280 goto done;
281 }
282
283 ret = nvif_mclass(&cli->mmu.object, mems);
284 if (ret < 0) {
285 NV_PRINTK(err, cli, "No supported MEM class\n");
286 goto done;
287 }
288
289 cli->mem = &mems[ret];
290 return 0;
291 done:
292 if (ret)
293 nouveau_cli_fini(cli);
294 return ret;
295 }
296
297 static void
nouveau_accel_ce_fini(struct nouveau_drm * drm)298 nouveau_accel_ce_fini(struct nouveau_drm *drm)
299 {
300 nouveau_channel_idle(drm->cechan);
301 nvif_object_dtor(&drm->ttm.copy);
302 nouveau_channel_del(&drm->cechan);
303 }
304
305 static void
nouveau_accel_ce_init(struct nouveau_drm * drm)306 nouveau_accel_ce_init(struct nouveau_drm *drm)
307 {
308 struct nvif_device *device = &drm->client.device;
309 int ret = 0;
310
311 /* Allocate channel that has access to a (preferably async) copy
312 * engine, to use for TTM buffer moves.
313 */
314 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
315 ret = nouveau_channel_new(drm, device,
316 nvif_fifo_runlist_ce(device), 0,
317 true, &drm->cechan);
318 } else
319 if (device->info.chipset >= 0xa3 &&
320 device->info.chipset != 0xaa &&
321 device->info.chipset != 0xac) {
322 /* Prior to Kepler, there's only a single runlist, so all
323 * engines can be accessed from any channel.
324 *
325 * We still want to use a separate channel though.
326 */
327 ret = nouveau_channel_new(drm, device, NvDmaFB, NvDmaTT, false,
328 &drm->cechan);
329 }
330
331 if (ret)
332 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
333 }
334
335 static void
nouveau_accel_gr_fini(struct nouveau_drm * drm)336 nouveau_accel_gr_fini(struct nouveau_drm *drm)
337 {
338 nouveau_channel_idle(drm->channel);
339 nvif_object_dtor(&drm->ntfy);
340 nvkm_gpuobj_del(&drm->notify);
341 nouveau_channel_del(&drm->channel);
342 }
343
344 static void
nouveau_accel_gr_init(struct nouveau_drm * drm)345 nouveau_accel_gr_init(struct nouveau_drm *drm)
346 {
347 struct nvif_device *device = &drm->client.device;
348 u32 arg0, arg1;
349 int ret;
350
351 /* Allocate channel that has access to the graphics engine. */
352 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
353 arg0 = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_GR);
354 arg1 = 1;
355 } else {
356 arg0 = NvDmaFB;
357 arg1 = NvDmaTT;
358 }
359
360 ret = nouveau_channel_new(drm, device, arg0, arg1, false,
361 &drm->channel);
362 if (ret) {
363 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
364 nouveau_accel_gr_fini(drm);
365 return;
366 }
367
368 /* A SW class is used on pre-NV50 HW to assist with handling the
369 * synchronisation of page flips, as well as to implement fences
370 * on TNT/TNT2 HW that lacks any kind of support in host.
371 */
372 if (!drm->channel->nvsw.client && device->info.family < NV_DEVICE_INFO_V0_TESLA) {
373 ret = nvif_object_ctor(&drm->channel->user, "drmNvsw",
374 NVDRM_NVSW, nouveau_abi16_swclass(drm),
375 NULL, 0, &drm->channel->nvsw);
376 if (ret == 0) {
377 struct nvif_push *push = drm->channel->chan.push;
378 ret = PUSH_WAIT(push, 2);
379 if (ret == 0)
380 PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);
381 }
382
383 if (ret) {
384 NV_ERROR(drm, "failed to allocate sw class, %d\n", ret);
385 nouveau_accel_gr_fini(drm);
386 return;
387 }
388 }
389
390 /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason,
391 * even if notification is never requested, so, allocate a ctxdma on
392 * any GPU where it's possible we'll end up using M2MF for BO moves.
393 */
394 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
395 ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL,
396 &drm->notify);
397 if (ret) {
398 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
399 nouveau_accel_gr_fini(drm);
400 return;
401 }
402
403 ret = nvif_object_ctor(&drm->channel->user, "drmM2mfNtfy",
404 NvNotify0, NV_DMA_IN_MEMORY,
405 &(struct nv_dma_v0) {
406 .target = NV_DMA_V0_TARGET_VRAM,
407 .access = NV_DMA_V0_ACCESS_RDWR,
408 .start = drm->notify->addr,
409 .limit = drm->notify->addr + 31
410 }, sizeof(struct nv_dma_v0),
411 &drm->ntfy);
412 if (ret) {
413 nouveau_accel_gr_fini(drm);
414 return;
415 }
416 }
417 }
418
419 static void
nouveau_accel_fini(struct nouveau_drm * drm)420 nouveau_accel_fini(struct nouveau_drm *drm)
421 {
422 nouveau_accel_ce_fini(drm);
423 nouveau_accel_gr_fini(drm);
424 if (drm->fence)
425 nouveau_fence(drm)->dtor(drm);
426 }
427
428 static void
nouveau_accel_init(struct nouveau_drm * drm)429 nouveau_accel_init(struct nouveau_drm *drm)
430 {
431 struct nvif_device *device = &drm->client.device;
432 struct nvif_sclass *sclass;
433 int ret, i, n;
434
435 if (nouveau_noaccel)
436 return;
437
438 /* Initialise global support for channels, and synchronisation. */
439 ret = nouveau_channels_init(drm);
440 if (ret)
441 return;
442
443 /*XXX: this is crap, but the fence/channel stuff is a little
444 * backwards in some places. this will be fixed.
445 */
446 ret = n = nvif_object_sclass_get(&device->object, &sclass);
447 if (ret < 0)
448 return;
449
450 for (ret = -ENOSYS, i = 0; i < n; i++) {
451 switch (sclass[i].oclass) {
452 case NV03_CHANNEL_DMA:
453 ret = nv04_fence_create(drm);
454 break;
455 case NV10_CHANNEL_DMA:
456 ret = nv10_fence_create(drm);
457 break;
458 case NV17_CHANNEL_DMA:
459 case NV40_CHANNEL_DMA:
460 ret = nv17_fence_create(drm);
461 break;
462 case NV50_CHANNEL_GPFIFO:
463 ret = nv50_fence_create(drm);
464 break;
465 case G82_CHANNEL_GPFIFO:
466 ret = nv84_fence_create(drm);
467 break;
468 case FERMI_CHANNEL_GPFIFO:
469 case KEPLER_CHANNEL_GPFIFO_A:
470 case KEPLER_CHANNEL_GPFIFO_B:
471 case MAXWELL_CHANNEL_GPFIFO_A:
472 case PASCAL_CHANNEL_GPFIFO_A:
473 case VOLTA_CHANNEL_GPFIFO_A:
474 case TURING_CHANNEL_GPFIFO_A:
475 ret = nvc0_fence_create(drm);
476 break;
477 default:
478 break;
479 }
480 }
481
482 nvif_object_sclass_put(&sclass);
483 if (ret) {
484 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
485 nouveau_accel_fini(drm);
486 return;
487 }
488
489 /* Volta requires access to a doorbell register for kickoff. */
490 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
491 ret = nvif_user_ctor(device, "drmUsermode");
492 if (ret)
493 return;
494 }
495
496 /* Allocate channels we need to support various functions. */
497 nouveau_accel_gr_init(drm);
498 nouveau_accel_ce_init(drm);
499
500 /* Initialise accelerated TTM buffer moves. */
501 nouveau_bo_move_init(drm);
502 }
503
504 static void __printf(2, 3)
nouveau_drm_errorf(struct nvif_object * object,const char * fmt,...)505 nouveau_drm_errorf(struct nvif_object *object, const char *fmt, ...)
506 {
507 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
508 struct va_format vaf;
509 va_list va;
510
511 va_start(va, fmt);
512 vaf.fmt = fmt;
513 vaf.va = &va;
514 NV_ERROR(drm, "%pV", &vaf);
515 va_end(va);
516 }
517
518 static void __printf(2, 3)
nouveau_drm_debugf(struct nvif_object * object,const char * fmt,...)519 nouveau_drm_debugf(struct nvif_object *object, const char *fmt, ...)
520 {
521 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
522 struct va_format vaf;
523 va_list va;
524
525 va_start(va, fmt);
526 vaf.fmt = fmt;
527 vaf.va = &va;
528 NV_DEBUG(drm, "%pV", &vaf);
529 va_end(va);
530 }
531
532 static const struct nvif_parent_func
533 nouveau_parent = {
534 .debugf = nouveau_drm_debugf,
535 .errorf = nouveau_drm_errorf,
536 };
537
538 static int
nouveau_drm_device_init(struct drm_device * dev)539 nouveau_drm_device_init(struct drm_device *dev)
540 {
541 struct nouveau_drm *drm;
542 int ret;
543
544 if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL)))
545 return -ENOMEM;
546 dev->dev_private = drm;
547 drm->dev = dev;
548
549 nvif_parent_ctor(&nouveau_parent, &drm->parent);
550 drm->master.base.object.parent = &drm->parent;
551
552 ret = nouveau_cli_init(drm, "DRM-master", &drm->master);
553 if (ret)
554 goto fail_alloc;
555
556 ret = nouveau_cli_init(drm, "DRM", &drm->client);
557 if (ret)
558 goto fail_master;
559
560 dev->irq_enabled = true;
561
562 nvxx_client(&drm->client.base)->debug =
563 nvkm_dbgopt(nouveau_debug, "DRM");
564
565 INIT_LIST_HEAD(&drm->clients);
566 mutex_init(&drm->clients_lock);
567 spin_lock_init(&drm->tile.lock);
568
569 /* workaround an odd issue on nvc1 by disabling the device's
570 * nosnoop capability. hopefully won't cause issues until a
571 * better fix is found - assuming there is one...
572 */
573 if (drm->client.device.info.chipset == 0xc1)
574 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
575
576 nouveau_vga_init(drm);
577
578 ret = nouveau_ttm_init(drm);
579 if (ret)
580 goto fail_ttm;
581
582 ret = nouveau_bios_init(dev);
583 if (ret)
584 goto fail_bios;
585
586 nouveau_accel_init(drm);
587
588 ret = nouveau_display_create(dev);
589 if (ret)
590 goto fail_dispctor;
591
592 if (dev->mode_config.num_crtc) {
593 ret = nouveau_display_init(dev, false, false);
594 if (ret)
595 goto fail_dispinit;
596 }
597
598 nouveau_debugfs_init(drm);
599 nouveau_hwmon_init(dev);
600 nouveau_svm_init(drm);
601 nouveau_dmem_init(drm);
602 nouveau_fbcon_init(dev);
603 nouveau_led_init(dev);
604
605 if (nouveau_pmops_runtime()) {
606 pm_runtime_use_autosuspend(dev->dev);
607 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
608 pm_runtime_set_active(dev->dev);
609 pm_runtime_allow(dev->dev);
610 pm_runtime_mark_last_busy(dev->dev);
611 pm_runtime_put(dev->dev);
612 }
613
614 return 0;
615
616 fail_dispinit:
617 nouveau_display_destroy(dev);
618 fail_dispctor:
619 nouveau_accel_fini(drm);
620 nouveau_bios_takedown(dev);
621 fail_bios:
622 nouveau_ttm_fini(drm);
623 fail_ttm:
624 nouveau_vga_fini(drm);
625 nouveau_cli_fini(&drm->client);
626 fail_master:
627 nouveau_cli_fini(&drm->master);
628 fail_alloc:
629 nvif_parent_dtor(&drm->parent);
630 kfree(drm);
631 return ret;
632 }
633
634 static void
nouveau_drm_device_fini(struct drm_device * dev)635 nouveau_drm_device_fini(struct drm_device *dev)
636 {
637 struct nouveau_cli *cli, *temp_cli;
638 struct nouveau_drm *drm = nouveau_drm(dev);
639
640 if (nouveau_pmops_runtime()) {
641 pm_runtime_get_sync(dev->dev);
642 pm_runtime_forbid(dev->dev);
643 }
644
645 nouveau_led_fini(dev);
646 nouveau_fbcon_fini(dev);
647 nouveau_dmem_fini(drm);
648 nouveau_svm_fini(drm);
649 nouveau_hwmon_fini(dev);
650 nouveau_debugfs_fini(drm);
651
652 if (dev->mode_config.num_crtc)
653 nouveau_display_fini(dev, false, false);
654 nouveau_display_destroy(dev);
655
656 nouveau_accel_fini(drm);
657 nouveau_bios_takedown(dev);
658
659 nouveau_ttm_fini(drm);
660 nouveau_vga_fini(drm);
661
662 /*
663 * There may be existing clients from as-yet unclosed files. For now,
664 * clean them up here rather than deferring until the file is closed,
665 * but this likely not correct if we want to support hot-unplugging
666 * properly.
667 */
668 mutex_lock(&drm->clients_lock);
669 list_for_each_entry_safe(cli, temp_cli, &drm->clients, head) {
670 list_del(&cli->head);
671 mutex_lock(&cli->mutex);
672 if (cli->abi16)
673 nouveau_abi16_fini(cli->abi16);
674 mutex_unlock(&cli->mutex);
675 nouveau_cli_fini(cli);
676 kfree(cli);
677 }
678 mutex_unlock(&drm->clients_lock);
679
680 nouveau_cli_fini(&drm->client);
681 nouveau_cli_fini(&drm->master);
682 nvif_parent_dtor(&drm->parent);
683 mutex_destroy(&drm->clients_lock);
684 kfree(drm);
685 }
686
687 /*
688 * On some Intel PCIe bridge controllers doing a
689 * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear.
690 * Skipping the intermediate D3hot step seems to make it work again. This is
691 * probably caused by not meeting the expectation the involved AML code has
692 * when the GPU is put into D3hot state before invoking it.
693 *
694 * This leads to various manifestations of this issue:
695 * - AML code execution to power on the GPU hits an infinite loop (as the
696 * code waits on device memory to change).
697 * - kernel crashes, as all PCI reads return -1, which most code isn't able
698 * to handle well enough.
699 *
700 * In all cases dmesg will contain at least one line like this:
701 * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3'
702 * followed by a lot of nouveau timeouts.
703 *
704 * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not
705 * documented PCI config space register 0x248 of the Intel PCIe bridge
706 * controller (0x1901) in order to change the state of the PCIe link between
707 * the PCIe port and the GPU. There are alternative code paths using other
708 * registers, which seem to work fine (executed pre Windows 8):
709 * - 0xbc bit 0x20 (publicly available documentation claims 'reserved')
710 * - 0xb0 bit 0x10 (link disable)
711 * Changing the conditions inside the firmware by poking into the relevant
712 * addresses does resolve the issue, but it seemed to be ACPI private memory
713 * and not any device accessible memory at all, so there is no portable way of
714 * changing the conditions.
715 * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared.
716 *
717 * The only systems where this behavior can be seen are hybrid graphics laptops
718 * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether
719 * this issue only occurs in combination with listed Intel PCIe bridge
720 * controllers and the mentioned GPUs or other devices as well.
721 *
722 * documentation on the PCIe bridge controller can be found in the
723 * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2"
724 * Section "12 PCI Express* Controller (x16) Registers"
725 */
726
quirk_broken_nv_runpm(struct pci_dev * pdev)727 static void quirk_broken_nv_runpm(struct pci_dev *pdev)
728 {
729 struct drm_device *dev = pci_get_drvdata(pdev);
730 struct nouveau_drm *drm = nouveau_drm(dev);
731 struct pci_dev *bridge = pci_upstream_bridge(pdev);
732
733 if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL)
734 return;
735
736 switch (bridge->device) {
737 case 0x1901:
738 drm->old_pm_cap = pdev->pm_cap;
739 pdev->pm_cap = 0;
740 NV_INFO(drm, "Disabling PCI power management to avoid bug\n");
741 break;
742 }
743 }
744
nouveau_drm_probe(struct pci_dev * pdev,const struct pci_device_id * pent)745 static int nouveau_drm_probe(struct pci_dev *pdev,
746 const struct pci_device_id *pent)
747 {
748 struct nvkm_device *device;
749 struct drm_device *drm_dev;
750 int ret;
751
752 if (vga_switcheroo_client_probe_defer(pdev))
753 return -EPROBE_DEFER;
754
755 /* We need to check that the chipset is supported before booting
756 * fbdev off the hardware, as there's no way to put it back.
757 */
758 ret = nvkm_device_pci_new(pdev, nouveau_config, "error",
759 true, false, 0, &device);
760 if (ret)
761 return ret;
762
763 nvkm_device_del(&device);
764
765 /* Remove conflicting drivers (vesafb, efifb etc). */
766 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "nouveaufb");
767 if (ret)
768 return ret;
769
770 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
771 true, true, ~0ULL, &device);
772 if (ret)
773 return ret;
774
775 pci_set_master(pdev);
776
777 if (nouveau_atomic)
778 driver_pci.driver_features |= DRIVER_ATOMIC;
779
780 drm_dev = drm_dev_alloc(&driver_pci, &pdev->dev);
781 if (IS_ERR(drm_dev)) {
782 ret = PTR_ERR(drm_dev);
783 goto fail_nvkm;
784 }
785
786 ret = pci_enable_device(pdev);
787 if (ret)
788 goto fail_drm;
789
790 drm_dev->pdev = pdev;
791 pci_set_drvdata(pdev, drm_dev);
792
793 ret = nouveau_drm_device_init(drm_dev);
794 if (ret)
795 goto fail_pci;
796
797 ret = drm_dev_register(drm_dev, pent->driver_data);
798 if (ret)
799 goto fail_drm_dev_init;
800
801 quirk_broken_nv_runpm(pdev);
802 return 0;
803
804 fail_drm_dev_init:
805 nouveau_drm_device_fini(drm_dev);
806 fail_pci:
807 pci_disable_device(pdev);
808 fail_drm:
809 drm_dev_put(drm_dev);
810 fail_nvkm:
811 nvkm_device_del(&device);
812 return ret;
813 }
814
815 void
nouveau_drm_device_remove(struct drm_device * dev)816 nouveau_drm_device_remove(struct drm_device *dev)
817 {
818 struct nouveau_drm *drm = nouveau_drm(dev);
819 struct nvkm_client *client;
820 struct nvkm_device *device;
821
822 drm_dev_unplug(dev);
823
824 dev->irq_enabled = false;
825 client = nvxx_client(&drm->client.base);
826 device = nvkm_device_find(client->device);
827
828 nouveau_drm_device_fini(dev);
829 drm_dev_put(dev);
830 nvkm_device_del(&device);
831 }
832
833 static void
nouveau_drm_remove(struct pci_dev * pdev)834 nouveau_drm_remove(struct pci_dev *pdev)
835 {
836 struct drm_device *dev = pci_get_drvdata(pdev);
837 struct nouveau_drm *drm = nouveau_drm(dev);
838
839 /* revert our workaround */
840 if (drm->old_pm_cap)
841 pdev->pm_cap = drm->old_pm_cap;
842 nouveau_drm_device_remove(dev);
843 pci_disable_device(pdev);
844 }
845
846 static int
nouveau_do_suspend(struct drm_device * dev,bool runtime)847 nouveau_do_suspend(struct drm_device *dev, bool runtime)
848 {
849 struct nouveau_drm *drm = nouveau_drm(dev);
850 int ret;
851
852 nouveau_svm_suspend(drm);
853 nouveau_dmem_suspend(drm);
854 nouveau_led_suspend(dev);
855
856 if (dev->mode_config.num_crtc) {
857 NV_DEBUG(drm, "suspending console...\n");
858 nouveau_fbcon_set_suspend(dev, 1);
859 NV_DEBUG(drm, "suspending display...\n");
860 ret = nouveau_display_suspend(dev, runtime);
861 if (ret)
862 return ret;
863 }
864
865 NV_DEBUG(drm, "evicting buffers...\n");
866 ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
867
868 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
869 if (drm->cechan) {
870 ret = nouveau_channel_idle(drm->cechan);
871 if (ret)
872 goto fail_display;
873 }
874
875 if (drm->channel) {
876 ret = nouveau_channel_idle(drm->channel);
877 if (ret)
878 goto fail_display;
879 }
880
881 NV_DEBUG(drm, "suspending fence...\n");
882 if (drm->fence && nouveau_fence(drm)->suspend) {
883 if (!nouveau_fence(drm)->suspend(drm)) {
884 ret = -ENOMEM;
885 goto fail_display;
886 }
887 }
888
889 NV_DEBUG(drm, "suspending object tree...\n");
890 ret = nvif_client_suspend(&drm->master.base);
891 if (ret)
892 goto fail_client;
893
894 return 0;
895
896 fail_client:
897 if (drm->fence && nouveau_fence(drm)->resume)
898 nouveau_fence(drm)->resume(drm);
899
900 fail_display:
901 if (dev->mode_config.num_crtc) {
902 NV_DEBUG(drm, "resuming display...\n");
903 nouveau_display_resume(dev, runtime);
904 }
905 return ret;
906 }
907
908 static int
nouveau_do_resume(struct drm_device * dev,bool runtime)909 nouveau_do_resume(struct drm_device *dev, bool runtime)
910 {
911 int ret = 0;
912 struct nouveau_drm *drm = nouveau_drm(dev);
913
914 NV_DEBUG(drm, "resuming object tree...\n");
915 ret = nvif_client_resume(&drm->master.base);
916 if (ret) {
917 NV_ERROR(drm, "Client resume failed with error: %d\n", ret);
918 return ret;
919 }
920
921 NV_DEBUG(drm, "resuming fence...\n");
922 if (drm->fence && nouveau_fence(drm)->resume)
923 nouveau_fence(drm)->resume(drm);
924
925 nouveau_run_vbios_init(dev);
926
927 if (dev->mode_config.num_crtc) {
928 NV_DEBUG(drm, "resuming display...\n");
929 nouveau_display_resume(dev, runtime);
930 NV_DEBUG(drm, "resuming console...\n");
931 nouveau_fbcon_set_suspend(dev, 0);
932 }
933
934 nouveau_led_resume(dev);
935 nouveau_dmem_resume(drm);
936 nouveau_svm_resume(drm);
937 return 0;
938 }
939
940 int
nouveau_pmops_suspend(struct device * dev)941 nouveau_pmops_suspend(struct device *dev)
942 {
943 struct pci_dev *pdev = to_pci_dev(dev);
944 struct drm_device *drm_dev = pci_get_drvdata(pdev);
945 int ret;
946
947 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
948 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
949 return 0;
950
951 ret = nouveau_do_suspend(drm_dev, false);
952 if (ret)
953 return ret;
954
955 pci_save_state(pdev);
956 pci_disable_device(pdev);
957 pci_set_power_state(pdev, PCI_D3hot);
958 udelay(200);
959 return 0;
960 }
961
962 int
nouveau_pmops_resume(struct device * dev)963 nouveau_pmops_resume(struct device *dev)
964 {
965 struct pci_dev *pdev = to_pci_dev(dev);
966 struct drm_device *drm_dev = pci_get_drvdata(pdev);
967 int ret;
968
969 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
970 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
971 return 0;
972
973 pci_set_power_state(pdev, PCI_D0);
974 pci_restore_state(pdev);
975 ret = pci_enable_device(pdev);
976 if (ret)
977 return ret;
978 pci_set_master(pdev);
979
980 ret = nouveau_do_resume(drm_dev, false);
981
982 /* Monitors may have been connected / disconnected during suspend */
983 nouveau_display_hpd_resume(drm_dev);
984
985 return ret;
986 }
987
988 static int
nouveau_pmops_freeze(struct device * dev)989 nouveau_pmops_freeze(struct device *dev)
990 {
991 struct pci_dev *pdev = to_pci_dev(dev);
992 struct drm_device *drm_dev = pci_get_drvdata(pdev);
993 return nouveau_do_suspend(drm_dev, false);
994 }
995
996 static int
nouveau_pmops_thaw(struct device * dev)997 nouveau_pmops_thaw(struct device *dev)
998 {
999 struct pci_dev *pdev = to_pci_dev(dev);
1000 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1001 return nouveau_do_resume(drm_dev, false);
1002 }
1003
1004 bool
nouveau_pmops_runtime(void)1005 nouveau_pmops_runtime(void)
1006 {
1007 if (nouveau_runtime_pm == -1)
1008 return nouveau_is_optimus() || nouveau_is_v1_dsm();
1009 return nouveau_runtime_pm == 1;
1010 }
1011
1012 static int
nouveau_pmops_runtime_suspend(struct device * dev)1013 nouveau_pmops_runtime_suspend(struct device *dev)
1014 {
1015 struct pci_dev *pdev = to_pci_dev(dev);
1016 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1017 int ret;
1018
1019 if (!nouveau_pmops_runtime()) {
1020 pm_runtime_forbid(dev);
1021 return -EBUSY;
1022 }
1023
1024 nouveau_switcheroo_optimus_dsm();
1025 ret = nouveau_do_suspend(drm_dev, true);
1026 pci_save_state(pdev);
1027 pci_disable_device(pdev);
1028 pci_ignore_hotplug(pdev);
1029 pci_set_power_state(pdev, PCI_D3cold);
1030 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1031 return ret;
1032 }
1033
1034 static int
nouveau_pmops_runtime_resume(struct device * dev)1035 nouveau_pmops_runtime_resume(struct device *dev)
1036 {
1037 struct pci_dev *pdev = to_pci_dev(dev);
1038 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1039 struct nouveau_drm *drm = nouveau_drm(drm_dev);
1040 struct nvif_device *device = &nouveau_drm(drm_dev)->client.device;
1041 int ret;
1042
1043 if (!nouveau_pmops_runtime()) {
1044 pm_runtime_forbid(dev);
1045 return -EBUSY;
1046 }
1047
1048 pci_set_power_state(pdev, PCI_D0);
1049 pci_restore_state(pdev);
1050 ret = pci_enable_device(pdev);
1051 if (ret)
1052 return ret;
1053 pci_set_master(pdev);
1054
1055 ret = nouveau_do_resume(drm_dev, true);
1056 if (ret) {
1057 NV_ERROR(drm, "resume failed with: %d\n", ret);
1058 return ret;
1059 }
1060
1061 /* do magic */
1062 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
1063 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1064
1065 /* Monitors may have been connected / disconnected during suspend */
1066 nouveau_display_hpd_resume(drm_dev);
1067
1068 return ret;
1069 }
1070
1071 static int
nouveau_pmops_runtime_idle(struct device * dev)1072 nouveau_pmops_runtime_idle(struct device *dev)
1073 {
1074 if (!nouveau_pmops_runtime()) {
1075 pm_runtime_forbid(dev);
1076 return -EBUSY;
1077 }
1078
1079 pm_runtime_mark_last_busy(dev);
1080 pm_runtime_autosuspend(dev);
1081 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1082 return 1;
1083 }
1084
1085 static int
nouveau_drm_open(struct drm_device * dev,struct drm_file * fpriv)1086 nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
1087 {
1088 struct nouveau_drm *drm = nouveau_drm(dev);
1089 struct nouveau_cli *cli;
1090 char name[32], tmpname[TASK_COMM_LEN];
1091 int ret;
1092
1093 /* need to bring up power immediately if opening device */
1094 ret = pm_runtime_get_sync(dev->dev);
1095 if (ret < 0 && ret != -EACCES) {
1096 pm_runtime_put_autosuspend(dev->dev);
1097 return ret;
1098 }
1099
1100 get_task_comm(tmpname, current);
1101 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
1102
1103 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) {
1104 ret = -ENOMEM;
1105 goto done;
1106 }
1107
1108 ret = nouveau_cli_init(drm, name, cli);
1109 if (ret)
1110 goto done;
1111
1112 cli->base.super = false;
1113
1114 fpriv->driver_priv = cli;
1115
1116 mutex_lock(&drm->clients_lock);
1117 list_add(&cli->head, &drm->clients);
1118 mutex_unlock(&drm->clients_lock);
1119
1120 done:
1121 if (ret && cli) {
1122 nouveau_cli_fini(cli);
1123 kfree(cli);
1124 }
1125
1126 pm_runtime_mark_last_busy(dev->dev);
1127 pm_runtime_put_autosuspend(dev->dev);
1128 return ret;
1129 }
1130
1131 static void
nouveau_drm_postclose(struct drm_device * dev,struct drm_file * fpriv)1132 nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
1133 {
1134 struct nouveau_cli *cli = nouveau_cli(fpriv);
1135 struct nouveau_drm *drm = nouveau_drm(dev);
1136 int dev_index;
1137
1138 /*
1139 * The device is gone, and as it currently stands all clients are
1140 * cleaned up in the removal codepath. In the future this may change
1141 * so that we can support hot-unplugging, but for now we immediately
1142 * return to avoid a double-free situation.
1143 */
1144 if (!drm_dev_enter(dev, &dev_index))
1145 return;
1146
1147 pm_runtime_get_sync(dev->dev);
1148
1149 mutex_lock(&cli->mutex);
1150 if (cli->abi16)
1151 nouveau_abi16_fini(cli->abi16);
1152 mutex_unlock(&cli->mutex);
1153
1154 mutex_lock(&drm->clients_lock);
1155 list_del(&cli->head);
1156 mutex_unlock(&drm->clients_lock);
1157
1158 nouveau_cli_fini(cli);
1159 kfree(cli);
1160 pm_runtime_mark_last_busy(dev->dev);
1161 pm_runtime_put_autosuspend(dev->dev);
1162 drm_dev_exit(dev_index);
1163 }
1164
1165 static const struct drm_ioctl_desc
1166 nouveau_ioctls[] = {
1167 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW),
1168 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1169 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW),
1170 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW),
1171 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW),
1172 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW),
1173 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW),
1174 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW),
1175 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW),
1176 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW),
1177 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW),
1178 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW),
1179 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW),
1180 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW),
1181 };
1182
1183 long
nouveau_drm_ioctl(struct file * file,unsigned int cmd,unsigned long arg)1184 nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1185 {
1186 struct drm_file *filp = file->private_data;
1187 struct drm_device *dev = filp->minor->dev;
1188 long ret;
1189
1190 ret = pm_runtime_get_sync(dev->dev);
1191 if (ret < 0 && ret != -EACCES) {
1192 pm_runtime_put_autosuspend(dev->dev);
1193 return ret;
1194 }
1195
1196 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
1197 case DRM_NOUVEAU_NVIF:
1198 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
1199 break;
1200 default:
1201 ret = drm_ioctl(file, cmd, arg);
1202 break;
1203 }
1204
1205 pm_runtime_mark_last_busy(dev->dev);
1206 pm_runtime_put_autosuspend(dev->dev);
1207 return ret;
1208 }
1209
1210 static const struct file_operations
1211 nouveau_driver_fops = {
1212 .owner = THIS_MODULE,
1213 .open = drm_open,
1214 .release = drm_release,
1215 .unlocked_ioctl = nouveau_drm_ioctl,
1216 .mmap = nouveau_ttm_mmap,
1217 .poll = drm_poll,
1218 .read = drm_read,
1219 #if defined(CONFIG_COMPAT)
1220 .compat_ioctl = nouveau_compat_ioctl,
1221 #endif
1222 .llseek = noop_llseek,
1223 };
1224
1225 static struct drm_driver
1226 driver_stub = {
1227 .driver_features =
1228 DRIVER_GEM | DRIVER_MODESET | DRIVER_RENDER
1229 #if defined(CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT)
1230 | DRIVER_KMS_LEGACY_CONTEXT
1231 #endif
1232 ,
1233
1234 .open = nouveau_drm_open,
1235 .postclose = nouveau_drm_postclose,
1236 .lastclose = nouveau_vga_lastclose,
1237
1238 #if defined(CONFIG_DEBUG_FS)
1239 .debugfs_init = nouveau_drm_debugfs_init,
1240 #endif
1241
1242 .ioctls = nouveau_ioctls,
1243 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
1244 .fops = &nouveau_driver_fops,
1245
1246 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1247 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1248 .gem_prime_pin = nouveau_gem_prime_pin,
1249 .gem_prime_unpin = nouveau_gem_prime_unpin,
1250 .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
1251 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
1252 .gem_prime_vmap = nouveau_gem_prime_vmap,
1253 .gem_prime_vunmap = nouveau_gem_prime_vunmap,
1254
1255 .gem_free_object_unlocked = nouveau_gem_object_del,
1256 .gem_open_object = nouveau_gem_object_open,
1257 .gem_close_object = nouveau_gem_object_close,
1258
1259 .dumb_create = nouveau_display_dumb_create,
1260 .dumb_map_offset = nouveau_display_dumb_map_offset,
1261
1262 .name = DRIVER_NAME,
1263 .desc = DRIVER_DESC,
1264 #ifdef GIT_REVISION
1265 .date = GIT_REVISION,
1266 #else
1267 .date = DRIVER_DATE,
1268 #endif
1269 .major = DRIVER_MAJOR,
1270 .minor = DRIVER_MINOR,
1271 .patchlevel = DRIVER_PATCHLEVEL,
1272 };
1273
1274 static struct pci_device_id
1275 nouveau_drm_pci_table[] = {
1276 {
1277 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1278 .class = PCI_BASE_CLASS_DISPLAY << 16,
1279 .class_mask = 0xff << 16,
1280 },
1281 {
1282 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1283 .class = PCI_BASE_CLASS_DISPLAY << 16,
1284 .class_mask = 0xff << 16,
1285 },
1286 {}
1287 };
1288
nouveau_display_options(void)1289 static void nouveau_display_options(void)
1290 {
1291 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1292
1293 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
1294 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
1295 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
1296 DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
1297 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
1298 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
1299 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
1300 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
1301 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
1302 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
1303 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
1304 }
1305
1306 static const struct dev_pm_ops nouveau_pm_ops = {
1307 .suspend = nouveau_pmops_suspend,
1308 .resume = nouveau_pmops_resume,
1309 .freeze = nouveau_pmops_freeze,
1310 .thaw = nouveau_pmops_thaw,
1311 .poweroff = nouveau_pmops_freeze,
1312 .restore = nouveau_pmops_resume,
1313 .runtime_suspend = nouveau_pmops_runtime_suspend,
1314 .runtime_resume = nouveau_pmops_runtime_resume,
1315 .runtime_idle = nouveau_pmops_runtime_idle,
1316 };
1317
1318 static struct pci_driver
1319 nouveau_drm_pci_driver = {
1320 .name = "nouveau",
1321 .id_table = nouveau_drm_pci_table,
1322 .probe = nouveau_drm_probe,
1323 .remove = nouveau_drm_remove,
1324 .driver.pm = &nouveau_pm_ops,
1325 };
1326
1327 struct drm_device *
nouveau_platform_device_create(const struct nvkm_device_tegra_func * func,struct platform_device * pdev,struct nvkm_device ** pdevice)1328 nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1329 struct platform_device *pdev,
1330 struct nvkm_device **pdevice)
1331 {
1332 struct drm_device *drm;
1333 int err;
1334
1335 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
1336 true, true, ~0ULL, pdevice);
1337 if (err)
1338 goto err_free;
1339
1340 drm = drm_dev_alloc(&driver_platform, &pdev->dev);
1341 if (IS_ERR(drm)) {
1342 err = PTR_ERR(drm);
1343 goto err_free;
1344 }
1345
1346 err = nouveau_drm_device_init(drm);
1347 if (err)
1348 goto err_put;
1349
1350 platform_set_drvdata(pdev, drm);
1351
1352 return drm;
1353
1354 err_put:
1355 drm_dev_put(drm);
1356 err_free:
1357 nvkm_device_del(pdevice);
1358
1359 return ERR_PTR(err);
1360 }
1361
1362 static int __init
nouveau_drm_init(void)1363 nouveau_drm_init(void)
1364 {
1365 driver_pci = driver_stub;
1366 driver_platform = driver_stub;
1367
1368 nouveau_display_options();
1369
1370 if (nouveau_modeset == -1) {
1371 if (vgacon_text_force())
1372 nouveau_modeset = 0;
1373 }
1374
1375 if (!nouveau_modeset)
1376 return 0;
1377
1378 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1379 platform_driver_register(&nouveau_platform_driver);
1380 #endif
1381
1382 nouveau_register_dsm_handler();
1383 nouveau_backlight_ctor();
1384
1385 #ifdef CONFIG_PCI
1386 return pci_register_driver(&nouveau_drm_pci_driver);
1387 #else
1388 return 0;
1389 #endif
1390 }
1391
1392 static void __exit
nouveau_drm_exit(void)1393 nouveau_drm_exit(void)
1394 {
1395 if (!nouveau_modeset)
1396 return;
1397
1398 #ifdef CONFIG_PCI
1399 pci_unregister_driver(&nouveau_drm_pci_driver);
1400 #endif
1401 nouveau_backlight_dtor();
1402 nouveau_unregister_dsm_handler();
1403
1404 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1405 platform_driver_unregister(&nouveau_platform_driver);
1406 #endif
1407 if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM))
1408 mmu_notifier_synchronize();
1409 }
1410
1411 module_init(nouveau_drm_init);
1412 module_exit(nouveau_drm_exit);
1413
1414 MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
1415 MODULE_AUTHOR(DRIVER_AUTHOR);
1416 MODULE_DESCRIPTION(DRIVER_DESC);
1417 MODULE_LICENSE("GPL and additional rights");
1418