1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale i.MX8MQ USB3 PHY 8 9maintainers: 10 - Li Jun <jun.li@nxp.com> 11 12properties: 13 compatible: 14 enum: 15 - fsl,imx8mq-usb-phy 16 - fsl,imx8mp-usb-phy 17 18 reg: 19 maxItems: 1 20 21 "#phy-cells": 22 const: 0 23 24 clocks: 25 maxItems: 1 26 27 clock-names: 28 items: 29 - const: phy 30 31 power-domains: 32 maxItems: 1 33 34 vbus-supply: 35 description: 36 A phandle to the regulator for USB VBUS. 37 38 fsl,phy-tx-vref-tune-percent: 39 description: 40 Tunes the HS DC level relative to the nominal level 41 minimum: 94 42 maximum: 124 43 44 fsl,phy-tx-rise-tune-percent: 45 description: 46 Adjusts the rise/fall time duration of the HS waveform relative to 47 its nominal value 48 minimum: 97 49 maximum: 103 50 51 fsl,phy-tx-preemp-amp-tune-microamp: 52 description: 53 Adjust amount of current sourced to DPn and DMn after a J-to-K 54 or K-to-J transition. Default is 0 (disabled). 55 minimum: 0 56 maximum: 1800 57 58 fsl,phy-tx-vboost-level-microvolt: 59 description: 60 Adjust the boosted transmit launch pk-pk differential amplitude 61 enum: [844, 1008, 1156] 62 63 fsl,phy-comp-dis-tune-percent: 64 description: 65 Adjust the voltage level used to detect a disconnect event at the host 66 relative to the nominal value 67 minimum: 91 68 maximum: 115 69 70 fsl,phy-pcs-tx-deemph-3p5db-attenuation-db: 71 description: 72 Adjust TX de-emphasis attenuation in dB at nominal 73 3.5dB point as per USB specification 74 $ref: /schemas/types.yaml#/definitions/uint32 75 minimum: 0 76 maximum: 36 77 78 fsl,phy-pcs-tx-swing-full-percent: 79 description: 80 Scaling of the voltage defined by fsl,phy-tx-vboost-level-microvolt 81 minimum: 0 82 maximum: 100 83 84required: 85 - compatible 86 - reg 87 - "#phy-cells" 88 - clocks 89 - clock-names 90 91additionalProperties: false 92 93examples: 94 - | 95 #include <dt-bindings/clock/imx8mq-clock.h> 96 usb3_phy0: phy@381f0040 { 97 compatible = "fsl,imx8mq-usb-phy"; 98 reg = <0x381f0040 0x40>; 99 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; 100 clock-names = "phy"; 101 #phy-cells = <0>; 102 }; 103