1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2016 ARM Ltd. 3// based on the Allwinner H3 dtsi: 4// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 6#include <dt-bindings/clock/sun50i-a64-ccu.h> 7#include <dt-bindings/clock/sun6i-rtc.h> 8#include <dt-bindings/clock/sun8i-de2.h> 9#include <dt-bindings/clock/sun8i-r-ccu.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/reset/sun50i-a64-ccu.h> 12#include <dt-bindings/reset/sun8i-de2.h> 13#include <dt-bindings/reset/sun8i-r-ccu.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 chosen { 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges; 25 26 simplefb_lcd: framebuffer-lcd { 27 compatible = "allwinner,simple-framebuffer", 28 "simple-framebuffer"; 29 allwinner,pipeline = "mixer0-lcd0"; 30 clocks = <&ccu CLK_TCON0>, 31 <&display_clocks CLK_MIXER0>; 32 status = "disabled"; 33 }; 34 35 simplefb_hdmi: framebuffer-hdmi { 36 compatible = "allwinner,simple-framebuffer", 37 "simple-framebuffer"; 38 allwinner,pipeline = "mixer1-lcd1-hdmi"; 39 clocks = <&display_clocks CLK_MIXER1>, 40 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 41 status = "disabled"; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 compatible = "arm,cortex-a53"; 51 device_type = "cpu"; 52 reg = <0>; 53 enable-method = "psci"; 54 next-level-cache = <&L2>; 55 clocks = <&ccu CLK_CPUX>; 56 clock-names = "cpu"; 57 #cooling-cells = <2>; 58 }; 59 60 cpu1: cpu@1 { 61 compatible = "arm,cortex-a53"; 62 device_type = "cpu"; 63 reg = <1>; 64 enable-method = "psci"; 65 next-level-cache = <&L2>; 66 clocks = <&ccu CLK_CPUX>; 67 clock-names = "cpu"; 68 #cooling-cells = <2>; 69 }; 70 71 cpu2: cpu@2 { 72 compatible = "arm,cortex-a53"; 73 device_type = "cpu"; 74 reg = <2>; 75 enable-method = "psci"; 76 next-level-cache = <&L2>; 77 clocks = <&ccu CLK_CPUX>; 78 clock-names = "cpu"; 79 #cooling-cells = <2>; 80 }; 81 82 cpu3: cpu@3 { 83 compatible = "arm,cortex-a53"; 84 device_type = "cpu"; 85 reg = <3>; 86 enable-method = "psci"; 87 next-level-cache = <&L2>; 88 clocks = <&ccu CLK_CPUX>; 89 clock-names = "cpu"; 90 #cooling-cells = <2>; 91 }; 92 93 L2: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 }; 98 }; 99 100 de: display-engine { 101 compatible = "allwinner,sun50i-a64-display-engine"; 102 allwinner,pipelines = <&mixer0>, 103 <&mixer1>; 104 status = "disabled"; 105 }; 106 107 gpu_opp_table: opp-table-gpu { 108 compatible = "operating-points-v2"; 109 110 opp-120000000 { 111 opp-hz = /bits/ 64 <120000000>; 112 }; 113 114 opp-312000000 { 115 opp-hz = /bits/ 64 <312000000>; 116 }; 117 118 opp-432000000 { 119 opp-hz = /bits/ 64 <432000000>; 120 }; 121 }; 122 123 osc24M: osc24M_clk { 124 #clock-cells = <0>; 125 compatible = "fixed-clock"; 126 clock-frequency = <24000000>; 127 clock-output-names = "osc24M"; 128 }; 129 130 osc32k: osc32k_clk { 131 #clock-cells = <0>; 132 compatible = "fixed-clock"; 133 clock-frequency = <32768>; 134 clock-output-names = "ext-osc32k"; 135 }; 136 137 pmu { 138 compatible = "arm,cortex-a53-pmu"; 139 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 143 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 144 }; 145 146 psci { 147 compatible = "arm,psci-0.2"; 148 method = "smc"; 149 }; 150 151 sound: sound { 152 #address-cells = <1>; 153 #size-cells = <0>; 154 compatible = "simple-audio-card"; 155 simple-audio-card,name = "sun50i-a64-audio"; 156 simple-audio-card,aux-devs = <&codec_analog>; 157 simple-audio-card,routing = 158 "Left DAC", "DACL", 159 "Right DAC", "DACR", 160 "ADCL", "Left ADC", 161 "ADCR", "Right ADC"; 162 status = "disabled"; 163 164 simple-audio-card,dai-link@0 { 165 format = "i2s"; 166 frame-master = <&link0_cpu>; 167 bitclock-master = <&link0_cpu>; 168 mclk-fs = <128>; 169 170 link0_cpu: cpu { 171 sound-dai = <&dai>; 172 }; 173 174 link0_codec: codec { 175 sound-dai = <&codec 0>; 176 }; 177 }; 178 }; 179 180 timer { 181 compatible = "arm,armv8-timer"; 182 allwinner,erratum-unknown1; 183 arm,no-tick-in-suspend; 184 interrupts = <GIC_PPI 13 185 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 186 <GIC_PPI 14 187 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 188 <GIC_PPI 11 189 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 190 <GIC_PPI 10 191 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 192 }; 193 194 thermal-zones { 195 cpu_thermal: cpu0-thermal { 196 /* milliseconds */ 197 polling-delay-passive = <0>; 198 polling-delay = <0>; 199 thermal-sensors = <&ths 0>; 200 201 cooling-maps { 202 map0 { 203 trip = <&cpu_alert0>; 204 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 205 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 206 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 207 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 208 }; 209 map1 { 210 trip = <&cpu_alert1>; 211 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 212 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 213 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 214 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 215 }; 216 }; 217 218 trips { 219 cpu_alert0: cpu_alert0 { 220 /* milliCelsius */ 221 temperature = <75000>; 222 hysteresis = <2000>; 223 type = "passive"; 224 }; 225 226 cpu_alert1: cpu_alert1 { 227 /* milliCelsius */ 228 temperature = <90000>; 229 hysteresis = <2000>; 230 type = "hot"; 231 }; 232 233 cpu_crit: cpu_crit { 234 /* milliCelsius */ 235 temperature = <110000>; 236 hysteresis = <2000>; 237 type = "critical"; 238 }; 239 }; 240 }; 241 242 gpu0_thermal: gpu0-thermal { 243 /* milliseconds */ 244 polling-delay-passive = <0>; 245 polling-delay = <0>; 246 thermal-sensors = <&ths 1>; 247 }; 248 249 gpu1_thermal: gpu1-thermal { 250 /* milliseconds */ 251 polling-delay-passive = <0>; 252 polling-delay = <0>; 253 thermal-sensors = <&ths 2>; 254 }; 255 }; 256 257 soc { 258 compatible = "simple-bus"; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 ranges; 262 263 bus@1000000 { 264 compatible = "allwinner,sun50i-a64-de2"; 265 reg = <0x1000000 0x400000>; 266 allwinner,sram = <&de2_sram 1>; 267 #address-cells = <1>; 268 #size-cells = <1>; 269 ranges = <0 0x1000000 0x400000>; 270 271 display_clocks: clock@0 { 272 compatible = "allwinner,sun50i-a64-de2-clk"; 273 reg = <0x0 0x10000>; 274 clocks = <&ccu CLK_BUS_DE>, 275 <&ccu CLK_DE>; 276 clock-names = "bus", 277 "mod"; 278 resets = <&ccu RST_BUS_DE>; 279 #clock-cells = <1>; 280 #reset-cells = <1>; 281 }; 282 283 rotate: rotate@20000 { 284 compatible = "allwinner,sun50i-a64-de2-rotate", 285 "allwinner,sun8i-a83t-de2-rotate"; 286 reg = <0x20000 0x10000>; 287 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&display_clocks CLK_BUS_ROT>, 289 <&display_clocks CLK_ROT>; 290 clock-names = "bus", 291 "mod"; 292 resets = <&display_clocks RST_ROT>; 293 }; 294 295 mixer0: mixer@100000 { 296 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 297 reg = <0x100000 0x100000>; 298 clocks = <&display_clocks CLK_BUS_MIXER0>, 299 <&display_clocks CLK_MIXER0>; 300 clock-names = "bus", 301 "mod"; 302 resets = <&display_clocks RST_MIXER0>; 303 304 ports { 305 #address-cells = <1>; 306 #size-cells = <0>; 307 308 mixer0_out: port@1 { 309 #address-cells = <1>; 310 #size-cells = <0>; 311 reg = <1>; 312 313 mixer0_out_tcon0: endpoint@0 { 314 reg = <0>; 315 remote-endpoint = <&tcon0_in_mixer0>; 316 }; 317 318 mixer0_out_tcon1: endpoint@1 { 319 reg = <1>; 320 remote-endpoint = <&tcon1_in_mixer0>; 321 }; 322 }; 323 }; 324 }; 325 326 mixer1: mixer@200000 { 327 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 328 reg = <0x200000 0x100000>; 329 clocks = <&display_clocks CLK_BUS_MIXER1>, 330 <&display_clocks CLK_MIXER1>; 331 clock-names = "bus", 332 "mod"; 333 resets = <&display_clocks RST_MIXER1>; 334 335 ports { 336 #address-cells = <1>; 337 #size-cells = <0>; 338 339 mixer1_out: port@1 { 340 #address-cells = <1>; 341 #size-cells = <0>; 342 reg = <1>; 343 344 mixer1_out_tcon0: endpoint@0 { 345 reg = <0>; 346 remote-endpoint = <&tcon0_in_mixer1>; 347 }; 348 349 mixer1_out_tcon1: endpoint@1 { 350 reg = <1>; 351 remote-endpoint = <&tcon1_in_mixer1>; 352 }; 353 }; 354 }; 355 }; 356 }; 357 358 syscon: syscon@1c00000 { 359 compatible = "allwinner,sun50i-a64-system-control"; 360 reg = <0x01c00000 0x1000>; 361 #address-cells = <1>; 362 #size-cells = <1>; 363 ranges; 364 365 sram_c: sram@18000 { 366 compatible = "mmio-sram"; 367 reg = <0x00018000 0x28000>; 368 #address-cells = <1>; 369 #size-cells = <1>; 370 ranges = <0 0x00018000 0x28000>; 371 372 de2_sram: sram-section@0 { 373 compatible = "allwinner,sun50i-a64-sram-c"; 374 reg = <0x0000 0x28000>; 375 }; 376 }; 377 378 sram_c1: sram@1d00000 { 379 compatible = "mmio-sram"; 380 reg = <0x01d00000 0x40000>; 381 #address-cells = <1>; 382 #size-cells = <1>; 383 ranges = <0 0x01d00000 0x40000>; 384 385 ve_sram: sram-section@0 { 386 compatible = "allwinner,sun50i-a64-sram-c1", 387 "allwinner,sun4i-a10-sram-c1"; 388 reg = <0x000000 0x40000>; 389 }; 390 }; 391 }; 392 393 dma: dma-controller@1c02000 { 394 compatible = "allwinner,sun50i-a64-dma"; 395 reg = <0x01c02000 0x1000>; 396 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&ccu CLK_BUS_DMA>; 398 dma-channels = <8>; 399 dma-requests = <27>; 400 resets = <&ccu RST_BUS_DMA>; 401 #dma-cells = <1>; 402 }; 403 404 tcon0: lcd-controller@1c0c000 { 405 compatible = "allwinner,sun50i-a64-tcon-lcd", 406 "allwinner,sun8i-a83t-tcon-lcd"; 407 reg = <0x01c0c000 0x1000>; 408 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 410 clock-names = "ahb", "tcon-ch0"; 411 clock-output-names = "tcon-data-clock"; 412 #clock-cells = <0>; 413 assigned-clocks = <&ccu CLK_TCON0>; 414 assigned-clock-parents = <&ccu CLK_PLL_MIPI>; 415 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 416 reset-names = "lcd", "lvds"; 417 418 ports { 419 #address-cells = <1>; 420 #size-cells = <0>; 421 422 tcon0_in: port@0 { 423 #address-cells = <1>; 424 #size-cells = <0>; 425 reg = <0>; 426 427 tcon0_in_mixer0: endpoint@0 { 428 reg = <0>; 429 remote-endpoint = <&mixer0_out_tcon0>; 430 }; 431 432 tcon0_in_mixer1: endpoint@1 { 433 reg = <1>; 434 remote-endpoint = <&mixer1_out_tcon0>; 435 }; 436 }; 437 438 tcon0_out: port@1 { 439 #address-cells = <1>; 440 #size-cells = <0>; 441 reg = <1>; 442 443 tcon0_out_dsi: endpoint@1 { 444 reg = <1>; 445 remote-endpoint = <&dsi_in_tcon0>; 446 allwinner,tcon-channel = <1>; 447 }; 448 }; 449 }; 450 }; 451 452 tcon1: lcd-controller@1c0d000 { 453 compatible = "allwinner,sun50i-a64-tcon-tv", 454 "allwinner,sun8i-a83t-tcon-tv"; 455 reg = <0x01c0d000 0x1000>; 456 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 458 clock-names = "ahb", "tcon-ch1"; 459 resets = <&ccu RST_BUS_TCON1>; 460 reset-names = "lcd"; 461 462 ports { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 466 tcon1_in: port@0 { 467 #address-cells = <1>; 468 #size-cells = <0>; 469 reg = <0>; 470 471 tcon1_in_mixer0: endpoint@0 { 472 reg = <0>; 473 remote-endpoint = <&mixer0_out_tcon1>; 474 }; 475 476 tcon1_in_mixer1: endpoint@1 { 477 reg = <1>; 478 remote-endpoint = <&mixer1_out_tcon1>; 479 }; 480 }; 481 482 tcon1_out: port@1 { 483 #address-cells = <1>; 484 #size-cells = <0>; 485 reg = <1>; 486 487 tcon1_out_hdmi: endpoint@1 { 488 reg = <1>; 489 remote-endpoint = <&hdmi_in_tcon1>; 490 }; 491 }; 492 }; 493 }; 494 495 video-codec@1c0e000 { 496 compatible = "allwinner,sun50i-a64-video-engine"; 497 reg = <0x01c0e000 0x1000>; 498 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 499 <&ccu CLK_DRAM_VE>; 500 clock-names = "ahb", "mod", "ram"; 501 resets = <&ccu RST_BUS_VE>; 502 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 503 allwinner,sram = <&ve_sram 1>; 504 }; 505 506 mmc0: mmc@1c0f000 { 507 compatible = "allwinner,sun50i-a64-mmc"; 508 reg = <0x01c0f000 0x1000>; 509 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 510 clock-names = "ahb", "mmc"; 511 resets = <&ccu RST_BUS_MMC0>; 512 reset-names = "ahb"; 513 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 514 max-frequency = <150000000>; 515 status = "disabled"; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 }; 519 520 mmc1: mmc@1c10000 { 521 compatible = "allwinner,sun50i-a64-mmc"; 522 reg = <0x01c10000 0x1000>; 523 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 524 clock-names = "ahb", "mmc"; 525 resets = <&ccu RST_BUS_MMC1>; 526 reset-names = "ahb"; 527 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 528 max-frequency = <150000000>; 529 status = "disabled"; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 }; 533 534 mmc2: mmc@1c11000 { 535 compatible = "allwinner,sun50i-a64-emmc"; 536 reg = <0x01c11000 0x1000>; 537 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 538 clock-names = "ahb", "mmc"; 539 resets = <&ccu RST_BUS_MMC2>; 540 reset-names = "ahb"; 541 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 542 max-frequency = <150000000>; 543 status = "disabled"; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 }; 547 548 sid: eeprom@1c14000 { 549 compatible = "allwinner,sun50i-a64-sid"; 550 reg = <0x1c14000 0x400>; 551 #address-cells = <1>; 552 #size-cells = <1>; 553 554 ths_calibration: thermal-sensor-calibration@34 { 555 reg = <0x34 0x8>; 556 }; 557 }; 558 559 crypto: crypto@1c15000 { 560 compatible = "allwinner,sun50i-a64-crypto"; 561 reg = <0x01c15000 0x1000>; 562 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 564 clock-names = "bus", "mod"; 565 resets = <&ccu RST_BUS_CE>; 566 }; 567 568 msgbox: mailbox@1c17000 { 569 compatible = "allwinner,sun50i-a64-msgbox", 570 "allwinner,sun6i-a31-msgbox"; 571 reg = <0x01c17000 0x1000>; 572 clocks = <&ccu CLK_BUS_MSGBOX>; 573 resets = <&ccu RST_BUS_MSGBOX>; 574 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 575 #mbox-cells = <1>; 576 }; 577 578 usb_otg: usb@1c19000 { 579 compatible = "allwinner,sun8i-a33-musb"; 580 reg = <0x01c19000 0x0400>; 581 clocks = <&ccu CLK_BUS_OTG>; 582 resets = <&ccu RST_BUS_OTG>; 583 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 584 interrupt-names = "mc"; 585 phys = <&usbphy 0>; 586 phy-names = "usb"; 587 extcon = <&usbphy 0>; 588 dr_mode = "otg"; 589 status = "disabled"; 590 }; 591 592 usbphy: phy@1c19400 { 593 compatible = "allwinner,sun50i-a64-usb-phy"; 594 reg = <0x01c19400 0x14>, 595 <0x01c1a800 0x4>, 596 <0x01c1b800 0x4>; 597 reg-names = "phy_ctrl", 598 "pmu0", 599 "pmu1"; 600 clocks = <&ccu CLK_USB_PHY0>, 601 <&ccu CLK_USB_PHY1>; 602 clock-names = "usb0_phy", 603 "usb1_phy"; 604 resets = <&ccu RST_USB_PHY0>, 605 <&ccu RST_USB_PHY1>; 606 reset-names = "usb0_reset", 607 "usb1_reset"; 608 status = "disabled"; 609 #phy-cells = <1>; 610 }; 611 612 ehci0: usb@1c1a000 { 613 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 614 reg = <0x01c1a000 0x100>; 615 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&ccu CLK_BUS_OHCI0>, 617 <&ccu CLK_BUS_EHCI0>, 618 <&ccu CLK_USB_OHCI0>; 619 resets = <&ccu RST_BUS_OHCI0>, 620 <&ccu RST_BUS_EHCI0>; 621 phys = <&usbphy 0>; 622 phy-names = "usb"; 623 status = "disabled"; 624 }; 625 626 ohci0: usb@1c1a400 { 627 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 628 reg = <0x01c1a400 0x100>; 629 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&ccu CLK_BUS_OHCI0>, 631 <&ccu CLK_USB_OHCI0>; 632 resets = <&ccu RST_BUS_OHCI0>; 633 phys = <&usbphy 0>; 634 phy-names = "usb"; 635 status = "disabled"; 636 }; 637 638 ehci1: usb@1c1b000 { 639 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 640 reg = <0x01c1b000 0x100>; 641 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&ccu CLK_BUS_OHCI1>, 643 <&ccu CLK_BUS_EHCI1>, 644 <&ccu CLK_USB_OHCI1>; 645 resets = <&ccu RST_BUS_OHCI1>, 646 <&ccu RST_BUS_EHCI1>; 647 phys = <&usbphy 1>; 648 phy-names = "usb"; 649 status = "disabled"; 650 }; 651 652 ohci1: usb@1c1b400 { 653 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 654 reg = <0x01c1b400 0x100>; 655 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&ccu CLK_BUS_OHCI1>, 657 <&ccu CLK_USB_OHCI1>; 658 resets = <&ccu RST_BUS_OHCI1>; 659 phys = <&usbphy 1>; 660 phy-names = "usb"; 661 status = "disabled"; 662 }; 663 664 ccu: clock@1c20000 { 665 compatible = "allwinner,sun50i-a64-ccu"; 666 reg = <0x01c20000 0x400>; 667 clocks = <&osc24M>, <&rtc CLK_OSC32K>; 668 clock-names = "hosc", "losc"; 669 #clock-cells = <1>; 670 #reset-cells = <1>; 671 }; 672 673 pio: pinctrl@1c20800 { 674 compatible = "allwinner,sun50i-a64-pinctrl"; 675 reg = <0x01c20800 0x400>; 676 interrupt-parent = <&r_intc>; 677 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, 681 <&rtc CLK_OSC32K>; 682 clock-names = "apb", "hosc", "losc"; 683 gpio-controller; 684 #gpio-cells = <3>; 685 interrupt-controller; 686 #interrupt-cells = <3>; 687 688 /omit-if-no-ref/ 689 aif2_pins: aif2-pins { 690 pins = "PB4", "PB5", "PB6", "PB7"; 691 function = "aif2"; 692 }; 693 694 /omit-if-no-ref/ 695 aif3_pins: aif3-pins { 696 pins = "PG10", "PG11", "PG12", "PG13"; 697 function = "aif3"; 698 }; 699 700 csi_pins: csi-pins { 701 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 702 "PE7", "PE8", "PE9", "PE10", "PE11"; 703 function = "csi"; 704 }; 705 706 /omit-if-no-ref/ 707 csi_mclk_pin: csi-mclk-pin { 708 pins = "PE1"; 709 function = "csi"; 710 }; 711 712 i2c0_pins: i2c0-pins { 713 pins = "PH0", "PH1"; 714 function = "i2c0"; 715 }; 716 717 i2c1_pins: i2c1-pins { 718 pins = "PH2", "PH3"; 719 function = "i2c1"; 720 }; 721 722 i2c2_pins: i2c2-pins { 723 pins = "PE14", "PE15"; 724 function = "i2c2"; 725 }; 726 727 /omit-if-no-ref/ 728 lcd_rgb666_pins: lcd-rgb666-pins { 729 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 730 "PD5", "PD6", "PD7", "PD8", "PD9", 731 "PD10", "PD11", "PD12", "PD13", 732 "PD14", "PD15", "PD16", "PD17", 733 "PD18", "PD19", "PD20", "PD21"; 734 function = "lcd0"; 735 }; 736 737 mmc0_pins: mmc0-pins { 738 pins = "PF0", "PF1", "PF2", "PF3", 739 "PF4", "PF5"; 740 function = "mmc0"; 741 drive-strength = <30>; 742 bias-pull-up; 743 }; 744 745 mmc1_pins: mmc1-pins { 746 pins = "PG0", "PG1", "PG2", "PG3", 747 "PG4", "PG5"; 748 function = "mmc1"; 749 drive-strength = <30>; 750 bias-pull-up; 751 }; 752 753 mmc2_pins: mmc2-pins { 754 pins = "PC5", "PC6", "PC8", "PC9", 755 "PC10","PC11", "PC12", "PC13", 756 "PC14", "PC15", "PC16"; 757 function = "mmc2"; 758 drive-strength = <30>; 759 bias-pull-up; 760 }; 761 762 mmc2_ds_pin: mmc2-ds-pin { 763 pins = "PC1"; 764 function = "mmc2"; 765 drive-strength = <30>; 766 bias-pull-up; 767 }; 768 769 pwm_pin: pwm-pin { 770 pins = "PD22"; 771 function = "pwm"; 772 }; 773 774 rmii_pins: rmii-pins { 775 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 776 "PD18", "PD19", "PD20", "PD22", "PD23"; 777 function = "emac"; 778 drive-strength = <40>; 779 }; 780 781 rgmii_pins: rgmii-pins { 782 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 783 "PD13", "PD15", "PD16", "PD17", "PD18", 784 "PD19", "PD20", "PD21", "PD22", "PD23"; 785 function = "emac"; 786 drive-strength = <40>; 787 }; 788 789 spdif_tx_pin: spdif-tx-pin { 790 pins = "PH8"; 791 function = "spdif"; 792 }; 793 794 spi0_pins: spi0-pins { 795 pins = "PC0", "PC1", "PC2", "PC3"; 796 function = "spi0"; 797 }; 798 799 spi1_pins: spi1-pins { 800 pins = "PD0", "PD1", "PD2", "PD3"; 801 function = "spi1"; 802 }; 803 804 uart0_pb_pins: uart0-pb-pins { 805 pins = "PB8", "PB9"; 806 function = "uart0"; 807 }; 808 809 uart1_pins: uart1-pins { 810 pins = "PG6", "PG7"; 811 function = "uart1"; 812 }; 813 814 uart1_rts_cts_pins: uart1-rts-cts-pins { 815 pins = "PG8", "PG9"; 816 function = "uart1"; 817 }; 818 819 uart2_pins: uart2-pins { 820 pins = "PB0", "PB1"; 821 function = "uart2"; 822 }; 823 824 uart3_pins: uart3-pins { 825 pins = "PD0", "PD1"; 826 function = "uart3"; 827 }; 828 829 uart4_pins: uart4-pins { 830 pins = "PD2", "PD3"; 831 function = "uart4"; 832 }; 833 834 uart4_rts_cts_pins: uart4-rts-cts-pins { 835 pins = "PD4", "PD5"; 836 function = "uart4"; 837 }; 838 }; 839 840 timer@1c20c00 { 841 compatible = "allwinner,sun50i-a64-timer", 842 "allwinner,sun8i-a23-timer"; 843 reg = <0x01c20c00 0xa0>; 844 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&osc24M>; 847 }; 848 849 wdt0: watchdog@1c20ca0 { 850 compatible = "allwinner,sun50i-a64-wdt", 851 "allwinner,sun6i-a31-wdt"; 852 reg = <0x01c20ca0 0x20>; 853 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&osc24M>; 855 }; 856 857 spdif: spdif@1c21000 { 858 #sound-dai-cells = <0>; 859 compatible = "allwinner,sun50i-a64-spdif", 860 "allwinner,sun8i-h3-spdif"; 861 reg = <0x01c21000 0x400>; 862 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 864 resets = <&ccu RST_BUS_SPDIF>; 865 clock-names = "apb", "spdif"; 866 dmas = <&dma 2>; 867 dma-names = "tx"; 868 pinctrl-names = "default"; 869 pinctrl-0 = <&spdif_tx_pin>; 870 status = "disabled"; 871 }; 872 873 lradc: lradc@1c21800 { 874 compatible = "allwinner,sun50i-a64-lradc", 875 "allwinner,sun8i-a83t-r-lradc"; 876 reg = <0x01c21800 0x400>; 877 interrupt-parent = <&r_intc>; 878 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 879 status = "disabled"; 880 }; 881 882 i2s0: i2s@1c22000 { 883 #sound-dai-cells = <0>; 884 compatible = "allwinner,sun50i-a64-i2s", 885 "allwinner,sun8i-h3-i2s"; 886 reg = <0x01c22000 0x400>; 887 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 889 clock-names = "apb", "mod"; 890 resets = <&ccu RST_BUS_I2S0>; 891 dma-names = "rx", "tx"; 892 dmas = <&dma 3>, <&dma 3>; 893 status = "disabled"; 894 }; 895 896 i2s1: i2s@1c22400 { 897 #sound-dai-cells = <0>; 898 compatible = "allwinner,sun50i-a64-i2s", 899 "allwinner,sun8i-h3-i2s"; 900 reg = <0x01c22400 0x400>; 901 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 903 clock-names = "apb", "mod"; 904 resets = <&ccu RST_BUS_I2S1>; 905 dma-names = "rx", "tx"; 906 dmas = <&dma 4>, <&dma 4>; 907 status = "disabled"; 908 }; 909 910 i2s2: i2s@1c22800 { 911 #sound-dai-cells = <0>; 912 compatible = "allwinner,sun50i-a64-i2s", 913 "allwinner,sun8i-h3-i2s"; 914 reg = <0x01c22800 0x400>; 915 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 917 clock-names = "apb", "mod"; 918 resets = <&ccu RST_BUS_I2S2>; 919 dma-names = "rx", "tx"; 920 dmas = <&dma 27>, <&dma 27>; 921 status = "disabled"; 922 }; 923 924 dai: dai@1c22c00 { 925 #sound-dai-cells = <0>; 926 compatible = "allwinner,sun50i-a64-codec-i2s"; 927 reg = <0x01c22c00 0x200>; 928 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 930 clock-names = "apb", "mod"; 931 resets = <&ccu RST_BUS_CODEC>; 932 dmas = <&dma 15>, <&dma 15>; 933 dma-names = "rx", "tx"; 934 status = "disabled"; 935 }; 936 937 codec: codec@1c22e00 { 938 #sound-dai-cells = <1>; 939 compatible = "allwinner,sun50i-a64-codec", 940 "allwinner,sun8i-a33-codec"; 941 reg = <0x01c22e00 0x600>; 942 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 944 clock-names = "bus", "mod"; 945 status = "disabled"; 946 }; 947 948 ths: thermal-sensor@1c25000 { 949 compatible = "allwinner,sun50i-a64-ths"; 950 reg = <0x01c25000 0x100>; 951 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 952 clock-names = "bus", "mod"; 953 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 954 resets = <&ccu RST_BUS_THS>; 955 nvmem-cells = <&ths_calibration>; 956 nvmem-cell-names = "calibration"; 957 #thermal-sensor-cells = <1>; 958 }; 959 960 uart0: serial@1c28000 { 961 compatible = "snps,dw-apb-uart"; 962 reg = <0x01c28000 0x400>; 963 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 964 reg-shift = <2>; 965 reg-io-width = <4>; 966 clocks = <&ccu CLK_BUS_UART0>; 967 resets = <&ccu RST_BUS_UART0>; 968 status = "disabled"; 969 }; 970 971 uart1: serial@1c28400 { 972 compatible = "snps,dw-apb-uart"; 973 reg = <0x01c28400 0x400>; 974 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 975 reg-shift = <2>; 976 reg-io-width = <4>; 977 clocks = <&ccu CLK_BUS_UART1>; 978 resets = <&ccu RST_BUS_UART1>; 979 status = "disabled"; 980 }; 981 982 uart2: serial@1c28800 { 983 compatible = "snps,dw-apb-uart"; 984 reg = <0x01c28800 0x400>; 985 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 986 reg-shift = <2>; 987 reg-io-width = <4>; 988 clocks = <&ccu CLK_BUS_UART2>; 989 resets = <&ccu RST_BUS_UART2>; 990 status = "disabled"; 991 }; 992 993 uart3: serial@1c28c00 { 994 compatible = "snps,dw-apb-uart"; 995 reg = <0x01c28c00 0x400>; 996 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 997 reg-shift = <2>; 998 reg-io-width = <4>; 999 clocks = <&ccu CLK_BUS_UART3>; 1000 resets = <&ccu RST_BUS_UART3>; 1001 status = "disabled"; 1002 }; 1003 1004 uart4: serial@1c29000 { 1005 compatible = "snps,dw-apb-uart"; 1006 reg = <0x01c29000 0x400>; 1007 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1008 reg-shift = <2>; 1009 reg-io-width = <4>; 1010 clocks = <&ccu CLK_BUS_UART4>; 1011 resets = <&ccu RST_BUS_UART4>; 1012 status = "disabled"; 1013 }; 1014 1015 i2c0: i2c@1c2ac00 { 1016 compatible = "allwinner,sun6i-a31-i2c"; 1017 reg = <0x01c2ac00 0x400>; 1018 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1019 clocks = <&ccu CLK_BUS_I2C0>; 1020 resets = <&ccu RST_BUS_I2C0>; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&i2c0_pins>; 1023 status = "disabled"; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 }; 1027 1028 i2c1: i2c@1c2b000 { 1029 compatible = "allwinner,sun6i-a31-i2c"; 1030 reg = <0x01c2b000 0x400>; 1031 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&ccu CLK_BUS_I2C1>; 1033 resets = <&ccu RST_BUS_I2C1>; 1034 pinctrl-names = "default"; 1035 pinctrl-0 = <&i2c1_pins>; 1036 status = "disabled"; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 }; 1040 1041 i2c2: i2c@1c2b400 { 1042 compatible = "allwinner,sun6i-a31-i2c"; 1043 reg = <0x01c2b400 0x400>; 1044 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&ccu CLK_BUS_I2C2>; 1046 resets = <&ccu RST_BUS_I2C2>; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&i2c2_pins>; 1049 status = "disabled"; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 }; 1053 1054 spi0: spi@1c68000 { 1055 compatible = "allwinner,sun8i-h3-spi"; 1056 reg = <0x01c68000 0x1000>; 1057 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1058 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 1059 clock-names = "ahb", "mod"; 1060 dmas = <&dma 23>, <&dma 23>; 1061 dma-names = "rx", "tx"; 1062 pinctrl-names = "default"; 1063 pinctrl-0 = <&spi0_pins>; 1064 resets = <&ccu RST_BUS_SPI0>; 1065 status = "disabled"; 1066 num-cs = <1>; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 }; 1070 1071 spi1: spi@1c69000 { 1072 compatible = "allwinner,sun8i-h3-spi"; 1073 reg = <0x01c69000 0x1000>; 1074 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 1076 clock-names = "ahb", "mod"; 1077 dmas = <&dma 24>, <&dma 24>; 1078 dma-names = "rx", "tx"; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&spi1_pins>; 1081 resets = <&ccu RST_BUS_SPI1>; 1082 status = "disabled"; 1083 num-cs = <1>; 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 }; 1087 1088 emac: ethernet@1c30000 { 1089 compatible = "allwinner,sun50i-a64-emac"; 1090 syscon = <&syscon>; 1091 reg = <0x01c30000 0x10000>; 1092 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1093 interrupt-names = "macirq"; 1094 resets = <&ccu RST_BUS_EMAC>; 1095 reset-names = "stmmaceth"; 1096 clocks = <&ccu CLK_BUS_EMAC>; 1097 clock-names = "stmmaceth"; 1098 status = "disabled"; 1099 1100 mdio: mdio { 1101 compatible = "snps,dwmac-mdio"; 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 }; 1105 }; 1106 1107 mali: gpu@1c40000 { 1108 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 1109 reg = <0x01c40000 0x10000>; 1110 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1117 interrupt-names = "gp", 1118 "gpmmu", 1119 "pp0", 1120 "ppmmu0", 1121 "pp1", 1122 "ppmmu1", 1123 "pmu"; 1124 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 1125 clock-names = "bus", "core"; 1126 resets = <&ccu RST_BUS_GPU>; 1127 operating-points-v2 = <&gpu_opp_table>; 1128 }; 1129 1130 gic: interrupt-controller@1c81000 { 1131 compatible = "arm,gic-400"; 1132 reg = <0x01c81000 0x1000>, 1133 <0x01c82000 0x2000>, 1134 <0x01c84000 0x2000>, 1135 <0x01c86000 0x2000>; 1136 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1137 interrupt-controller; 1138 #interrupt-cells = <3>; 1139 }; 1140 1141 pwm: pwm@1c21400 { 1142 compatible = "allwinner,sun50i-a64-pwm", 1143 "allwinner,sun5i-a13-pwm"; 1144 reg = <0x01c21400 0x400>; 1145 clocks = <&osc24M>; 1146 pinctrl-names = "default"; 1147 pinctrl-0 = <&pwm_pin>; 1148 #pwm-cells = <3>; 1149 status = "disabled"; 1150 }; 1151 1152 mbus: dram-controller@1c62000 { 1153 compatible = "allwinner,sun50i-a64-mbus"; 1154 reg = <0x01c62000 0x1000>, 1155 <0x01c63000 0x1000>; 1156 reg-names = "mbus", "dram"; 1157 clocks = <&ccu CLK_MBUS>, 1158 <&ccu CLK_DRAM>, 1159 <&ccu CLK_BUS_DRAM>; 1160 clock-names = "mbus", "dram", "bus"; 1161 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1162 #address-cells = <1>; 1163 #size-cells = <1>; 1164 dma-ranges = <0x00000000 0x40000000 0xc0000000>; 1165 #interconnect-cells = <1>; 1166 }; 1167 1168 csi: csi@1cb0000 { 1169 compatible = "allwinner,sun50i-a64-csi"; 1170 reg = <0x01cb0000 0x1000>; 1171 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1172 clocks = <&ccu CLK_BUS_CSI>, 1173 <&ccu CLK_CSI_SCLK>, 1174 <&ccu CLK_DRAM_CSI>; 1175 clock-names = "bus", "mod", "ram"; 1176 resets = <&ccu RST_BUS_CSI>; 1177 pinctrl-names = "default"; 1178 pinctrl-0 = <&csi_pins>; 1179 status = "disabled"; 1180 }; 1181 1182 dsi: dsi@1ca0000 { 1183 compatible = "allwinner,sun50i-a64-mipi-dsi"; 1184 reg = <0x01ca0000 0x1000>; 1185 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1186 clocks = <&ccu CLK_BUS_MIPI_DSI>; 1187 resets = <&ccu RST_BUS_MIPI_DSI>; 1188 phys = <&dphy>; 1189 phy-names = "dphy"; 1190 status = "disabled"; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 1194 port { 1195 dsi_in_tcon0: endpoint { 1196 remote-endpoint = <&tcon0_out_dsi>; 1197 }; 1198 }; 1199 }; 1200 1201 dphy: d-phy@1ca1000 { 1202 compatible = "allwinner,sun50i-a64-mipi-dphy", 1203 "allwinner,sun6i-a31-mipi-dphy"; 1204 reg = <0x01ca1000 0x1000>; 1205 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1206 clocks = <&ccu CLK_BUS_MIPI_DSI>, 1207 <&ccu CLK_DSI_DPHY>; 1208 clock-names = "bus", "mod"; 1209 resets = <&ccu RST_BUS_MIPI_DSI>; 1210 status = "disabled"; 1211 #phy-cells = <0>; 1212 }; 1213 1214 deinterlace: deinterlace@1e00000 { 1215 compatible = "allwinner,sun50i-a64-deinterlace", 1216 "allwinner,sun8i-h3-deinterlace"; 1217 reg = <0x01e00000 0x20000>; 1218 clocks = <&ccu CLK_BUS_DEINTERLACE>, 1219 <&ccu CLK_DEINTERLACE>, 1220 <&ccu CLK_DRAM_DEINTERLACE>; 1221 clock-names = "bus", "mod", "ram"; 1222 resets = <&ccu RST_BUS_DEINTERLACE>; 1223 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1224 interconnects = <&mbus 9>; 1225 interconnect-names = "dma-mem"; 1226 }; 1227 1228 hdmi: hdmi@1ee0000 { 1229 compatible = "allwinner,sun50i-a64-dw-hdmi", 1230 "allwinner,sun8i-a83t-dw-hdmi"; 1231 reg = <0x01ee0000 0x10000>; 1232 reg-io-width = <1>; 1233 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1234 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1235 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; 1236 clock-names = "iahb", "isfr", "tmds", "cec"; 1237 resets = <&ccu RST_BUS_HDMI1>; 1238 reset-names = "ctrl"; 1239 phys = <&hdmi_phy>; 1240 phy-names = "phy"; 1241 status = "disabled"; 1242 1243 ports { 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 1247 hdmi_in: port@0 { 1248 reg = <0>; 1249 1250 hdmi_in_tcon1: endpoint { 1251 remote-endpoint = <&tcon1_out_hdmi>; 1252 }; 1253 }; 1254 1255 hdmi_out: port@1 { 1256 reg = <1>; 1257 }; 1258 }; 1259 }; 1260 1261 hdmi_phy: hdmi-phy@1ef0000 { 1262 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1263 reg = <0x01ef0000 0x10000>; 1264 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1265 <&ccu CLK_PLL_VIDEO0>; 1266 clock-names = "bus", "mod", "pll-0"; 1267 resets = <&ccu RST_BUS_HDMI0>; 1268 reset-names = "phy"; 1269 #phy-cells = <0>; 1270 }; 1271 1272 rtc: rtc@1f00000 { 1273 compatible = "allwinner,sun50i-a64-rtc", 1274 "allwinner,sun8i-h3-rtc"; 1275 reg = <0x01f00000 0x400>; 1276 interrupt-parent = <&r_intc>; 1277 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1279 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1280 clocks = <&osc32k>; 1281 #clock-cells = <1>; 1282 }; 1283 1284 r_intc: interrupt-controller@1f00c00 { 1285 compatible = "allwinner,sun50i-a64-r-intc", 1286 "allwinner,sun6i-a31-r-intc"; 1287 interrupt-controller; 1288 #interrupt-cells = <3>; 1289 reg = <0x01f00c00 0x400>; 1290 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1291 }; 1292 1293 r_ccu: clock@1f01400 { 1294 compatible = "allwinner,sun50i-a64-r-ccu"; 1295 reg = <0x01f01400 0x100>; 1296 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 1297 <&ccu CLK_PLL_PERIPH0>; 1298 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1299 #clock-cells = <1>; 1300 #reset-cells = <1>; 1301 }; 1302 1303 codec_analog: codec-analog@1f015c0 { 1304 compatible = "allwinner,sun50i-a64-codec-analog"; 1305 reg = <0x01f015c0 0x4>; 1306 status = "disabled"; 1307 }; 1308 1309 r_i2c: i2c@1f02400 { 1310 compatible = "allwinner,sun50i-a64-i2c", 1311 "allwinner,sun6i-a31-i2c"; 1312 reg = <0x01f02400 0x400>; 1313 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1314 clocks = <&r_ccu CLK_APB0_I2C>; 1315 resets = <&r_ccu RST_APB0_I2C>; 1316 status = "disabled"; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 }; 1320 1321 r_ir: ir@1f02000 { 1322 compatible = "allwinner,sun50i-a64-ir", 1323 "allwinner,sun6i-a31-ir"; 1324 reg = <0x01f02000 0x400>; 1325 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1326 clock-names = "apb", "ir"; 1327 resets = <&r_ccu RST_APB0_IR>; 1328 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1329 pinctrl-names = "default"; 1330 pinctrl-0 = <&r_ir_rx_pin>; 1331 status = "disabled"; 1332 }; 1333 1334 r_pwm: pwm@1f03800 { 1335 compatible = "allwinner,sun50i-a64-pwm", 1336 "allwinner,sun5i-a13-pwm"; 1337 reg = <0x01f03800 0x400>; 1338 clocks = <&osc24M>; 1339 pinctrl-names = "default"; 1340 pinctrl-0 = <&r_pwm_pin>; 1341 #pwm-cells = <3>; 1342 status = "disabled"; 1343 }; 1344 1345 r_pio: pinctrl@1f02c00 { 1346 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1347 reg = <0x01f02c00 0x400>; 1348 interrupt-parent = <&r_intc>; 1349 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1350 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1351 clock-names = "apb", "hosc", "losc"; 1352 gpio-controller; 1353 #gpio-cells = <3>; 1354 interrupt-controller; 1355 #interrupt-cells = <3>; 1356 1357 r_i2c_pl89_pins: r-i2c-pl89-pins { 1358 pins = "PL8", "PL9"; 1359 function = "s_i2c"; 1360 }; 1361 1362 r_ir_rx_pin: r-ir-rx-pin { 1363 pins = "PL11"; 1364 function = "s_cir_rx"; 1365 }; 1366 1367 r_pwm_pin: r-pwm-pin { 1368 pins = "PL10"; 1369 function = "s_pwm"; 1370 }; 1371 1372 r_rsb_pins: r-rsb-pins { 1373 pins = "PL0", "PL1"; 1374 function = "s_rsb"; 1375 }; 1376 }; 1377 1378 r_rsb: rsb@1f03400 { 1379 compatible = "allwinner,sun8i-a23-rsb"; 1380 reg = <0x01f03400 0x400>; 1381 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1382 clocks = <&r_ccu 6>; 1383 clock-frequency = <3000000>; 1384 resets = <&r_ccu 2>; 1385 pinctrl-names = "default"; 1386 pinctrl-0 = <&r_rsb_pins>; 1387 status = "disabled"; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 }; 1391 }; 1392}; 1393