1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include <dt-bindings/phy/phy-imx8-pcie.h> 7#include <dt-bindings/pwm/pwm.h> 8#include "imx8mm.dtsi" 9 10/ { 11 chosen { 12 stdout-path = &uart1; 13 }; 14 15 aliases { 16 rtc0 = &rtc_i2c; 17 rtc1 = &snvs_rtc; 18 }; 19 20 backlight: backlight { 21 compatible = "pwm-backlight"; 22 brightness-levels = <0 45 63 88 119 158 203 255>; 23 default-brightness-level = <4>; 24 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 25 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 28 power-supply = <®_3p3v>; 29 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 30 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; 31 status = "disabled"; 32 }; 33 34 /* Fixed clock dedicated to SPI CAN controller */ 35 clk40m: oscillator { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <40000000>; 39 }; 40 41 gpio-keys { 42 compatible = "gpio-keys"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_gpio_keys>; 45 46 key-wakeup { 47 debounce-interval = <10>; 48 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 49 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 50 label = "Wake-Up"; 51 linux,code = <KEY_WAKEUP>; 52 wakeup-source; 53 }; 54 }; 55 56 hdmi_connector: hdmi-connector { 57 compatible = "hdmi-connector"; 58 ddc-i2c-bus = <&i2c2>; 59 /* Verdin PWM_3_DSI (SODIMM 19) */ 60 hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 61 label = "hdmi"; 62 pinctrl-names = "default"; 63 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>; 64 type = "a"; 65 status = "disabled"; 66 }; 67 68 panel_lvds: panel-lvds { 69 compatible = "panel-lvds"; 70 backlight = <&backlight>; 71 data-mapping = "vesa-24"; 72 status = "disabled"; 73 }; 74 75 /* Carrier Board Supplies */ 76 reg_1p8v: regulator-1p8v { 77 compatible = "regulator-fixed"; 78 regulator-max-microvolt = <1800000>; 79 regulator-min-microvolt = <1800000>; 80 regulator-name = "+V1.8_SW"; 81 }; 82 83 reg_3p3v: regulator-3p3v { 84 compatible = "regulator-fixed"; 85 regulator-max-microvolt = <3300000>; 86 regulator-min-microvolt = <3300000>; 87 regulator-name = "+V3.3_SW"; 88 }; 89 90 reg_5p0v: regulator-5p0v { 91 compatible = "regulator-fixed"; 92 regulator-max-microvolt = <5000000>; 93 regulator-min-microvolt = <5000000>; 94 regulator-name = "+V5_SW"; 95 }; 96 97 /* Non PMIC On-module Supplies */ 98 reg_ethphy: regulator-ethphy { 99 compatible = "regulator-fixed"; 100 enable-active-high; 101 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 102 off-on-delay-us = <500000>; 103 pinctrl-names = "default"; 104 pinctrl-0 = <&pinctrl_reg_eth>; 105 regulator-always-on; 106 regulator-boot-on; 107 regulator-max-microvolt = <3300000>; 108 regulator-min-microvolt = <3300000>; 109 regulator-name = "On-module +V3.3_ETH"; 110 startup-delay-us = <200000>; 111 }; 112 113 reg_usb_otg1_vbus: regulator-usb-otg1 { 114 compatible = "regulator-fixed"; 115 enable-active-high; 116 /* Verdin USB_1_EN (SODIMM 155) */ 117 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 118 pinctrl-names = "default"; 119 pinctrl-0 = <&pinctrl_reg_usb1_en>; 120 regulator-max-microvolt = <5000000>; 121 regulator-min-microvolt = <5000000>; 122 regulator-name = "USB_1_EN"; 123 }; 124 125 reg_usb_otg2_vbus: regulator-usb-otg2 { 126 compatible = "regulator-fixed"; 127 enable-active-high; 128 /* Verdin USB_2_EN (SODIMM 185) */ 129 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_reg_usb2_en>; 132 regulator-max-microvolt = <5000000>; 133 regulator-min-microvolt = <5000000>; 134 regulator-name = "USB_2_EN"; 135 }; 136 137 reg_usdhc2_vmmc: regulator-usdhc2 { 138 compatible = "regulator-fixed"; 139 enable-active-high; 140 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 141 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 142 off-on-delay-us = <100000>; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 145 regulator-max-microvolt = <3300000>; 146 regulator-min-microvolt = <3300000>; 147 regulator-name = "+V3.3_SD"; 148 startup-delay-us = <20000>; 149 }; 150 151 reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 152 compatible = "regulator-gpio"; 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_usdhc2_vsel>; 155 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 156 regulator-max-microvolt = <3300000>; 157 regulator-min-microvolt = <1800000>; 158 states = <1800000 0x1>, 159 <3300000 0x0>; 160 regulator-name = "PMIC_USDHC_VSELECT"; 161 vin-supply = <®_nvcc_sd>; 162 }; 163 164 reserved-memory { 165 #address-cells = <2>; 166 #size-cells = <2>; 167 ranges; 168 169 /* Use the kernel configuration settings instead */ 170 /delete-node/ linux,cma; 171 }; 172}; 173 174&A53_0 { 175 cpu-supply = <®_vdd_arm>; 176}; 177 178&A53_1 { 179 cpu-supply = <®_vdd_arm>; 180}; 181 182&A53_2 { 183 cpu-supply = <®_vdd_arm>; 184}; 185 186&A53_3 { 187 cpu-supply = <®_vdd_arm>; 188}; 189 190&cpu_alert0 { 191 temperature = <95000>; 192}; 193 194&cpu_crit0 { 195 temperature = <105000>; 196}; 197 198&ddrc { 199 operating-points-v2 = <&ddrc_opp_table>; 200 201 ddrc_opp_table: opp-table { 202 compatible = "operating-points-v2"; 203 204 opp-25000000 { 205 opp-hz = /bits/ 64 <25000000>; 206 }; 207 208 opp-100000000 { 209 opp-hz = /bits/ 64 <100000000>; 210 }; 211 212 opp-750000000 { 213 opp-hz = /bits/ 64 <750000000>; 214 }; 215 }; 216}; 217 218/* Verdin SPI_1 */ 219&ecspi2 { 220 #address-cells = <1>; 221 #size-cells = <0>; 222 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_ecspi2>; 225}; 226 227/* Verdin CAN_1 (On-module) */ 228&ecspi3 { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&pinctrl_ecspi3>; 234 status = "okay"; 235 236 can1: can@0 { 237 compatible = "microchip,mcp251xfd"; 238 clocks = <&clk40m>; 239 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_can1_int>; 242 reg = <0>; 243 spi-max-frequency = <8500000>; 244 }; 245}; 246 247/* Verdin ETH_1 (On-module PHY) */ 248&fec1 { 249 fsl,magic-packet; 250 phy-handle = <ðphy0>; 251 phy-mode = "rgmii-id"; 252 phy-supply = <®_ethphy>; 253 pinctrl-names = "default", "sleep"; 254 pinctrl-0 = <&pinctrl_fec1>; 255 pinctrl-1 = <&pinctrl_fec1_sleep>; 256 257 mdio { 258 #address-cells = <1>; 259 #size-cells = <0>; 260 261 ethphy0: ethernet-phy@7 { 262 compatible = "ethernet-phy-ieee802.3-c22"; 263 interrupt-parent = <&gpio1>; 264 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 265 micrel,led-mode = <0>; 266 reg = <7>; 267 }; 268 }; 269}; 270 271/* Verdin QSPI_1 */ 272&flexspi { 273 pinctrl-names = "default"; 274 pinctrl-0 = <&pinctrl_flexspi0>; 275}; 276 277&gpio1 { 278 gpio-line-names = "SODIMM_216", 279 "SODIMM_19", 280 "", 281 "", 282 "PMIC_USDHC_VSELECT", 283 "", 284 "", 285 "", 286 "SODIMM_220", 287 "SODIMM_222", 288 "", 289 "SODIMM_218", 290 "SODIMM_155", 291 "SODIMM_157", 292 "SODIMM_185", 293 "SODIMM_187"; 294}; 295 296&gpio2 { 297 gpio-line-names = "", 298 "", 299 "", 300 "", 301 "", 302 "", 303 "", 304 "", 305 "", 306 "", 307 "", 308 "", 309 "SODIMM_84", 310 "SODIMM_78", 311 "SODIMM_74", 312 "SODIMM_80", 313 "SODIMM_82", 314 "SODIMM_70", 315 "SODIMM_72"; 316}; 317 318&gpio5 { 319 gpio-line-names = "SODIMM_131", 320 "", 321 "SODIMM_91", 322 "SODIMM_16", 323 "SODIMM_15", 324 "SODIMM_208", 325 "SODIMM_137", 326 "SODIMM_139", 327 "SODIMM_141", 328 "SODIMM_143", 329 "SODIMM_196", 330 "SODIMM_200", 331 "SODIMM_198", 332 "SODIMM_202", 333 "", 334 "", 335 "SODIMM_55", 336 "SODIMM_53", 337 "SODIMM_95", 338 "SODIMM_93", 339 "SODIMM_14", 340 "SODIMM_12", 341 "", 342 "", 343 "", 344 "", 345 "SODIMM_210", 346 "SODIMM_212", 347 "SODIMM_151", 348 "SODIMM_153"; 349 350 ctrl-sleep-moci-hog { 351 gpio-hog; 352 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 353 gpios = <1 GPIO_ACTIVE_HIGH>; 354 line-name = "CTRL_SLEEP_MOCI#"; 355 output-high; 356 pinctrl-names = "default"; 357 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 358 }; 359}; 360 361/* On-module I2C */ 362&i2c1 { 363 clock-frequency = <400000>; 364 pinctrl-names = "default", "gpio"; 365 pinctrl-0 = <&pinctrl_i2c1>; 366 pinctrl-1 = <&pinctrl_i2c1_gpio>; 367 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 368 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 369 status = "okay"; 370 371 pca9450: pmic@25 { 372 compatible = "nxp,pca9450a"; 373 interrupt-parent = <&gpio1>; 374 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 375 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&pinctrl_pmic>; 378 reg = <0x25>; 379 380 /* 381 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC 382 * behind this PMIC. 383 */ 384 385 regulators { 386 reg_vdd_soc: BUCK1 { 387 nxp,dvs-run-voltage = <850000>; 388 nxp,dvs-standby-voltage = <800000>; 389 regulator-always-on; 390 regulator-boot-on; 391 regulator-max-microvolt = <850000>; 392 regulator-min-microvolt = <800000>; 393 regulator-name = "On-module +VDD_SOC (BUCK1)"; 394 regulator-ramp-delay = <3125>; 395 }; 396 397 reg_vdd_arm: BUCK2 { 398 nxp,dvs-run-voltage = <950000>; 399 nxp,dvs-standby-voltage = <850000>; 400 regulator-always-on; 401 regulator-boot-on; 402 regulator-max-microvolt = <1050000>; 403 regulator-min-microvolt = <805000>; 404 regulator-name = "On-module +VDD_ARM (BUCK2)"; 405 regulator-ramp-delay = <3125>; 406 }; 407 408 reg_vdd_dram: BUCK3 { 409 regulator-always-on; 410 regulator-boot-on; 411 regulator-max-microvolt = <1000000>; 412 regulator-min-microvolt = <805000>; 413 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; 414 }; 415 416 reg_vdd_3v3: BUCK4 { 417 regulator-always-on; 418 regulator-boot-on; 419 regulator-max-microvolt = <3300000>; 420 regulator-min-microvolt = <3300000>; 421 regulator-name = "On-module +V3.3 (BUCK4)"; 422 }; 423 424 reg_vdd_1v8: BUCK5 { 425 regulator-always-on; 426 regulator-boot-on; 427 regulator-max-microvolt = <1800000>; 428 regulator-min-microvolt = <1800000>; 429 regulator-name = "PWR_1V8_MOCI (BUCK5)"; 430 }; 431 432 reg_nvcc_dram: BUCK6 { 433 regulator-always-on; 434 regulator-boot-on; 435 regulator-max-microvolt = <1100000>; 436 regulator-min-microvolt = <1100000>; 437 regulator-name = "On-module +VDD_DDR (BUCK6)"; 438 }; 439 440 reg_nvcc_snvs: LDO1 { 441 regulator-always-on; 442 regulator-boot-on; 443 regulator-max-microvolt = <1800000>; 444 regulator-min-microvolt = <1800000>; 445 regulator-name = "On-module +V1.8_SNVS (LDO1)"; 446 }; 447 448 reg_vdd_snvs: LDO2 { 449 regulator-always-on; 450 regulator-boot-on; 451 regulator-max-microvolt = <800000>; 452 regulator-min-microvolt = <800000>; 453 regulator-name = "On-module +V0.8_SNVS (LDO2)"; 454 }; 455 456 reg_vdda: LDO3 { 457 regulator-always-on; 458 regulator-boot-on; 459 regulator-max-microvolt = <1800000>; 460 regulator-min-microvolt = <1800000>; 461 regulator-name = "On-module +V1.8A (LDO3)"; 462 }; 463 464 reg_vdd_phy: LDO4 { 465 regulator-always-on; 466 regulator-boot-on; 467 regulator-max-microvolt = <900000>; 468 regulator-min-microvolt = <900000>; 469 regulator-name = "On-module +V0.9_MIPI (LDO4)"; 470 }; 471 472 reg_nvcc_sd: LDO5 { 473 regulator-always-on; 474 regulator-max-microvolt = <3300000>; 475 regulator-min-microvolt = <1800000>; 476 regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 477 }; 478 }; 479 }; 480 481 rtc_i2c: rtc@32 { 482 compatible = "epson,rx8130"; 483 reg = <0x32>; 484 }; 485 486 adc@49 { 487 compatible = "ti,ads1015"; 488 reg = <0x49>; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 492 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 493 channel@0 { 494 reg = <0>; 495 ti,datarate = <4>; 496 ti,gain = <2>; 497 }; 498 499 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 500 channel@1 { 501 reg = <1>; 502 ti,datarate = <4>; 503 ti,gain = <2>; 504 }; 505 506 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 507 channel@2 { 508 reg = <2>; 509 ti,datarate = <4>; 510 ti,gain = <2>; 511 }; 512 513 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 514 channel@3 { 515 reg = <3>; 516 ti,datarate = <4>; 517 ti,gain = <2>; 518 }; 519 520 /* Verdin I2C_1 ADC_4 */ 521 channel@4 { 522 reg = <4>; 523 ti,datarate = <4>; 524 ti,gain = <2>; 525 }; 526 527 /* Verdin I2C_1 ADC_3 */ 528 channel@5 { 529 reg = <5>; 530 ti,datarate = <4>; 531 ti,gain = <2>; 532 }; 533 534 /* Verdin I2C_1 ADC_2 */ 535 channel@6 { 536 reg = <6>; 537 ti,datarate = <4>; 538 ti,gain = <2>; 539 }; 540 541 /* Verdin I2C_1 ADC_1 */ 542 channel@7 { 543 reg = <7>; 544 ti,datarate = <4>; 545 ti,gain = <2>; 546 }; 547 }; 548 549 eeprom@50 { 550 compatible = "st,24c02"; 551 pagesize = <16>; 552 reg = <0x50>; 553 }; 554}; 555 556/* Verdin I2C_2_DSI */ 557&i2c2 { 558 clock-frequency = <10000>; 559 pinctrl-names = "default", "gpio"; 560 pinctrl-0 = <&pinctrl_i2c2>; 561 pinctrl-1 = <&pinctrl_i2c2_gpio>; 562 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 563 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 564 status = "disabled"; 565}; 566 567/* Verdin I2C_3_HDMI N/A */ 568 569/* Verdin I2C_4_CSI */ 570&i2c3 { 571 clock-frequency = <400000>; 572 pinctrl-names = "default", "gpio"; 573 pinctrl-0 = <&pinctrl_i2c3>; 574 pinctrl-1 = <&pinctrl_i2c3_gpio>; 575 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 576 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 577}; 578 579/* Verdin I2C_1 */ 580&i2c4 { 581 clock-frequency = <400000>; 582 pinctrl-names = "default", "gpio"; 583 pinctrl-0 = <&pinctrl_i2c4>; 584 pinctrl-1 = <&pinctrl_i2c4_gpio>; 585 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 586 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 587 588 gpio_expander_21: gpio-expander@21 { 589 compatible = "nxp,pcal6416"; 590 #gpio-cells = <2>; 591 gpio-controller; 592 reg = <0x21>; 593 vcc-supply = <®_3p3v>; 594 status = "disabled"; 595 }; 596 597 lvds_ti_sn65dsi84: bridge@2c { 598 compatible = "ti,sn65dsi84"; 599 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 600 /* Verdin GPIO_10_DSI (SODIMM 21) */ 601 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 602 pinctrl-names = "default"; 603 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 604 reg = <0x2c>; 605 status = "disabled"; 606 }; 607 608 /* Current measurement into module VCC */ 609 hwmon: hwmon@40 { 610 compatible = "ti,ina219"; 611 reg = <0x40>; 612 shunt-resistor = <10000>; 613 status = "disabled"; 614 }; 615 616 hdmi_lontium_lt8912: hdmi@48 { 617 compatible = "lontium,lt8912b"; 618 pinctrl-names = "default"; 619 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 620 reg = <0x48>; 621 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 622 /* Verdin GPIO_10_DSI (SODIMM 21) */ 623 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; 624 status = "disabled"; 625 }; 626 627 atmel_mxt_ts: touch@4a { 628 compatible = "atmel,maxtouch"; 629 /* 630 * Verdin GPIO_9_DSI 631 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) 632 */ 633 interrupt-parent = <&gpio3>; 634 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 635 pinctrl-names = "default"; 636 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 637 reg = <0x4a>; 638 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 639 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 640 status = "disabled"; 641 }; 642 643 /* Temperature sensor on carrier board */ 644 hwmon_temp: sensor@4f { 645 compatible = "ti,tmp75c"; 646 reg = <0x4f>; 647 status = "disabled"; 648 }; 649 650 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 651 eeprom_display_adapter: eeprom@50 { 652 compatible = "st,24c02"; 653 pagesize = <16>; 654 reg = <0x50>; 655 status = "disabled"; 656 }; 657 658 /* EEPROM on carrier board */ 659 eeprom_carrier_board: eeprom@57 { 660 compatible = "st,24c02"; 661 pagesize = <16>; 662 reg = <0x57>; 663 status = "disabled"; 664 }; 665}; 666 667/* Verdin PCIE_1 */ 668&pcie0 { 669 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 670 <&clk IMX8MM_CLK_PCIE1_CTRL>; 671 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 672 <&clk IMX8MM_SYS_PLL2_250M>; 673 assigned-clock-rates = <10000000>, <250000000>; 674 pinctrl-names = "default"; 675 pinctrl-0 = <&pinctrl_pcie0>; 676 /* PCIE_1_RESET# (SODIMM 244) */ 677 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 678}; 679 680&pcie_phy { 681 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 682 clock-names = "ref"; 683 fsl,clkreq-unsupported; 684 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 685 fsl,tx-deemph-gen1 = <0x2d>; 686 fsl,tx-deemph-gen2 = <0xf>; 687}; 688 689/* Verdin PWM_3_DSI */ 690&pwm1 { 691 pinctrl-names = "default"; 692 pinctrl-0 = <&pinctrl_pwm_1>; 693 #pwm-cells = <3>; 694}; 695 696/* Verdin PWM_1 */ 697&pwm2 { 698 pinctrl-names = "default"; 699 pinctrl-0 = <&pinctrl_pwm_2>; 700 #pwm-cells = <3>; 701}; 702 703/* Verdin PWM_2 */ 704&pwm3 { 705 pinctrl-names = "default"; 706 pinctrl-0 = <&pinctrl_pwm_3>; 707 #pwm-cells = <3>; 708}; 709 710/* Verdin I2S_1 */ 711&sai2 { 712 #sound-dai-cells = <0>; 713 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 714 assigned-clock-rates = <24576000>; 715 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 716 pinctrl-names = "default"; 717 pinctrl-0 = <&pinctrl_sai2>; 718}; 719 720&snvs_pwrkey { 721 status = "okay"; 722}; 723 724/* Verdin UART_3, used as the Linux console */ 725&uart1 { 726 pinctrl-names = "default"; 727 pinctrl-0 = <&pinctrl_uart1>; 728}; 729 730/* Verdin UART_1 */ 731&uart2 { 732 pinctrl-names = "default"; 733 pinctrl-0 = <&pinctrl_uart2>; 734 uart-has-rtscts; 735}; 736 737/* Verdin UART_2 */ 738&uart3 { 739 pinctrl-names = "default"; 740 pinctrl-0 = <&pinctrl_uart3>; 741 uart-has-rtscts; 742}; 743 744/* 745 * Verdin UART_4 746 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS 747 */ 748&uart4 { 749 pinctrl-names = "default"; 750 pinctrl-0 = <&pinctrl_uart4>; 751}; 752 753/* Verdin USB_1 */ 754&usbotg1 { 755 adp-disable; 756 dr_mode = "otg"; 757 hnp-disable; 758 samsung,picophy-dc-vol-level-adjust = <7>; 759 samsung,picophy-pre-emp-curr-control = <3>; 760 srp-disable; 761 vbus-supply = <®_usb_otg1_vbus>; 762}; 763 764/* Verdin USB_2 */ 765&usbotg2 { 766 dr_mode = "host"; 767 samsung,picophy-dc-vol-level-adjust = <7>; 768 samsung,picophy-pre-emp-curr-control = <3>; 769 vbus-supply = <®_usb_otg2_vbus>; 770}; 771 772&usbphynop1 { 773 vcc-supply = <®_vdd_3v3>; 774}; 775 776&usbphynop2 { 777 power-domains = <&pgc_otg2>; 778 vcc-supply = <®_vdd_3v3>; 779}; 780 781/* On-module eMMC */ 782&usdhc1 { 783 bus-width = <8>; 784 keep-power-in-suspend; 785 non-removable; 786 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 787 pinctrl-0 = <&pinctrl_usdhc1>; 788 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 789 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 790 status = "okay"; 791}; 792 793/* Verdin SD_1 */ 794&usdhc2 { 795 bus-width = <4>; 796 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 797 disable-wp; 798 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 799 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 800 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 801 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 802 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 803 vmmc-supply = <®_usdhc2_vmmc>; 804 vqmmc-supply = <®_usdhc2_vqmmc>; 805}; 806 807&wdog1 { 808 fsl,ext-reset-output; 809 pinctrl-names = "default"; 810 pinctrl-0 = <&pinctrl_wdog>; 811 status = "okay"; 812}; 813 814&iomuxc { 815 pinctrl-names = "default"; 816 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 817 <&pinctrl_gpio3>, <&pinctrl_gpio4>, 818 <&pinctrl_gpio7>, <&pinctrl_gpio8>, 819 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, 820 <&pinctrl_pmic_tpm_ena>; 821 822 pinctrl_can1_int: can1intgrp { 823 fsl,pins = 824 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */ 825 }; 826 827 pinctrl_can2_int: can2intgrp { 828 fsl,pins = 829 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */ 830 }; 831 832 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 833 fsl,pins = 834 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */ 835 }; 836 837 pinctrl_ecspi2: ecspi2grp { 838 fsl,pins = 839 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */ 840 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */ 841 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */ 842 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */ 843 }; 844 845 pinctrl_ecspi3: ecspi3grp { 846 fsl,pins = 847 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */ 848 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */ 849 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */ 850 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */ 851 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */ 852 }; 853 854 pinctrl_fec1: fec1grp { 855 fsl,pins = 856 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 857 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 858 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 859 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 860 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 861 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 862 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 863 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 864 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, 865 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, 866 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, 867 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, 868 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, 869 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, 870 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>; 871 }; 872 873 pinctrl_fec1_sleep: fec1-sleepgrp { 874 fsl,pins = 875 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 876 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 877 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 878 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 879 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 880 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 881 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 882 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 883 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>, 884 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>, 885 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>, 886 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>, 887 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, 888 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, 889 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>; 890 }; 891 892 pinctrl_flexspi0: flexspi0grp { 893 fsl,pins = 894 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */ 895 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */ 896 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */ 897 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */ 898 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */ 899 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */ 900 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */ 901 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */ 902 }; 903 904 pinctrl_gpio1: gpio1grp { 905 fsl,pins = 906 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */ 907 }; 908 909 pinctrl_gpio2: gpio2grp { 910 fsl,pins = 911 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */ 912 }; 913 914 pinctrl_gpio3: gpio3grp { 915 fsl,pins = 916 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */ 917 }; 918 919 pinctrl_gpio4: gpio4grp { 920 fsl,pins = 921 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */ 922 }; 923 924 pinctrl_gpio5: gpio5grp { 925 fsl,pins = 926 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */ 927 }; 928 929 pinctrl_gpio6: gpio6grp { 930 fsl,pins = 931 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */ 932 }; 933 934 pinctrl_gpio7: gpio7grp { 935 fsl,pins = 936 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */ 937 }; 938 939 pinctrl_gpio8: gpio8grp { 940 fsl,pins = 941 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */ 942 }; 943 944 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 945 pinctrl_gpio_9_dsi: gpio9dsigrp { 946 fsl,pins = 947 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c6>; /* SODIMM 17 */ 948 }; 949 950 /* Verdin GPIO_10_DSI (pulled-up as active-low) */ 951 pinctrl_gpio_10_dsi: gpio10dsigrp { 952 fsl,pins = 953 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */ 954 }; 955 956 pinctrl_gpio_hog1: gpiohog1grp { 957 fsl,pins = 958 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */ 959 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */ 960 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */ 961 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */ 962 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */ 963 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */ 964 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */ 965 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */ 966 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */ 967 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */ 968 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */ 969 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */ 970 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */ 971 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */ 972 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */ 973 }; 974 975 pinctrl_gpio_hog2: gpiohog2grp { 976 fsl,pins = 977 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */ 978 }; 979 980 pinctrl_gpio_hog3: gpiohog3grp { 981 fsl,pins = 982 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */ 983 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */ 984 }; 985 986 pinctrl_gpio_keys: gpiokeysgrp { 987 fsl,pins = 988 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */ 989 }; 990 991 /* On-module I2C */ 992 pinctrl_i2c1: i2c1grp { 993 fsl,pins = 994 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */ 995 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */ 996 }; 997 998 pinctrl_i2c1_gpio: i2c1gpiogrp { 999 fsl,pins = 1000 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */ 1001 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */ 1002 }; 1003 1004 /* Verdin I2C_4_CSI */ 1005 pinctrl_i2c2: i2c2grp { 1006 fsl,pins = 1007 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */ 1008 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */ 1009 }; 1010 1011 pinctrl_i2c2_gpio: i2c2gpiogrp { 1012 fsl,pins = 1013 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */ 1014 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */ 1015 }; 1016 1017 /* Verdin I2C_2_DSI */ 1018 pinctrl_i2c3: i2c3grp { 1019 fsl,pins = 1020 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */ 1021 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */ 1022 }; 1023 1024 pinctrl_i2c3_gpio: i2c3gpiogrp { 1025 fsl,pins = 1026 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */ 1027 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */ 1028 }; 1029 1030 /* Verdin I2C_1 */ 1031 pinctrl_i2c4: i2c4grp { 1032 fsl,pins = 1033 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */ 1034 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */ 1035 }; 1036 1037 pinctrl_i2c4_gpio: i2c4gpiogrp { 1038 fsl,pins = 1039 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */ 1040 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */ 1041 }; 1042 1043 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1044 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1045 fsl,pins = 1046 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */ 1047 }; 1048 1049 /* Verdin I2S_2_D_OUT shared with SAI5 */ 1050 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1051 fsl,pins = 1052 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */ 1053 }; 1054 1055 pinctrl_pcie0: pcie0grp { 1056 fsl,pins = 1057 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */ 1058 /* PMIC_EN_PCIe_CLK, unused */ 1059 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>; 1060 }; 1061 1062 pinctrl_pmic: pmicirqgrp { 1063 fsl,pins = 1064 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */ 1065 }; 1066 1067 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ 1068 pinctrl_pwm_1: pwm1grp { 1069 fsl,pins = 1070 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */ 1071 }; 1072 1073 pinctrl_pwm_2: pwm2grp { 1074 fsl,pins = 1075 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */ 1076 }; 1077 1078 pinctrl_pwm_3: pwm3grp { 1079 fsl,pins = 1080 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */ 1081 }; 1082 1083 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ 1084 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { 1085 fsl,pins = 1086 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */ 1087 }; 1088 1089 pinctrl_reg_eth: regethgrp { 1090 fsl,pins = 1091 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */ 1092 }; 1093 1094 pinctrl_reg_usb1_en: regusb1engrp { 1095 fsl,pins = 1096 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */ 1097 }; 1098 1099 pinctrl_reg_usb2_en: regusb2engrp { 1100 fsl,pins = 1101 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */ 1102 }; 1103 1104 pinctrl_sai2: sai2grp { 1105 fsl,pins = 1106 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */ 1107 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */ 1108 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */ 1109 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */ 1110 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */ 1111 }; 1112 1113 pinctrl_sai5: sai5grp { 1114 fsl,pins = 1115 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */ 1116 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */ 1117 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */ 1118 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */ 1119 }; 1120 1121 /* control signal for optional ATTPM20P or SE050 */ 1122 pinctrl_pmic_tpm_ena: pmictpmenagrp { 1123 fsl,pins = 1124 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */ 1125 }; 1126 1127 pinctrl_tsp: tspgrp { 1128 fsl,pins = 1129 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */ 1130 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */ 1131 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */ 1132 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */ 1133 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */ 1134 }; 1135 1136 pinctrl_uart1: uart1grp { 1137 fsl,pins = 1138 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */ 1139 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */ 1140 }; 1141 1142 pinctrl_uart2: uart2grp { 1143 fsl,pins = 1144 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */ 1145 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */ 1146 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */ 1147 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */ 1148 }; 1149 1150 pinctrl_uart3: uart3grp { 1151 fsl,pins = 1152 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */ 1153 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */ 1154 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */ 1155 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */ 1156 }; 1157 1158 pinctrl_uart4: uart4grp { 1159 fsl,pins = 1160 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */ 1161 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */ 1162 }; 1163 1164 pinctrl_usdhc1: usdhc1grp { 1165 fsl,pins = 1166 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>, 1167 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>, 1168 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>, 1169 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>, 1170 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>, 1171 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>, 1172 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>, 1173 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>, 1174 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>, 1175 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>, 1176 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1177 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>; 1178 }; 1179 1180 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1181 fsl,pins = 1182 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>, 1183 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>, 1184 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>, 1185 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>, 1186 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>, 1187 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>, 1188 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>, 1189 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>, 1190 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>, 1191 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>, 1192 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1193 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>; 1194 }; 1195 1196 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1197 fsl,pins = 1198 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>, 1199 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>, 1200 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>, 1201 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>, 1202 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>, 1203 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>, 1204 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>, 1205 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>, 1206 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>, 1207 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>, 1208 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1209 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>; 1210 }; 1211 1212 pinctrl_usdhc2_cd: usdhc2cdgrp { 1213 fsl,pins = 1214 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */ 1215 }; 1216 1217 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1218 fsl,pins = 1219 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */ 1220 }; 1221 1222 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1223 fsl,pins = 1224 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */ 1225 }; 1226 1227 pinctrl_usdhc2_vsel: usdhc2vselgrp { 1228 fsl,pins = 1229 <MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x10>; /* PMIC_USDHC_VSELECT */ 1230 }; 1231 1232 /* 1233 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the 1234 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. 1235 */ 1236 pinctrl_usdhc2: usdhc2grp { 1237 fsl,pins = 1238 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ 1239 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ 1240 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ 1241 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */ 1242 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */ 1243 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */ 1244 }; 1245 1246 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1247 fsl,pins = 1248 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, 1249 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, 1250 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, 1251 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>, 1252 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>, 1253 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>; 1254 }; 1255 1256 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1257 fsl,pins = 1258 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, 1259 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, 1260 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, 1261 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>, 1262 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>, 1263 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>; 1264 }; 1265 1266 /* Avoid backfeeding with removed card power */ 1267 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1268 fsl,pins = 1269 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>, 1270 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>, 1271 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>, 1272 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>, 1273 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>, 1274 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>; 1275 }; 1276 1277 /* 1278 * On-module Wi-Fi/BT or type specific SDHC interface 1279 * (e.g. on X52 extension slot of Verdin Development Board) 1280 */ 1281 pinctrl_usdhc3: usdhc3grp { 1282 fsl,pins = 1283 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>, 1284 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>, 1285 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>, 1286 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>, 1287 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>, 1288 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>; 1289 }; 1290 1291 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1292 fsl,pins = 1293 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>, 1294 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>, 1295 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>, 1296 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>, 1297 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>, 1298 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>; 1299 }; 1300 1301 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1302 fsl,pins = 1303 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>, 1304 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>, 1305 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>, 1306 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>, 1307 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>, 1308 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>; 1309 }; 1310 1311 pinctrl_wdog: wdoggrp { 1312 fsl,pins = 1313 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */ 1314 }; 1315 1316 pinctrl_wifi_ctrl: wifictrlgrp { 1317 fsl,pins = 1318 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */ 1319 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */ 1320 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */ 1321 }; 1322 1323 pinctrl_wifi_i2s: bti2sgrp { 1324 fsl,pins = 1325 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */ 1326 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */ 1327 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */ 1328 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */ 1329 }; 1330 1331 pinctrl_wifi_pwr_en: wifipwrengrp { 1332 fsl,pins = 1333 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */ 1334 }; 1335}; 1336