1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 11#include <dt-bindings/clock/qcom,sm8450-videocc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/phy/phy-qcom-qmp.h> 16#include <dt-bindings/power/qcom,rpmhpd.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/interconnect/qcom,icc.h> 19#include <dt-bindings/interconnect/qcom,sm8450.h> 20#include <dt-bindings/soc/qcom,gpr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <76800000>; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32764>; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 CPU0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "qcom,kryo780"; 54 reg = <0x0 0x0>; 55 enable-method = "psci"; 56 next-level-cache = <&L2_0>; 57 power-domains = <&CPU_PD0>; 58 power-domain-names = "psci"; 59 qcom,freq-domain = <&cpufreq_hw 0>; 60 #cooling-cells = <2>; 61 clocks = <&cpufreq_hw 0>; 62 L2_0: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 cache-unified; 66 next-level-cache = <&L3_0>; 67 L3_0: l3-cache { 68 compatible = "cache"; 69 cache-level = <3>; 70 cache-unified; 71 }; 72 }; 73 }; 74 75 CPU1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "qcom,kryo780"; 78 reg = <0x0 0x100>; 79 enable-method = "psci"; 80 next-level-cache = <&L2_100>; 81 power-domains = <&CPU_PD1>; 82 power-domain-names = "psci"; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 #cooling-cells = <2>; 85 clocks = <&cpufreq_hw 0>; 86 L2_100: l2-cache { 87 compatible = "cache"; 88 cache-level = <2>; 89 cache-unified; 90 next-level-cache = <&L3_0>; 91 }; 92 }; 93 94 CPU2: cpu@200 { 95 device_type = "cpu"; 96 compatible = "qcom,kryo780"; 97 reg = <0x0 0x200>; 98 enable-method = "psci"; 99 next-level-cache = <&L2_200>; 100 power-domains = <&CPU_PD2>; 101 power-domain-names = "psci"; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 #cooling-cells = <2>; 104 clocks = <&cpufreq_hw 0>; 105 L2_200: l2-cache { 106 compatible = "cache"; 107 cache-level = <2>; 108 cache-unified; 109 next-level-cache = <&L3_0>; 110 }; 111 }; 112 113 CPU3: cpu@300 { 114 device_type = "cpu"; 115 compatible = "qcom,kryo780"; 116 reg = <0x0 0x300>; 117 enable-method = "psci"; 118 next-level-cache = <&L2_300>; 119 power-domains = <&CPU_PD3>; 120 power-domain-names = "psci"; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 #cooling-cells = <2>; 123 clocks = <&cpufreq_hw 0>; 124 L2_300: l2-cache { 125 compatible = "cache"; 126 cache-level = <2>; 127 cache-unified; 128 next-level-cache = <&L3_0>; 129 }; 130 }; 131 132 CPU4: cpu@400 { 133 device_type = "cpu"; 134 compatible = "qcom,kryo780"; 135 reg = <0x0 0x400>; 136 enable-method = "psci"; 137 next-level-cache = <&L2_400>; 138 power-domains = <&CPU_PD4>; 139 power-domain-names = "psci"; 140 qcom,freq-domain = <&cpufreq_hw 1>; 141 #cooling-cells = <2>; 142 clocks = <&cpufreq_hw 1>; 143 L2_400: l2-cache { 144 compatible = "cache"; 145 cache-level = <2>; 146 cache-unified; 147 next-level-cache = <&L3_0>; 148 }; 149 }; 150 151 CPU5: cpu@500 { 152 device_type = "cpu"; 153 compatible = "qcom,kryo780"; 154 reg = <0x0 0x500>; 155 enable-method = "psci"; 156 next-level-cache = <&L2_500>; 157 power-domains = <&CPU_PD5>; 158 power-domain-names = "psci"; 159 qcom,freq-domain = <&cpufreq_hw 1>; 160 #cooling-cells = <2>; 161 clocks = <&cpufreq_hw 1>; 162 L2_500: l2-cache { 163 compatible = "cache"; 164 cache-level = <2>; 165 cache-unified; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 CPU6: cpu@600 { 171 device_type = "cpu"; 172 compatible = "qcom,kryo780"; 173 reg = <0x0 0x600>; 174 enable-method = "psci"; 175 next-level-cache = <&L2_600>; 176 power-domains = <&CPU_PD6>; 177 power-domain-names = "psci"; 178 qcom,freq-domain = <&cpufreq_hw 1>; 179 #cooling-cells = <2>; 180 clocks = <&cpufreq_hw 1>; 181 L2_600: l2-cache { 182 compatible = "cache"; 183 cache-level = <2>; 184 cache-unified; 185 next-level-cache = <&L3_0>; 186 }; 187 }; 188 189 CPU7: cpu@700 { 190 device_type = "cpu"; 191 compatible = "qcom,kryo780"; 192 reg = <0x0 0x700>; 193 enable-method = "psci"; 194 next-level-cache = <&L2_700>; 195 power-domains = <&CPU_PD7>; 196 power-domain-names = "psci"; 197 qcom,freq-domain = <&cpufreq_hw 2>; 198 #cooling-cells = <2>; 199 clocks = <&cpufreq_hw 2>; 200 L2_700: l2-cache { 201 compatible = "cache"; 202 cache-level = <2>; 203 cache-unified; 204 next-level-cache = <&L3_0>; 205 }; 206 }; 207 208 cpu-map { 209 cluster0 { 210 core0 { 211 cpu = <&CPU0>; 212 }; 213 214 core1 { 215 cpu = <&CPU1>; 216 }; 217 218 core2 { 219 cpu = <&CPU2>; 220 }; 221 222 core3 { 223 cpu = <&CPU3>; 224 }; 225 226 core4 { 227 cpu = <&CPU4>; 228 }; 229 230 core5 { 231 cpu = <&CPU5>; 232 }; 233 234 core6 { 235 cpu = <&CPU6>; 236 }; 237 238 core7 { 239 cpu = <&CPU7>; 240 }; 241 }; 242 }; 243 244 idle-states { 245 entry-method = "psci"; 246 247 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 248 compatible = "arm,idle-state"; 249 idle-state-name = "silver-rail-power-collapse"; 250 arm,psci-suspend-param = <0x40000004>; 251 entry-latency-us = <800>; 252 exit-latency-us = <750>; 253 min-residency-us = <4090>; 254 local-timer-stop; 255 }; 256 257 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "gold-rail-power-collapse"; 260 arm,psci-suspend-param = <0x40000004>; 261 entry-latency-us = <600>; 262 exit-latency-us = <1550>; 263 min-residency-us = <4791>; 264 local-timer-stop; 265 }; 266 }; 267 268 domain-idle-states { 269 CLUSTER_SLEEP_0: cluster-sleep-0 { 270 compatible = "domain-idle-state"; 271 arm,psci-suspend-param = <0x41000044>; 272 entry-latency-us = <1050>; 273 exit-latency-us = <2500>; 274 min-residency-us = <5309>; 275 }; 276 277 CLUSTER_SLEEP_1: cluster-sleep-1 { 278 compatible = "domain-idle-state"; 279 arm,psci-suspend-param = <0x4100c344>; 280 entry-latency-us = <2700>; 281 exit-latency-us = <3500>; 282 min-residency-us = <13959>; 283 }; 284 }; 285 }; 286 287 firmware { 288 scm: scm { 289 compatible = "qcom,scm-sm8450", "qcom,scm"; 290 qcom,dload-mode = <&tcsr 0x13000>; 291 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 292 #reset-cells = <1>; 293 }; 294 }; 295 296 clk_virt: interconnect-0 { 297 compatible = "qcom,sm8450-clk-virt"; 298 #interconnect-cells = <2>; 299 qcom,bcm-voters = <&apps_bcm_voter>; 300 }; 301 302 mc_virt: interconnect-1 { 303 compatible = "qcom,sm8450-mc-virt"; 304 #interconnect-cells = <2>; 305 qcom,bcm-voters = <&apps_bcm_voter>; 306 }; 307 308 memory@a0000000 { 309 device_type = "memory"; 310 /* We expect the bootloader to fill in the size */ 311 reg = <0x0 0xa0000000 0x0 0x0>; 312 }; 313 314 pmu { 315 compatible = "arm,armv8-pmuv3"; 316 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 317 }; 318 319 psci { 320 compatible = "arm,psci-1.0"; 321 method = "smc"; 322 323 CPU_PD0: power-domain-cpu0 { 324 #power-domain-cells = <0>; 325 power-domains = <&CLUSTER_PD>; 326 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 327 }; 328 329 CPU_PD1: power-domain-cpu1 { 330 #power-domain-cells = <0>; 331 power-domains = <&CLUSTER_PD>; 332 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 333 }; 334 335 CPU_PD2: power-domain-cpu2 { 336 #power-domain-cells = <0>; 337 power-domains = <&CLUSTER_PD>; 338 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 339 }; 340 341 CPU_PD3: power-domain-cpu3 { 342 #power-domain-cells = <0>; 343 power-domains = <&CLUSTER_PD>; 344 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 345 }; 346 347 CPU_PD4: power-domain-cpu4 { 348 #power-domain-cells = <0>; 349 power-domains = <&CLUSTER_PD>; 350 domain-idle-states = <&BIG_CPU_SLEEP_0>; 351 }; 352 353 CPU_PD5: power-domain-cpu5 { 354 #power-domain-cells = <0>; 355 power-domains = <&CLUSTER_PD>; 356 domain-idle-states = <&BIG_CPU_SLEEP_0>; 357 }; 358 359 CPU_PD6: power-domain-cpu6 { 360 #power-domain-cells = <0>; 361 power-domains = <&CLUSTER_PD>; 362 domain-idle-states = <&BIG_CPU_SLEEP_0>; 363 }; 364 365 CPU_PD7: power-domain-cpu7 { 366 #power-domain-cells = <0>; 367 power-domains = <&CLUSTER_PD>; 368 domain-idle-states = <&BIG_CPU_SLEEP_0>; 369 }; 370 371 CLUSTER_PD: power-domain-cpu-cluster0 { 372 #power-domain-cells = <0>; 373 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 374 }; 375 }; 376 377 qup_opp_table_100mhz: opp-table-qup { 378 compatible = "operating-points-v2"; 379 380 opp-50000000 { 381 opp-hz = /bits/ 64 <50000000>; 382 required-opps = <&rpmhpd_opp_min_svs>; 383 }; 384 385 opp-75000000 { 386 opp-hz = /bits/ 64 <75000000>; 387 required-opps = <&rpmhpd_opp_low_svs>; 388 }; 389 390 opp-100000000 { 391 opp-hz = /bits/ 64 <100000000>; 392 required-opps = <&rpmhpd_opp_svs>; 393 }; 394 }; 395 396 reserved_memory: reserved-memory { 397 #address-cells = <2>; 398 #size-cells = <2>; 399 ranges; 400 401 hyp_mem: memory@80000000 { 402 reg = <0x0 0x80000000 0x0 0x600000>; 403 no-map; 404 }; 405 406 xbl_dt_log_mem: memory@80600000 { 407 reg = <0x0 0x80600000 0x0 0x40000>; 408 no-map; 409 }; 410 411 xbl_ramdump_mem: memory@80640000 { 412 reg = <0x0 0x80640000 0x0 0x180000>; 413 no-map; 414 }; 415 416 xbl_sc_mem: memory@807c0000 { 417 reg = <0x0 0x807c0000 0x0 0x40000>; 418 no-map; 419 }; 420 421 aop_image_mem: memory@80800000 { 422 reg = <0x0 0x80800000 0x0 0x60000>; 423 no-map; 424 }; 425 426 aop_cmd_db_mem: memory@80860000 { 427 compatible = "qcom,cmd-db"; 428 reg = <0x0 0x80860000 0x0 0x20000>; 429 no-map; 430 }; 431 432 aop_config_mem: memory@80880000 { 433 reg = <0x0 0x80880000 0x0 0x20000>; 434 no-map; 435 }; 436 437 tme_crash_dump_mem: memory@808a0000 { 438 reg = <0x0 0x808a0000 0x0 0x40000>; 439 no-map; 440 }; 441 442 tme_log_mem: memory@808e0000 { 443 reg = <0x0 0x808e0000 0x0 0x4000>; 444 no-map; 445 }; 446 447 uefi_log_mem: memory@808e4000 { 448 reg = <0x0 0x808e4000 0x0 0x10000>; 449 no-map; 450 }; 451 452 /* secdata region can be reused by apps */ 453 smem: memory@80900000 { 454 compatible = "qcom,smem"; 455 reg = <0x0 0x80900000 0x0 0x200000>; 456 hwlocks = <&tcsr_mutex 3>; 457 no-map; 458 }; 459 460 cpucp_fw_mem: memory@80b00000 { 461 reg = <0x0 0x80b00000 0x0 0x100000>; 462 no-map; 463 }; 464 465 cdsp_secure_heap: memory@80c00000 { 466 reg = <0x0 0x80c00000 0x0 0x4600000>; 467 no-map; 468 }; 469 470 video_mem: memory@85700000 { 471 reg = <0x0 0x85700000 0x0 0x700000>; 472 no-map; 473 }; 474 475 adsp_mem: memory@85e00000 { 476 reg = <0x0 0x85e00000 0x0 0x2100000>; 477 no-map; 478 }; 479 480 slpi_mem: memory@88000000 { 481 reg = <0x0 0x88000000 0x0 0x1900000>; 482 no-map; 483 }; 484 485 cdsp_mem: memory@89900000 { 486 reg = <0x0 0x89900000 0x0 0x2000000>; 487 no-map; 488 }; 489 490 ipa_fw_mem: memory@8b900000 { 491 reg = <0x0 0x8b900000 0x0 0x10000>; 492 no-map; 493 }; 494 495 ipa_gsi_mem: memory@8b910000 { 496 reg = <0x0 0x8b910000 0x0 0xa000>; 497 no-map; 498 }; 499 500 gpu_micro_code_mem: memory@8b91a000 { 501 reg = <0x0 0x8b91a000 0x0 0x2000>; 502 no-map; 503 }; 504 505 spss_region_mem: memory@8ba00000 { 506 reg = <0x0 0x8ba00000 0x0 0x180000>; 507 no-map; 508 }; 509 510 /* First part of the "SPU secure shared memory" region */ 511 spu_tz_shared_mem: memory@8bb80000 { 512 reg = <0x0 0x8bb80000 0x0 0x60000>; 513 no-map; 514 }; 515 516 /* Second part of the "SPU secure shared memory" region */ 517 spu_modem_shared_mem: memory@8bbe0000 { 518 reg = <0x0 0x8bbe0000 0x0 0x20000>; 519 no-map; 520 }; 521 522 mpss_mem: memory@8bc00000 { 523 reg = <0x0 0x8bc00000 0x0 0x13200000>; 524 no-map; 525 }; 526 527 cvp_mem: memory@9ee00000 { 528 reg = <0x0 0x9ee00000 0x0 0x700000>; 529 no-map; 530 }; 531 532 camera_mem: memory@9f500000 { 533 reg = <0x0 0x9f500000 0x0 0x800000>; 534 no-map; 535 }; 536 537 rmtfs_mem: memory@9fd00000 { 538 compatible = "qcom,rmtfs-mem"; 539 reg = <0x0 0x9fd00000 0x0 0x280000>; 540 no-map; 541 542 qcom,client-id = <1>; 543 qcom,vmid = <15>; 544 }; 545 546 xbl_sc_mem2: memory@a6e00000 { 547 reg = <0x0 0xa6e00000 0x0 0x40000>; 548 no-map; 549 }; 550 551 global_sync_mem: memory@a6f00000 { 552 reg = <0x0 0xa6f00000 0x0 0x100000>; 553 no-map; 554 }; 555 556 /* uefi region can be reused by APPS */ 557 558 /* Linux kernel image is loaded at 0xa0000000 */ 559 560 oem_vm_mem: memory@bb000000 { 561 reg = <0x0 0xbb000000 0x0 0x5000000>; 562 no-map; 563 }; 564 565 mte_mem: memory@c0000000 { 566 reg = <0x0 0xc0000000 0x0 0x20000000>; 567 no-map; 568 }; 569 570 qheebsp_reserved_mem: memory@e0000000 { 571 reg = <0x0 0xe0000000 0x0 0x600000>; 572 no-map; 573 }; 574 575 cpusys_vm_mem: memory@e0600000 { 576 reg = <0x0 0xe0600000 0x0 0x400000>; 577 no-map; 578 }; 579 580 hyp_reserved_mem: memory@e0a00000 { 581 reg = <0x0 0xe0a00000 0x0 0x100000>; 582 no-map; 583 }; 584 585 trust_ui_vm_mem: memory@e0b00000 { 586 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 587 no-map; 588 }; 589 590 trust_ui_vm_qrtr: memory@e55f3000 { 591 reg = <0x0 0xe55f3000 0x0 0x9000>; 592 no-map; 593 }; 594 595 trust_ui_vm_vblk0_ring: memory@e55fc000 { 596 reg = <0x0 0xe55fc000 0x0 0x4000>; 597 no-map; 598 }; 599 600 trust_ui_vm_swiotlb: memory@e5600000 { 601 reg = <0x0 0xe5600000 0x0 0x100000>; 602 no-map; 603 }; 604 605 tz_stat_mem: memory@e8800000 { 606 reg = <0x0 0xe8800000 0x0 0x100000>; 607 no-map; 608 }; 609 610 tags_mem: memory@e8900000 { 611 reg = <0x0 0xe8900000 0x0 0x1200000>; 612 no-map; 613 }; 614 615 qtee_mem: memory@e9b00000 { 616 reg = <0x0 0xe9b00000 0x0 0x500000>; 617 no-map; 618 }; 619 620 trusted_apps_mem: memory@ea000000 { 621 reg = <0x0 0xea000000 0x0 0x3900000>; 622 no-map; 623 }; 624 625 trusted_apps_ext_mem: memory@ed900000 { 626 reg = <0x0 0xed900000 0x0 0x3b00000>; 627 no-map; 628 }; 629 }; 630 631 smp2p-adsp { 632 compatible = "qcom,smp2p"; 633 qcom,smem = <443>, <429>; 634 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 635 IPCC_MPROC_SIGNAL_SMP2P 636 IRQ_TYPE_EDGE_RISING>; 637 mboxes = <&ipcc IPCC_CLIENT_LPASS 638 IPCC_MPROC_SIGNAL_SMP2P>; 639 640 qcom,local-pid = <0>; 641 qcom,remote-pid = <2>; 642 643 smp2p_adsp_out: master-kernel { 644 qcom,entry-name = "master-kernel"; 645 #qcom,smem-state-cells = <1>; 646 }; 647 648 smp2p_adsp_in: slave-kernel { 649 qcom,entry-name = "slave-kernel"; 650 interrupt-controller; 651 #interrupt-cells = <2>; 652 }; 653 }; 654 655 smp2p-cdsp { 656 compatible = "qcom,smp2p"; 657 qcom,smem = <94>, <432>; 658 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 659 IPCC_MPROC_SIGNAL_SMP2P 660 IRQ_TYPE_EDGE_RISING>; 661 mboxes = <&ipcc IPCC_CLIENT_CDSP 662 IPCC_MPROC_SIGNAL_SMP2P>; 663 664 qcom,local-pid = <0>; 665 qcom,remote-pid = <5>; 666 667 smp2p_cdsp_out: master-kernel { 668 qcom,entry-name = "master-kernel"; 669 #qcom,smem-state-cells = <1>; 670 }; 671 672 smp2p_cdsp_in: slave-kernel { 673 qcom,entry-name = "slave-kernel"; 674 interrupt-controller; 675 #interrupt-cells = <2>; 676 }; 677 }; 678 679 smp2p-modem { 680 compatible = "qcom,smp2p"; 681 qcom,smem = <435>, <428>; 682 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 683 IPCC_MPROC_SIGNAL_SMP2P 684 IRQ_TYPE_EDGE_RISING>; 685 mboxes = <&ipcc IPCC_CLIENT_MPSS 686 IPCC_MPROC_SIGNAL_SMP2P>; 687 688 qcom,local-pid = <0>; 689 qcom,remote-pid = <1>; 690 691 smp2p_modem_out: master-kernel { 692 qcom,entry-name = "master-kernel"; 693 #qcom,smem-state-cells = <1>; 694 }; 695 696 smp2p_modem_in: slave-kernel { 697 qcom,entry-name = "slave-kernel"; 698 interrupt-controller; 699 #interrupt-cells = <2>; 700 }; 701 702 ipa_smp2p_out: ipa-ap-to-modem { 703 qcom,entry-name = "ipa"; 704 #qcom,smem-state-cells = <1>; 705 }; 706 707 ipa_smp2p_in: ipa-modem-to-ap { 708 qcom,entry-name = "ipa"; 709 interrupt-controller; 710 #interrupt-cells = <2>; 711 }; 712 }; 713 714 smp2p-slpi { 715 compatible = "qcom,smp2p"; 716 qcom,smem = <481>, <430>; 717 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 718 IPCC_MPROC_SIGNAL_SMP2P 719 IRQ_TYPE_EDGE_RISING>; 720 mboxes = <&ipcc IPCC_CLIENT_SLPI 721 IPCC_MPROC_SIGNAL_SMP2P>; 722 723 qcom,local-pid = <0>; 724 qcom,remote-pid = <3>; 725 726 smp2p_slpi_out: master-kernel { 727 qcom,entry-name = "master-kernel"; 728 #qcom,smem-state-cells = <1>; 729 }; 730 731 smp2p_slpi_in: slave-kernel { 732 qcom,entry-name = "slave-kernel"; 733 interrupt-controller; 734 #interrupt-cells = <2>; 735 }; 736 }; 737 738 soc: soc@0 { 739 #address-cells = <2>; 740 #size-cells = <2>; 741 ranges = <0 0 0 0 0x10 0>; 742 dma-ranges = <0 0 0 0 0x10 0>; 743 compatible = "simple-bus"; 744 745 gcc: clock-controller@100000 { 746 compatible = "qcom,gcc-sm8450"; 747 reg = <0x0 0x00100000 0x0 0x1f4200>; 748 #clock-cells = <1>; 749 #reset-cells = <1>; 750 #power-domain-cells = <1>; 751 clocks = <&rpmhcc RPMH_CXO_CLK>, 752 <&sleep_clk>, 753 <&pcie0_lane>, 754 <&pcie1_lane>, 755 <0>, 756 <&ufs_mem_phy_lanes 0>, 757 <&ufs_mem_phy_lanes 1>, 758 <&ufs_mem_phy_lanes 2>, 759 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 760 clock-names = "bi_tcxo", 761 "sleep_clk", 762 "pcie_0_pipe_clk", 763 "pcie_1_pipe_clk", 764 "pcie_1_phy_aux_clk", 765 "ufs_phy_rx_symbol_0_clk", 766 "ufs_phy_rx_symbol_1_clk", 767 "ufs_phy_tx_symbol_0_clk", 768 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 769 }; 770 771 gpi_dma2: dma-controller@800000 { 772 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 773 #dma-cells = <3>; 774 reg = <0 0x00800000 0 0x60000>; 775 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 787 dma-channels = <12>; 788 dma-channel-mask = <0x7e>; 789 iommus = <&apps_smmu 0x496 0x0>; 790 status = "disabled"; 791 }; 792 793 qupv3_id_2: geniqup@8c0000 { 794 compatible = "qcom,geni-se-qup"; 795 reg = <0x0 0x008c0000 0x0 0x2000>; 796 clock-names = "m-ahb", "s-ahb"; 797 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 798 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 799 iommus = <&apps_smmu 0x483 0x0>; 800 #address-cells = <2>; 801 #size-cells = <2>; 802 ranges; 803 status = "disabled"; 804 805 i2c15: i2c@880000 { 806 compatible = "qcom,geni-i2c"; 807 reg = <0x0 0x00880000 0x0 0x4000>; 808 clock-names = "se"; 809 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 810 pinctrl-names = "default"; 811 pinctrl-0 = <&qup_i2c15_data_clk>; 812 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 816 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 817 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 818 interconnect-names = "qup-core", "qup-config", "qup-memory"; 819 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 820 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 821 dma-names = "tx", "rx"; 822 status = "disabled"; 823 }; 824 825 spi15: spi@880000 { 826 compatible = "qcom,geni-spi"; 827 reg = <0x0 0x00880000 0x0 0x4000>; 828 clock-names = "se"; 829 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 830 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 831 pinctrl-names = "default"; 832 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 833 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 834 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 835 interconnect-names = "qup-core", "qup-config"; 836 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 837 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 838 dma-names = "tx", "rx"; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 status = "disabled"; 842 }; 843 844 i2c16: i2c@884000 { 845 compatible = "qcom,geni-i2c"; 846 reg = <0x0 0x00884000 0x0 0x4000>; 847 clock-names = "se"; 848 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 849 pinctrl-names = "default"; 850 pinctrl-0 = <&qup_i2c16_data_clk>; 851 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 855 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 856 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 857 interconnect-names = "qup-core", "qup-config", "qup-memory"; 858 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 859 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 860 dma-names = "tx", "rx"; 861 status = "disabled"; 862 }; 863 864 spi16: spi@884000 { 865 compatible = "qcom,geni-spi"; 866 reg = <0x0 0x00884000 0x0 0x4000>; 867 clock-names = "se"; 868 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 869 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 870 pinctrl-names = "default"; 871 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 872 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 873 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 874 interconnect-names = "qup-core", "qup-config"; 875 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 876 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 877 dma-names = "tx", "rx"; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 status = "disabled"; 881 }; 882 883 i2c17: i2c@888000 { 884 compatible = "qcom,geni-i2c"; 885 reg = <0x0 0x00888000 0x0 0x4000>; 886 clock-names = "se"; 887 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 888 pinctrl-names = "default"; 889 pinctrl-0 = <&qup_i2c17_data_clk>; 890 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 894 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 895 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 896 interconnect-names = "qup-core", "qup-config", "qup-memory"; 897 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 898 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 899 dma-names = "tx", "rx"; 900 status = "disabled"; 901 }; 902 903 spi17: spi@888000 { 904 compatible = "qcom,geni-spi"; 905 reg = <0x0 0x00888000 0x0 0x4000>; 906 clock-names = "se"; 907 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 908 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 909 pinctrl-names = "default"; 910 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 911 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 912 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 913 interconnect-names = "qup-core", "qup-config"; 914 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 915 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 916 dma-names = "tx", "rx"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 status = "disabled"; 920 }; 921 922 i2c18: i2c@88c000 { 923 compatible = "qcom,geni-i2c"; 924 reg = <0x0 0x0088c000 0x0 0x4000>; 925 clock-names = "se"; 926 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 927 pinctrl-names = "default"; 928 pinctrl-0 = <&qup_i2c18_data_clk>; 929 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 933 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 934 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 935 interconnect-names = "qup-core", "qup-config", "qup-memory"; 936 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 937 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 938 dma-names = "tx", "rx"; 939 status = "disabled"; 940 }; 941 942 spi18: spi@88c000 { 943 compatible = "qcom,geni-spi"; 944 reg = <0 0x0088c000 0 0x4000>; 945 clock-names = "se"; 946 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 947 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 951 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 952 interconnect-names = "qup-core", "qup-config"; 953 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 954 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 955 dma-names = "tx", "rx"; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 status = "disabled"; 959 }; 960 961 i2c19: i2c@890000 { 962 compatible = "qcom,geni-i2c"; 963 reg = <0x0 0x00890000 0x0 0x4000>; 964 clock-names = "se"; 965 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&qup_i2c19_data_clk>; 968 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 972 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 973 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 974 interconnect-names = "qup-core", "qup-config", "qup-memory"; 975 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 976 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 977 dma-names = "tx", "rx"; 978 status = "disabled"; 979 }; 980 981 spi19: spi@890000 { 982 compatible = "qcom,geni-spi"; 983 reg = <0 0x00890000 0 0x4000>; 984 clock-names = "se"; 985 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 986 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 987 pinctrl-names = "default"; 988 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 989 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 990 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 991 interconnect-names = "qup-core", "qup-config"; 992 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 993 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 994 dma-names = "tx", "rx"; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 status = "disabled"; 998 }; 999 1000 i2c20: i2c@894000 { 1001 compatible = "qcom,geni-i2c"; 1002 reg = <0x0 0x00894000 0x0 0x4000>; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_i2c20_data_clk>; 1007 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1011 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1012 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1013 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1014 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1015 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1016 dma-names = "tx", "rx"; 1017 status = "disabled"; 1018 }; 1019 1020 uart20: serial@894000 { 1021 compatible = "qcom,geni-uart"; 1022 reg = <0 0x00894000 0 0x4000>; 1023 clock-names = "se"; 1024 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&qup_uart20_default>; 1027 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1029 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1030 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1031 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1032 interconnect-names = "qup-core", 1033 "qup-config"; 1034 status = "disabled"; 1035 }; 1036 1037 spi20: spi@894000 { 1038 compatible = "qcom,geni-spi"; 1039 reg = <0 0x00894000 0 0x4000>; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1042 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1046 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1047 interconnect-names = "qup-core", "qup-config"; 1048 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1049 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1050 dma-names = "tx", "rx"; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 status = "disabled"; 1054 }; 1055 1056 i2c21: i2c@898000 { 1057 compatible = "qcom,geni-i2c"; 1058 reg = <0x0 0x00898000 0x0 0x4000>; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&qup_i2c21_data_clk>; 1063 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1067 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1068 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1069 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1070 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1071 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1072 dma-names = "tx", "rx"; 1073 status = "disabled"; 1074 }; 1075 1076 spi21: spi@898000 { 1077 compatible = "qcom,geni-spi"; 1078 reg = <0 0x00898000 0 0x4000>; 1079 clock-names = "se"; 1080 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1081 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1082 pinctrl-names = "default"; 1083 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1084 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1085 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1086 interconnect-names = "qup-core", "qup-config"; 1087 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1088 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1089 dma-names = "tx", "rx"; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 }; 1095 1096 gpi_dma0: dma-controller@900000 { 1097 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1098 #dma-cells = <3>; 1099 reg = <0 0x00900000 0 0x60000>; 1100 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1112 dma-channels = <12>; 1113 dma-channel-mask = <0x7e>; 1114 iommus = <&apps_smmu 0x5b6 0x0>; 1115 status = "disabled"; 1116 }; 1117 1118 qupv3_id_0: geniqup@9c0000 { 1119 compatible = "qcom,geni-se-qup"; 1120 reg = <0x0 0x009c0000 0x0 0x2000>; 1121 clock-names = "m-ahb", "s-ahb"; 1122 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1123 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1124 iommus = <&apps_smmu 0x5a3 0x0>; 1125 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1126 interconnect-names = "qup-core"; 1127 #address-cells = <2>; 1128 #size-cells = <2>; 1129 ranges; 1130 status = "disabled"; 1131 1132 i2c0: i2c@980000 { 1133 compatible = "qcom,geni-i2c"; 1134 reg = <0x0 0x00980000 0x0 0x4000>; 1135 clock-names = "se"; 1136 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1137 pinctrl-names = "default"; 1138 pinctrl-0 = <&qup_i2c0_data_clk>; 1139 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1143 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1144 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1145 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1146 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1147 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1148 dma-names = "tx", "rx"; 1149 status = "disabled"; 1150 }; 1151 1152 spi0: spi@980000 { 1153 compatible = "qcom,geni-spi"; 1154 reg = <0x0 0x00980000 0x0 0x4000>; 1155 clock-names = "se"; 1156 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1157 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1158 pinctrl-names = "default"; 1159 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1160 power-domains = <&rpmhpd RPMHPD_CX>; 1161 operating-points-v2 = <&qup_opp_table_100mhz>; 1162 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1163 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1164 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1165 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1166 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1167 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1168 dma-names = "tx", "rx"; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 status = "disabled"; 1172 }; 1173 1174 i2c1: i2c@984000 { 1175 compatible = "qcom,geni-i2c"; 1176 reg = <0x0 0x00984000 0x0 0x4000>; 1177 clock-names = "se"; 1178 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1179 pinctrl-names = "default"; 1180 pinctrl-0 = <&qup_i2c1_data_clk>; 1181 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1185 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1186 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1187 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1188 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1189 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1190 dma-names = "tx", "rx"; 1191 status = "disabled"; 1192 }; 1193 1194 spi1: spi@984000 { 1195 compatible = "qcom,geni-spi"; 1196 reg = <0x0 0x00984000 0x0 0x4000>; 1197 clock-names = "se"; 1198 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1199 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1200 pinctrl-names = "default"; 1201 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1202 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1203 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1204 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1205 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1206 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1207 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1208 dma-names = "tx", "rx"; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 status = "disabled"; 1212 }; 1213 1214 i2c2: i2c@988000 { 1215 compatible = "qcom,geni-i2c"; 1216 reg = <0x0 0x00988000 0x0 0x4000>; 1217 clock-names = "se"; 1218 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1219 pinctrl-names = "default"; 1220 pinctrl-0 = <&qup_i2c2_data_clk>; 1221 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1225 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1226 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1227 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1228 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1229 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1230 dma-names = "tx", "rx"; 1231 status = "disabled"; 1232 }; 1233 1234 spi2: spi@988000 { 1235 compatible = "qcom,geni-spi"; 1236 reg = <0x0 0x00988000 0x0 0x4000>; 1237 clock-names = "se"; 1238 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1239 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1240 pinctrl-names = "default"; 1241 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1243 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1244 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1245 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1246 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1247 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1248 dma-names = "tx", "rx"; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 status = "disabled"; 1252 }; 1253 1254 1255 i2c3: i2c@98c000 { 1256 compatible = "qcom,geni-i2c"; 1257 reg = <0x0 0x0098c000 0x0 0x4000>; 1258 clock-names = "se"; 1259 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&qup_i2c3_data_clk>; 1262 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1266 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1267 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1268 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1269 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1270 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1271 dma-names = "tx", "rx"; 1272 status = "disabled"; 1273 }; 1274 1275 spi3: spi@98c000 { 1276 compatible = "qcom,geni-spi"; 1277 reg = <0x0 0x0098c000 0x0 0x4000>; 1278 clock-names = "se"; 1279 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1280 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1281 pinctrl-names = "default"; 1282 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1283 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1284 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1285 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1286 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1287 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1288 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1289 dma-names = "tx", "rx"; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 status = "disabled"; 1293 }; 1294 1295 i2c4: i2c@990000 { 1296 compatible = "qcom,geni-i2c"; 1297 reg = <0x0 0x00990000 0x0 0x4000>; 1298 clock-names = "se"; 1299 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1300 pinctrl-names = "default"; 1301 pinctrl-0 = <&qup_i2c4_data_clk>; 1302 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1306 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1307 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1308 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1309 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1310 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1311 dma-names = "tx", "rx"; 1312 status = "disabled"; 1313 }; 1314 1315 spi4: spi@990000 { 1316 compatible = "qcom,geni-spi"; 1317 reg = <0x0 0x00990000 0x0 0x4000>; 1318 clock-names = "se"; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1320 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1323 power-domains = <&rpmhpd RPMHPD_CX>; 1324 operating-points-v2 = <&qup_opp_table_100mhz>; 1325 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1326 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1327 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1328 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1329 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1330 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1331 dma-names = "tx", "rx"; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 status = "disabled"; 1335 }; 1336 1337 i2c5: i2c@994000 { 1338 compatible = "qcom,geni-i2c"; 1339 reg = <0x0 0x00994000 0x0 0x4000>; 1340 clock-names = "se"; 1341 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_i2c5_data_clk>; 1344 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1348 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1349 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1350 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1351 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1352 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1353 dma-names = "tx", "rx"; 1354 status = "disabled"; 1355 }; 1356 1357 spi5: spi@994000 { 1358 compatible = "qcom,geni-spi"; 1359 reg = <0x0 0x00994000 0x0 0x4000>; 1360 clock-names = "se"; 1361 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1362 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1363 pinctrl-names = "default"; 1364 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1365 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1366 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1367 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1368 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1369 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1370 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1371 dma-names = "tx", "rx"; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 status = "disabled"; 1375 }; 1376 1377 1378 i2c6: i2c@998000 { 1379 compatible = "qcom,geni-i2c"; 1380 reg = <0x0 0x00998000 0x0 0x4000>; 1381 clock-names = "se"; 1382 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_i2c6_data_clk>; 1385 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1389 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1390 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1391 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1392 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1393 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1394 dma-names = "tx", "rx"; 1395 status = "disabled"; 1396 }; 1397 1398 spi6: spi@998000 { 1399 compatible = "qcom,geni-spi"; 1400 reg = <0x0 0x00998000 0x0 0x4000>; 1401 clock-names = "se"; 1402 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1403 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1404 pinctrl-names = "default"; 1405 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1406 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1407 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1408 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1409 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1410 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1411 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1412 dma-names = "tx", "rx"; 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 status = "disabled"; 1416 }; 1417 1418 uart7: serial@99c000 { 1419 compatible = "qcom,geni-debug-uart"; 1420 reg = <0 0x0099c000 0 0x4000>; 1421 clock-names = "se"; 1422 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1423 pinctrl-names = "default"; 1424 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1425 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1426 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1427 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1428 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1429 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1430 interconnect-names = "qup-core", 1431 "qup-config"; 1432 status = "disabled"; 1433 }; 1434 }; 1435 1436 gpi_dma1: dma-controller@a00000 { 1437 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1438 #dma-cells = <3>; 1439 reg = <0 0x00a00000 0 0x60000>; 1440 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1452 dma-channels = <12>; 1453 dma-channel-mask = <0x7e>; 1454 iommus = <&apps_smmu 0x56 0x0>; 1455 status = "disabled"; 1456 }; 1457 1458 qupv3_id_1: geniqup@ac0000 { 1459 compatible = "qcom,geni-se-qup"; 1460 reg = <0x0 0x00ac0000 0x0 0x6000>; 1461 clock-names = "m-ahb", "s-ahb"; 1462 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1463 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1464 iommus = <&apps_smmu 0x43 0x0>; 1465 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1466 interconnect-names = "qup-core"; 1467 #address-cells = <2>; 1468 #size-cells = <2>; 1469 ranges; 1470 status = "disabled"; 1471 1472 i2c8: i2c@a80000 { 1473 compatible = "qcom,geni-i2c"; 1474 reg = <0x0 0x00a80000 0x0 0x4000>; 1475 clock-names = "se"; 1476 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1477 pinctrl-names = "default"; 1478 pinctrl-0 = <&qup_i2c8_data_clk>; 1479 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1480 #address-cells = <1>; 1481 #size-cells = <0>; 1482 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1483 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1484 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1485 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1486 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1487 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1488 dma-names = "tx", "rx"; 1489 status = "disabled"; 1490 }; 1491 1492 spi8: spi@a80000 { 1493 compatible = "qcom,geni-spi"; 1494 reg = <0x0 0x00a80000 0x0 0x4000>; 1495 clock-names = "se"; 1496 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1497 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1498 pinctrl-names = "default"; 1499 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1500 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1501 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1502 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1503 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1504 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1505 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1506 dma-names = "tx", "rx"; 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 status = "disabled"; 1510 }; 1511 1512 i2c9: i2c@a84000 { 1513 compatible = "qcom,geni-i2c"; 1514 reg = <0x0 0x00a84000 0x0 0x4000>; 1515 clock-names = "se"; 1516 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1517 pinctrl-names = "default"; 1518 pinctrl-0 = <&qup_i2c9_data_clk>; 1519 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1523 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1524 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1525 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1526 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1527 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1528 dma-names = "tx", "rx"; 1529 status = "disabled"; 1530 }; 1531 1532 spi9: spi@a84000 { 1533 compatible = "qcom,geni-spi"; 1534 reg = <0x0 0x00a84000 0x0 0x4000>; 1535 clock-names = "se"; 1536 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1537 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1538 pinctrl-names = "default"; 1539 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1540 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1541 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1542 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1543 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1544 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1545 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1546 dma-names = "tx", "rx"; 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 status = "disabled"; 1550 }; 1551 1552 i2c10: i2c@a88000 { 1553 compatible = "qcom,geni-i2c"; 1554 reg = <0x0 0x00a88000 0x0 0x4000>; 1555 clock-names = "se"; 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1557 pinctrl-names = "default"; 1558 pinctrl-0 = <&qup_i2c10_data_clk>; 1559 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1560 #address-cells = <1>; 1561 #size-cells = <0>; 1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1563 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1564 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1565 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1566 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1567 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1568 dma-names = "tx", "rx"; 1569 status = "disabled"; 1570 }; 1571 1572 spi10: spi@a88000 { 1573 compatible = "qcom,geni-spi"; 1574 reg = <0x0 0x00a88000 0x0 0x4000>; 1575 clock-names = "se"; 1576 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1577 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1578 pinctrl-names = "default"; 1579 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1580 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1581 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1582 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1583 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1584 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1585 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1586 dma-names = "tx", "rx"; 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 status = "disabled"; 1590 }; 1591 1592 i2c11: i2c@a8c000 { 1593 compatible = "qcom,geni-i2c"; 1594 reg = <0x0 0x00a8c000 0x0 0x4000>; 1595 clock-names = "se"; 1596 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1597 pinctrl-names = "default"; 1598 pinctrl-0 = <&qup_i2c11_data_clk>; 1599 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1603 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1604 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1605 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1606 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1607 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1608 dma-names = "tx", "rx"; 1609 status = "disabled"; 1610 }; 1611 1612 spi11: spi@a8c000 { 1613 compatible = "qcom,geni-spi"; 1614 reg = <0x0 0x00a8c000 0x0 0x4000>; 1615 clock-names = "se"; 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1617 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1618 pinctrl-names = "default"; 1619 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1621 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1622 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1623 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1624 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1625 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1626 dma-names = "tx", "rx"; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 i2c12: i2c@a90000 { 1633 compatible = "qcom,geni-i2c"; 1634 reg = <0x0 0x00a90000 0x0 0x4000>; 1635 clock-names = "se"; 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1637 pinctrl-names = "default"; 1638 pinctrl-0 = <&qup_i2c12_data_clk>; 1639 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1643 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1644 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1645 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1646 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1647 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1648 dma-names = "tx", "rx"; 1649 status = "disabled"; 1650 }; 1651 1652 spi12: spi@a90000 { 1653 compatible = "qcom,geni-spi"; 1654 reg = <0x0 0x00a90000 0x0 0x4000>; 1655 clock-names = "se"; 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1657 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1658 pinctrl-names = "default"; 1659 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1660 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1661 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1662 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1663 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1664 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1665 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1666 dma-names = "tx", "rx"; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 status = "disabled"; 1670 }; 1671 1672 i2c13: i2c@a94000 { 1673 compatible = "qcom,geni-i2c"; 1674 reg = <0 0x00a94000 0 0x4000>; 1675 clock-names = "se"; 1676 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1677 pinctrl-names = "default"; 1678 pinctrl-0 = <&qup_i2c13_data_clk>; 1679 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1681 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1682 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1683 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1684 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1685 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1686 dma-names = "tx", "rx"; 1687 #address-cells = <1>; 1688 #size-cells = <0>; 1689 status = "disabled"; 1690 }; 1691 1692 spi13: spi@a94000 { 1693 compatible = "qcom,geni-spi"; 1694 reg = <0x0 0x00a94000 0x0 0x4000>; 1695 clock-names = "se"; 1696 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1697 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1698 pinctrl-names = "default"; 1699 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1700 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1701 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1702 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1703 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1704 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1705 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1706 dma-names = "tx", "rx"; 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 status = "disabled"; 1710 }; 1711 1712 i2c14: i2c@a98000 { 1713 compatible = "qcom,geni-i2c"; 1714 reg = <0 0x00a98000 0 0x4000>; 1715 clock-names = "se"; 1716 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1717 pinctrl-names = "default"; 1718 pinctrl-0 = <&qup_i2c14_data_clk>; 1719 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1720 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1721 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1722 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1723 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1724 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1725 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1726 dma-names = "tx", "rx"; 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 status = "disabled"; 1730 }; 1731 1732 spi14: spi@a98000 { 1733 compatible = "qcom,geni-spi"; 1734 reg = <0x0 0x00a98000 0x0 0x4000>; 1735 clock-names = "se"; 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1737 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1738 pinctrl-names = "default"; 1739 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1740 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1741 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1742 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1743 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1744 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1745 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1746 dma-names = "tx", "rx"; 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 status = "disabled"; 1750 }; 1751 }; 1752 1753 rng: rng@10c3000 { 1754 compatible = "qcom,sm8450-prng-ee", "qcom,prng-ee"; 1755 reg = <0 0x010c3000 0 0x1000>; 1756 }; 1757 1758 pcie0: pci@1c00000 { 1759 compatible = "qcom,pcie-sm8450-pcie0"; 1760 reg = <0 0x01c00000 0 0x3000>, 1761 <0 0x60000000 0 0xf1d>, 1762 <0 0x60000f20 0 0xa8>, 1763 <0 0x60001000 0 0x1000>, 1764 <0 0x60100000 0 0x100000>; 1765 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1766 device_type = "pci"; 1767 linux,pci-domain = <0>; 1768 bus-range = <0x00 0xff>; 1769 num-lanes = <1>; 1770 1771 #address-cells = <3>; 1772 #size-cells = <2>; 1773 1774 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1775 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1776 1777 msi-map = <0x0 &gic_its 0x5980 0x1>, 1778 <0x100 &gic_its 0x5981 0x1>; 1779 msi-map-mask = <0xff00>; 1780 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1781 interrupt-names = "msi"; 1782 #interrupt-cells = <1>; 1783 interrupt-map-mask = <0 0 0 0x7>; 1784 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1785 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1786 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1787 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1788 1789 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1790 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1791 <&pcie0_lane>, 1792 <&rpmhcc RPMH_CXO_CLK>, 1793 <&gcc GCC_PCIE_0_AUX_CLK>, 1794 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1795 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1796 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1797 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1798 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1799 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1800 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1801 clock-names = "pipe", 1802 "pipe_mux", 1803 "phy_pipe", 1804 "ref", 1805 "aux", 1806 "cfg", 1807 "bus_master", 1808 "bus_slave", 1809 "slave_q2a", 1810 "ddrss_sf_tbu", 1811 "aggre0", 1812 "aggre1"; 1813 1814 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1815 <0x100 &apps_smmu 0x1c01 0x1>; 1816 1817 resets = <&gcc GCC_PCIE_0_BCR>; 1818 reset-names = "pci"; 1819 1820 power-domains = <&gcc PCIE_0_GDSC>; 1821 1822 phys = <&pcie0_lane>; 1823 phy-names = "pciephy"; 1824 1825 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1826 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1827 1828 pinctrl-names = "default"; 1829 pinctrl-0 = <&pcie0_default_state>; 1830 1831 status = "disabled"; 1832 }; 1833 1834 pcie0_phy: phy@1c06000 { 1835 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1836 reg = <0 0x01c06000 0 0x200>; 1837 #address-cells = <2>; 1838 #size-cells = <2>; 1839 ranges; 1840 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1841 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1842 <&gcc GCC_PCIE_0_CLKREF_EN>, 1843 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1844 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1845 1846 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1847 reset-names = "phy"; 1848 1849 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1850 assigned-clock-rates = <100000000>; 1851 1852 status = "disabled"; 1853 1854 pcie0_lane: phy@1c06200 { 1855 reg = <0 0x01c06e00 0 0x200>, /* tx */ 1856 <0 0x01c07000 0 0x200>, /* rx */ 1857 <0 0x01c06200 0 0x200>, /* pcs */ 1858 <0 0x01c06600 0 0x200>; /* pcs_pcie */ 1859 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1860 clock-names = "pipe0"; 1861 1862 #clock-cells = <0>; 1863 #phy-cells = <0>; 1864 clock-output-names = "pcie_0_pipe_clk"; 1865 }; 1866 }; 1867 1868 pcie1: pci@1c08000 { 1869 compatible = "qcom,pcie-sm8450-pcie1"; 1870 reg = <0 0x01c08000 0 0x3000>, 1871 <0 0x40000000 0 0xf1d>, 1872 <0 0x40000f20 0 0xa8>, 1873 <0 0x40001000 0 0x1000>, 1874 <0 0x40100000 0 0x100000>; 1875 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1876 device_type = "pci"; 1877 linux,pci-domain = <1>; 1878 bus-range = <0x00 0xff>; 1879 num-lanes = <2>; 1880 1881 #address-cells = <3>; 1882 #size-cells = <2>; 1883 1884 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1885 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1886 1887 msi-map = <0x0 &gic_its 0x5a00 0x1>, 1888 <0x100 &gic_its 0x5a01 0x1>; 1889 msi-map-mask = <0xff00>; 1890 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1891 interrupt-names = "msi"; 1892 #interrupt-cells = <1>; 1893 interrupt-map-mask = <0 0 0 0x7>; 1894 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1895 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1896 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1897 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1898 1899 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1900 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1901 <&pcie1_lane>, 1902 <&rpmhcc RPMH_CXO_CLK>, 1903 <&gcc GCC_PCIE_1_AUX_CLK>, 1904 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1905 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1906 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1907 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1908 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1909 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1910 clock-names = "pipe", 1911 "pipe_mux", 1912 "phy_pipe", 1913 "ref", 1914 "aux", 1915 "cfg", 1916 "bus_master", 1917 "bus_slave", 1918 "slave_q2a", 1919 "ddrss_sf_tbu", 1920 "aggre1"; 1921 1922 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1923 <0x100 &apps_smmu 0x1c81 0x1>; 1924 1925 resets = <&gcc GCC_PCIE_1_BCR>; 1926 reset-names = "pci"; 1927 1928 power-domains = <&gcc PCIE_1_GDSC>; 1929 1930 phys = <&pcie1_lane>; 1931 phy-names = "pciephy"; 1932 1933 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 1934 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1935 1936 pinctrl-names = "default"; 1937 pinctrl-0 = <&pcie1_default_state>; 1938 1939 status = "disabled"; 1940 }; 1941 1942 pcie1_phy: phy@1c0f000 { 1943 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 1944 reg = <0 0x01c0f000 0 0x200>; 1945 #address-cells = <2>; 1946 #size-cells = <2>; 1947 ranges; 1948 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1949 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1950 <&gcc GCC_PCIE_1_CLKREF_EN>, 1951 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1952 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1953 1954 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1955 reset-names = "phy"; 1956 1957 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1958 assigned-clock-rates = <100000000>; 1959 1960 status = "disabled"; 1961 1962 pcie1_lane: phy@1c0e000 { 1963 reg = <0 0x01c0e000 0 0x200>, /* tx */ 1964 <0 0x01c0e200 0 0x300>, /* rx */ 1965 <0 0x01c0f200 0 0x200>, /* pcs */ 1966 <0 0x01c0e800 0 0x200>, /* tx */ 1967 <0 0x01c0ea00 0 0x300>, /* rx */ 1968 <0 0x01c0f400 0 0xc00>; /* pcs_pcie */ 1969 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1970 clock-names = "pipe0"; 1971 1972 #clock-cells = <0>; 1973 #phy-cells = <0>; 1974 clock-output-names = "pcie_1_pipe_clk"; 1975 }; 1976 }; 1977 1978 config_noc: interconnect@1500000 { 1979 compatible = "qcom,sm8450-config-noc"; 1980 reg = <0 0x01500000 0 0x1c000>; 1981 #interconnect-cells = <2>; 1982 qcom,bcm-voters = <&apps_bcm_voter>; 1983 }; 1984 1985 system_noc: interconnect@1680000 { 1986 compatible = "qcom,sm8450-system-noc"; 1987 reg = <0 0x01680000 0 0x1e200>; 1988 #interconnect-cells = <2>; 1989 qcom,bcm-voters = <&apps_bcm_voter>; 1990 }; 1991 1992 pcie_noc: interconnect@16c0000 { 1993 compatible = "qcom,sm8450-pcie-anoc"; 1994 reg = <0 0x016c0000 0 0xe280>; 1995 #interconnect-cells = <2>; 1996 qcom,bcm-voters = <&apps_bcm_voter>; 1997 }; 1998 1999 aggre1_noc: interconnect@16e0000 { 2000 compatible = "qcom,sm8450-aggre1-noc"; 2001 reg = <0 0x016e0000 0 0x1c080>; 2002 #interconnect-cells = <2>; 2003 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2004 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2005 qcom,bcm-voters = <&apps_bcm_voter>; 2006 }; 2007 2008 aggre2_noc: interconnect@1700000 { 2009 compatible = "qcom,sm8450-aggre2-noc"; 2010 reg = <0 0x01700000 0 0x31080>; 2011 #interconnect-cells = <2>; 2012 qcom,bcm-voters = <&apps_bcm_voter>; 2013 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2014 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 2015 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2016 <&rpmhcc RPMH_IPA_CLK>; 2017 }; 2018 2019 mmss_noc: interconnect@1740000 { 2020 compatible = "qcom,sm8450-mmss-noc"; 2021 reg = <0 0x01740000 0 0x1f080>; 2022 #interconnect-cells = <2>; 2023 qcom,bcm-voters = <&apps_bcm_voter>; 2024 }; 2025 2026 tcsr_mutex: hwlock@1f40000 { 2027 compatible = "qcom,tcsr-mutex"; 2028 reg = <0x0 0x01f40000 0x0 0x40000>; 2029 #hwlock-cells = <1>; 2030 }; 2031 2032 tcsr: syscon@1fc0000 { 2033 compatible = "qcom,sm8450-tcsr", "syscon"; 2034 reg = <0x0 0x1fc0000 0x0 0x30000>; 2035 }; 2036 2037 usb_1_hsphy: phy@88e3000 { 2038 compatible = "qcom,sm8450-usb-hs-phy", 2039 "qcom,usb-snps-hs-7nm-phy"; 2040 reg = <0 0x088e3000 0 0x400>; 2041 status = "disabled"; 2042 #phy-cells = <0>; 2043 2044 clocks = <&rpmhcc RPMH_CXO_CLK>; 2045 clock-names = "ref"; 2046 2047 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2048 }; 2049 2050 usb_1_qmpphy: phy@88e8000 { 2051 compatible = "qcom,sm8450-qmp-usb3-dp-phy"; 2052 reg = <0 0x088e8000 0 0x3000>; 2053 2054 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2055 <&rpmhcc RPMH_CXO_CLK>, 2056 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2057 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2058 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2059 2060 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2061 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2062 reset-names = "phy", "common"; 2063 2064 #clock-cells = <1>; 2065 #phy-cells = <1>; 2066 2067 status = "disabled"; 2068 2069 ports { 2070 #address-cells = <1>; 2071 #size-cells = <0>; 2072 2073 port@0 { 2074 reg = <0>; 2075 2076 usb_1_qmpphy_out: endpoint { 2077 }; 2078 }; 2079 2080 port@1 { 2081 reg = <1>; 2082 2083 usb_1_qmpphy_usb_ss_in: endpoint { 2084 }; 2085 }; 2086 2087 port@2 { 2088 reg = <2>; 2089 2090 usb_1_qmpphy_dp_in: endpoint { 2091 }; 2092 }; 2093 }; 2094 }; 2095 2096 remoteproc_slpi: remoteproc@2400000 { 2097 compatible = "qcom,sm8450-slpi-pas"; 2098 reg = <0 0x02400000 0 0x4000>; 2099 2100 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2101 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2102 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2103 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2104 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2105 interrupt-names = "wdog", "fatal", "ready", 2106 "handover", "stop-ack"; 2107 2108 clocks = <&rpmhcc RPMH_CXO_CLK>; 2109 clock-names = "xo"; 2110 2111 power-domains = <&rpmhpd RPMHPD_LCX>, 2112 <&rpmhpd RPMHPD_LMX>; 2113 power-domain-names = "lcx", "lmx"; 2114 2115 memory-region = <&slpi_mem>; 2116 2117 qcom,qmp = <&aoss_qmp>; 2118 2119 qcom,smem-states = <&smp2p_slpi_out 0>; 2120 qcom,smem-state-names = "stop"; 2121 2122 status = "disabled"; 2123 2124 glink-edge { 2125 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2126 IPCC_MPROC_SIGNAL_GLINK_QMP 2127 IRQ_TYPE_EDGE_RISING>; 2128 mboxes = <&ipcc IPCC_CLIENT_SLPI 2129 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2130 2131 label = "slpi"; 2132 qcom,remote-pid = <3>; 2133 2134 fastrpc { 2135 compatible = "qcom,fastrpc"; 2136 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2137 label = "sdsp"; 2138 qcom,non-secure-domain; 2139 #address-cells = <1>; 2140 #size-cells = <0>; 2141 2142 compute-cb@1 { 2143 compatible = "qcom,fastrpc-compute-cb"; 2144 reg = <1>; 2145 iommus = <&apps_smmu 0x0541 0x0>; 2146 }; 2147 2148 compute-cb@2 { 2149 compatible = "qcom,fastrpc-compute-cb"; 2150 reg = <2>; 2151 iommus = <&apps_smmu 0x0542 0x0>; 2152 }; 2153 2154 compute-cb@3 { 2155 compatible = "qcom,fastrpc-compute-cb"; 2156 reg = <3>; 2157 iommus = <&apps_smmu 0x0543 0x0>; 2158 /* note: shared-cb = <4> in downstream */ 2159 }; 2160 }; 2161 }; 2162 }; 2163 2164 remoteproc_adsp: remoteproc@3000000 { 2165 compatible = "qcom,sm8450-adsp-pas"; 2166 reg = <0x0 0x03000000 0x0 0x10000>; 2167 2168 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2169 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2170 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2171 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2172 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2173 interrupt-names = "wdog", "fatal", "ready", 2174 "handover", "stop-ack"; 2175 2176 clocks = <&rpmhcc RPMH_CXO_CLK>; 2177 clock-names = "xo"; 2178 2179 power-domains = <&rpmhpd RPMHPD_LCX>, 2180 <&rpmhpd RPMHPD_LMX>; 2181 power-domain-names = "lcx", "lmx"; 2182 2183 memory-region = <&adsp_mem>; 2184 2185 qcom,qmp = <&aoss_qmp>; 2186 2187 qcom,smem-states = <&smp2p_adsp_out 0>; 2188 qcom,smem-state-names = "stop"; 2189 2190 status = "disabled"; 2191 2192 remoteproc_adsp_glink: glink-edge { 2193 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2194 IPCC_MPROC_SIGNAL_GLINK_QMP 2195 IRQ_TYPE_EDGE_RISING>; 2196 mboxes = <&ipcc IPCC_CLIENT_LPASS 2197 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2198 2199 label = "lpass"; 2200 qcom,remote-pid = <2>; 2201 2202 gpr { 2203 compatible = "qcom,gpr"; 2204 qcom,glink-channels = "adsp_apps"; 2205 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2206 qcom,intents = <512 20>; 2207 #address-cells = <1>; 2208 #size-cells = <0>; 2209 2210 q6apm: service@1 { 2211 compatible = "qcom,q6apm"; 2212 reg = <GPR_APM_MODULE_IID>; 2213 #sound-dai-cells = <0>; 2214 qcom,protection-domain = "avs/audio", 2215 "msm/adsp/audio_pd"; 2216 2217 q6apmdai: dais { 2218 compatible = "qcom,q6apm-dais"; 2219 iommus = <&apps_smmu 0x1801 0x0>; 2220 }; 2221 2222 q6apmbedai: bedais { 2223 compatible = "qcom,q6apm-lpass-dais"; 2224 #sound-dai-cells = <1>; 2225 }; 2226 }; 2227 2228 q6prm: service@2 { 2229 compatible = "qcom,q6prm"; 2230 reg = <GPR_PRM_MODULE_IID>; 2231 qcom,protection-domain = "avs/audio", 2232 "msm/adsp/audio_pd"; 2233 2234 q6prmcc: clock-controller { 2235 compatible = "qcom,q6prm-lpass-clocks"; 2236 #clock-cells = <2>; 2237 }; 2238 }; 2239 }; 2240 2241 fastrpc { 2242 compatible = "qcom,fastrpc"; 2243 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2244 label = "adsp"; 2245 qcom,non-secure-domain; 2246 #address-cells = <1>; 2247 #size-cells = <0>; 2248 2249 compute-cb@3 { 2250 compatible = "qcom,fastrpc-compute-cb"; 2251 reg = <3>; 2252 iommus = <&apps_smmu 0x1803 0x0>; 2253 }; 2254 2255 compute-cb@4 { 2256 compatible = "qcom,fastrpc-compute-cb"; 2257 reg = <4>; 2258 iommus = <&apps_smmu 0x1804 0x0>; 2259 }; 2260 2261 compute-cb@5 { 2262 compatible = "qcom,fastrpc-compute-cb"; 2263 reg = <5>; 2264 iommus = <&apps_smmu 0x1805 0x0>; 2265 }; 2266 }; 2267 }; 2268 }; 2269 2270 wsa2macro: codec@31e0000 { 2271 compatible = "qcom,sm8450-lpass-wsa-macro"; 2272 reg = <0 0x031e0000 0 0x1000>; 2273 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2274 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2275 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2276 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2277 <&vamacro>; 2278 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2279 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2280 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2281 assigned-clock-rates = <19200000>, <19200000>; 2282 2283 #clock-cells = <0>; 2284 clock-output-names = "wsa2-mclk"; 2285 pinctrl-names = "default"; 2286 pinctrl-0 = <&wsa2_swr_active>; 2287 #sound-dai-cells = <1>; 2288 }; 2289 2290 swr4: soundwire@31f0000 { 2291 compatible = "qcom,soundwire-v1.7.0"; 2292 reg = <0 0x031f0000 0 0x2000>; 2293 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2294 clocks = <&wsa2macro>; 2295 clock-names = "iface"; 2296 label = "WSA2"; 2297 2298 qcom,din-ports = <2>; 2299 qcom,dout-ports = <6>; 2300 2301 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2302 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2303 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2304 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2305 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2306 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2307 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2308 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2309 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2310 2311 #address-cells = <2>; 2312 #size-cells = <0>; 2313 #sound-dai-cells = <1>; 2314 status = "disabled"; 2315 }; 2316 2317 rxmacro: codec@3200000 { 2318 compatible = "qcom,sm8450-lpass-rx-macro"; 2319 reg = <0 0x03200000 0 0x1000>; 2320 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2321 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2322 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2323 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2324 <&vamacro>; 2325 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2326 2327 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2328 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2329 assigned-clock-rates = <19200000>, <19200000>; 2330 2331 #clock-cells = <0>; 2332 clock-output-names = "mclk"; 2333 pinctrl-names = "default"; 2334 pinctrl-0 = <&rx_swr_active>; 2335 #sound-dai-cells = <1>; 2336 }; 2337 2338 swr1: soundwire@3210000 { 2339 compatible = "qcom,soundwire-v1.7.0"; 2340 reg = <0 0x03210000 0 0x2000>; 2341 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2342 clocks = <&rxmacro>; 2343 clock-names = "iface"; 2344 label = "RX"; 2345 qcom,din-ports = <0>; 2346 qcom,dout-ports = <5>; 2347 2348 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2349 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2350 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2351 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2352 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2353 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2354 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2355 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2356 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2357 2358 #address-cells = <2>; 2359 #size-cells = <0>; 2360 #sound-dai-cells = <1>; 2361 status = "disabled"; 2362 }; 2363 2364 txmacro: codec@3220000 { 2365 compatible = "qcom,sm8450-lpass-tx-macro"; 2366 reg = <0 0x03220000 0 0x1000>; 2367 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2368 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2369 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2370 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2371 <&vamacro>; 2372 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2373 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2374 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2375 assigned-clock-rates = <19200000>, <19200000>; 2376 2377 #clock-cells = <0>; 2378 clock-output-names = "mclk"; 2379 pinctrl-names = "default"; 2380 pinctrl-0 = <&tx_swr_active>; 2381 #sound-dai-cells = <1>; 2382 }; 2383 2384 wsamacro: codec@3240000 { 2385 compatible = "qcom,sm8450-lpass-wsa-macro"; 2386 reg = <0 0x03240000 0 0x1000>; 2387 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2388 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2389 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2390 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2391 <&vamacro>; 2392 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2393 2394 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2395 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2396 assigned-clock-rates = <19200000>, <19200000>; 2397 2398 #clock-cells = <0>; 2399 clock-output-names = "mclk"; 2400 pinctrl-names = "default"; 2401 pinctrl-0 = <&wsa_swr_active>; 2402 #sound-dai-cells = <1>; 2403 }; 2404 2405 swr0: soundwire@3250000 { 2406 compatible = "qcom,soundwire-v1.7.0"; 2407 reg = <0 0x03250000 0 0x2000>; 2408 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2409 clocks = <&wsamacro>; 2410 clock-names = "iface"; 2411 label = "WSA"; 2412 2413 qcom,din-ports = <2>; 2414 qcom,dout-ports = <6>; 2415 2416 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2417 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2418 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2419 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2420 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2421 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2422 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2423 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2424 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2425 2426 #address-cells = <2>; 2427 #size-cells = <0>; 2428 #sound-dai-cells = <1>; 2429 status = "disabled"; 2430 }; 2431 2432 swr2: soundwire@33b0000 { 2433 compatible = "qcom,soundwire-v1.7.0"; 2434 reg = <0 0x033b0000 0 0x2000>; 2435 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2436 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2437 interrupt-names = "core", "wakeup"; 2438 2439 clocks = <&txmacro>; 2440 clock-names = "iface"; 2441 label = "TX"; 2442 2443 qcom,din-ports = <4>; 2444 qcom,dout-ports = <0>; 2445 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2446 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2447 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2448 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2449 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2450 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2451 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2452 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2453 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2454 2455 #address-cells = <2>; 2456 #size-cells = <0>; 2457 #sound-dai-cells = <1>; 2458 status = "disabled"; 2459 }; 2460 2461 vamacro: codec@33f0000 { 2462 compatible = "qcom,sm8450-lpass-va-macro"; 2463 reg = <0 0x033f0000 0 0x1000>; 2464 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2465 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2466 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2467 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2468 clock-names = "mclk", "macro", "dcodec", "npl"; 2469 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2470 assigned-clock-rates = <19200000>; 2471 2472 #clock-cells = <0>; 2473 clock-output-names = "fsgen"; 2474 #sound-dai-cells = <1>; 2475 status = "disabled"; 2476 }; 2477 2478 remoteproc_cdsp: remoteproc@32300000 { 2479 compatible = "qcom,sm8450-cdsp-pas"; 2480 reg = <0 0x32300000 0 0x10000>; 2481 2482 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2483 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2484 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2485 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2486 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2487 interrupt-names = "wdog", "fatal", "ready", 2488 "handover", "stop-ack"; 2489 2490 clocks = <&rpmhcc RPMH_CXO_CLK>; 2491 clock-names = "xo"; 2492 2493 power-domains = <&rpmhpd RPMHPD_CX>, 2494 <&rpmhpd RPMHPD_MXC>; 2495 power-domain-names = "cx", "mxc"; 2496 2497 memory-region = <&cdsp_mem>; 2498 2499 qcom,qmp = <&aoss_qmp>; 2500 2501 qcom,smem-states = <&smp2p_cdsp_out 0>; 2502 qcom,smem-state-names = "stop"; 2503 2504 status = "disabled"; 2505 2506 glink-edge { 2507 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2508 IPCC_MPROC_SIGNAL_GLINK_QMP 2509 IRQ_TYPE_EDGE_RISING>; 2510 mboxes = <&ipcc IPCC_CLIENT_CDSP 2511 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2512 2513 label = "cdsp"; 2514 qcom,remote-pid = <5>; 2515 2516 fastrpc { 2517 compatible = "qcom,fastrpc"; 2518 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2519 label = "cdsp"; 2520 qcom,non-secure-domain; 2521 #address-cells = <1>; 2522 #size-cells = <0>; 2523 2524 compute-cb@1 { 2525 compatible = "qcom,fastrpc-compute-cb"; 2526 reg = <1>; 2527 iommus = <&apps_smmu 0x2161 0x0400>, 2528 <&apps_smmu 0x1021 0x1420>; 2529 }; 2530 2531 compute-cb@2 { 2532 compatible = "qcom,fastrpc-compute-cb"; 2533 reg = <2>; 2534 iommus = <&apps_smmu 0x2162 0x0400>, 2535 <&apps_smmu 0x1022 0x1420>; 2536 }; 2537 2538 compute-cb@3 { 2539 compatible = "qcom,fastrpc-compute-cb"; 2540 reg = <3>; 2541 iommus = <&apps_smmu 0x2163 0x0400>, 2542 <&apps_smmu 0x1023 0x1420>; 2543 }; 2544 2545 compute-cb@4 { 2546 compatible = "qcom,fastrpc-compute-cb"; 2547 reg = <4>; 2548 iommus = <&apps_smmu 0x2164 0x0400>, 2549 <&apps_smmu 0x1024 0x1420>; 2550 }; 2551 2552 compute-cb@5 { 2553 compatible = "qcom,fastrpc-compute-cb"; 2554 reg = <5>; 2555 iommus = <&apps_smmu 0x2165 0x0400>, 2556 <&apps_smmu 0x1025 0x1420>; 2557 }; 2558 2559 compute-cb@6 { 2560 compatible = "qcom,fastrpc-compute-cb"; 2561 reg = <6>; 2562 iommus = <&apps_smmu 0x2166 0x0400>, 2563 <&apps_smmu 0x1026 0x1420>; 2564 }; 2565 2566 compute-cb@7 { 2567 compatible = "qcom,fastrpc-compute-cb"; 2568 reg = <7>; 2569 iommus = <&apps_smmu 0x2167 0x0400>, 2570 <&apps_smmu 0x1027 0x1420>; 2571 }; 2572 2573 compute-cb@8 { 2574 compatible = "qcom,fastrpc-compute-cb"; 2575 reg = <8>; 2576 iommus = <&apps_smmu 0x2168 0x0400>, 2577 <&apps_smmu 0x1028 0x1420>; 2578 }; 2579 2580 /* note: secure cb9 in downstream */ 2581 }; 2582 }; 2583 }; 2584 2585 remoteproc_mpss: remoteproc@4080000 { 2586 compatible = "qcom,sm8450-mpss-pas"; 2587 reg = <0x0 0x04080000 0x0 0x10000>; 2588 2589 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2590 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2591 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2592 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2593 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2594 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2595 interrupt-names = "wdog", "fatal", "ready", "handover", 2596 "stop-ack", "shutdown-ack"; 2597 2598 clocks = <&rpmhcc RPMH_CXO_CLK>; 2599 clock-names = "xo"; 2600 2601 power-domains = <&rpmhpd RPMHPD_CX>, 2602 <&rpmhpd RPMHPD_MSS>; 2603 power-domain-names = "cx", "mss"; 2604 2605 memory-region = <&mpss_mem>; 2606 2607 qcom,qmp = <&aoss_qmp>; 2608 2609 qcom,smem-states = <&smp2p_modem_out 0>; 2610 qcom,smem-state-names = "stop"; 2611 2612 status = "disabled"; 2613 2614 glink-edge { 2615 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2616 IPCC_MPROC_SIGNAL_GLINK_QMP 2617 IRQ_TYPE_EDGE_RISING>; 2618 mboxes = <&ipcc IPCC_CLIENT_MPSS 2619 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2620 label = "modem"; 2621 qcom,remote-pid = <1>; 2622 }; 2623 }; 2624 2625 videocc: clock-controller@aaf0000 { 2626 compatible = "qcom,sm8450-videocc"; 2627 reg = <0 0x0aaf0000 0 0x10000>; 2628 clocks = <&rpmhcc RPMH_CXO_CLK>, 2629 <&gcc GCC_VIDEO_AHB_CLK>; 2630 power-domains = <&rpmhpd RPMHPD_MMCX>; 2631 required-opps = <&rpmhpd_opp_low_svs>; 2632 #clock-cells = <1>; 2633 #reset-cells = <1>; 2634 #power-domain-cells = <1>; 2635 }; 2636 2637 cci0: cci@ac15000 { 2638 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2639 reg = <0 0x0ac15000 0 0x1000>; 2640 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 2641 power-domains = <&camcc TITAN_TOP_GDSC>; 2642 2643 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2644 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2645 <&camcc CAM_CC_CPAS_AHB_CLK>, 2646 <&camcc CAM_CC_CCI_0_CLK>, 2647 <&camcc CAM_CC_CCI_0_CLK_SRC>; 2648 clock-names = "camnoc_axi", 2649 "slow_ahb_src", 2650 "cpas_ahb", 2651 "cci", 2652 "cci_src"; 2653 pinctrl-0 = <&cci0_default &cci1_default>; 2654 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2655 pinctrl-names = "default", "sleep"; 2656 2657 status = "disabled"; 2658 #address-cells = <1>; 2659 #size-cells = <0>; 2660 2661 cci0_i2c0: i2c-bus@0 { 2662 reg = <0>; 2663 clock-frequency = <1000000>; 2664 #address-cells = <1>; 2665 #size-cells = <0>; 2666 }; 2667 2668 cci0_i2c1: i2c-bus@1 { 2669 reg = <1>; 2670 clock-frequency = <1000000>; 2671 #address-cells = <1>; 2672 #size-cells = <0>; 2673 }; 2674 }; 2675 2676 cci1: cci@ac16000 { 2677 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2678 reg = <0 0x0ac16000 0 0x1000>; 2679 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 2680 power-domains = <&camcc TITAN_TOP_GDSC>; 2681 2682 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2683 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2684 <&camcc CAM_CC_CPAS_AHB_CLK>, 2685 <&camcc CAM_CC_CCI_1_CLK>, 2686 <&camcc CAM_CC_CCI_1_CLK_SRC>; 2687 clock-names = "camnoc_axi", 2688 "slow_ahb_src", 2689 "cpas_ahb", 2690 "cci", 2691 "cci_src"; 2692 pinctrl-0 = <&cci2_default &cci3_default>; 2693 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 2694 pinctrl-names = "default", "sleep"; 2695 2696 status = "disabled"; 2697 #address-cells = <1>; 2698 #size-cells = <0>; 2699 2700 cci1_i2c0: i2c-bus@0 { 2701 reg = <0>; 2702 clock-frequency = <1000000>; 2703 #address-cells = <1>; 2704 #size-cells = <0>; 2705 }; 2706 2707 cci1_i2c1: i2c-bus@1 { 2708 reg = <1>; 2709 clock-frequency = <1000000>; 2710 #address-cells = <1>; 2711 #size-cells = <0>; 2712 }; 2713 }; 2714 2715 camcc: clock-controller@ade0000 { 2716 compatible = "qcom,sm8450-camcc"; 2717 reg = <0 0x0ade0000 0 0x20000>; 2718 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2719 <&rpmhcc RPMH_CXO_CLK>, 2720 <&rpmhcc RPMH_CXO_CLK_A>, 2721 <&sleep_clk>; 2722 power-domains = <&rpmhpd RPMHPD_MMCX>; 2723 required-opps = <&rpmhpd_opp_low_svs>; 2724 #clock-cells = <1>; 2725 #reset-cells = <1>; 2726 #power-domain-cells = <1>; 2727 status = "disabled"; 2728 }; 2729 2730 mdss: display-subsystem@ae00000 { 2731 compatible = "qcom,sm8450-mdss"; 2732 reg = <0 0x0ae00000 0 0x1000>; 2733 reg-names = "mdss"; 2734 2735 /* same path used twice */ 2736 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2737 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2738 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2739 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2740 interconnect-names = "mdp0-mem", 2741 "mdp1-mem", 2742 "cpu-cfg"; 2743 2744 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2745 2746 power-domains = <&dispcc MDSS_GDSC>; 2747 2748 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2749 <&gcc GCC_DISP_HF_AXI_CLK>, 2750 <&gcc GCC_DISP_SF_AXI_CLK>, 2751 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2752 2753 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2754 interrupt-controller; 2755 #interrupt-cells = <1>; 2756 2757 iommus = <&apps_smmu 0x2800 0x402>; 2758 2759 #address-cells = <2>; 2760 #size-cells = <2>; 2761 ranges; 2762 2763 status = "disabled"; 2764 2765 mdss_mdp: display-controller@ae01000 { 2766 compatible = "qcom,sm8450-dpu"; 2767 reg = <0 0x0ae01000 0 0x8f000>, 2768 <0 0x0aeb0000 0 0x2008>; 2769 reg-names = "mdp", "vbif"; 2770 2771 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2772 <&gcc GCC_DISP_SF_AXI_CLK>, 2773 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2774 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2775 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2776 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2777 clock-names = "bus", 2778 "nrt_bus", 2779 "iface", 2780 "lut", 2781 "core", 2782 "vsync"; 2783 2784 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2785 assigned-clock-rates = <19200000>; 2786 2787 operating-points-v2 = <&mdp_opp_table>; 2788 power-domains = <&rpmhpd RPMHPD_MMCX>; 2789 2790 interrupt-parent = <&mdss>; 2791 interrupts = <0>; 2792 2793 ports { 2794 #address-cells = <1>; 2795 #size-cells = <0>; 2796 2797 port@0 { 2798 reg = <0>; 2799 dpu_intf1_out: endpoint { 2800 remote-endpoint = <&mdss_dsi0_in>; 2801 }; 2802 }; 2803 2804 port@1 { 2805 reg = <1>; 2806 dpu_intf2_out: endpoint { 2807 remote-endpoint = <&mdss_dsi1_in>; 2808 }; 2809 }; 2810 2811 port@2 { 2812 reg = <2>; 2813 dpu_intf0_out: endpoint { 2814 remote-endpoint = <&mdss_dp0_in>; 2815 }; 2816 }; 2817 }; 2818 2819 mdp_opp_table: opp-table { 2820 compatible = "operating-points-v2"; 2821 2822 opp-172000000 { 2823 opp-hz = /bits/ 64 <172000000>; 2824 required-opps = <&rpmhpd_opp_low_svs_d1>; 2825 }; 2826 2827 opp-200000000 { 2828 opp-hz = /bits/ 64 <200000000>; 2829 required-opps = <&rpmhpd_opp_low_svs>; 2830 }; 2831 2832 opp-325000000 { 2833 opp-hz = /bits/ 64 <325000000>; 2834 required-opps = <&rpmhpd_opp_svs>; 2835 }; 2836 2837 opp-375000000 { 2838 opp-hz = /bits/ 64 <375000000>; 2839 required-opps = <&rpmhpd_opp_svs_l1>; 2840 }; 2841 2842 opp-500000000 { 2843 opp-hz = /bits/ 64 <500000000>; 2844 required-opps = <&rpmhpd_opp_nom>; 2845 }; 2846 }; 2847 }; 2848 2849 mdss_dp0: displayport-controller@ae90000 { 2850 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; 2851 reg = <0 0xae90000 0 0x200>, 2852 <0 0xae90200 0 0x200>, 2853 <0 0xae90400 0 0xc00>, 2854 <0 0xae91000 0 0x400>, 2855 <0 0xae91400 0 0x400>; 2856 interrupt-parent = <&mdss>; 2857 interrupts = <12>; 2858 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2859 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2860 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2861 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2862 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2863 clock-names = "core_iface", 2864 "core_aux", 2865 "ctrl_link", 2866 "ctrl_link_iface", 2867 "stream_pixel"; 2868 2869 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2870 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2871 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2872 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2873 2874 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2875 phy-names = "dp"; 2876 2877 #sound-dai-cells = <0>; 2878 2879 operating-points-v2 = <&dp_opp_table>; 2880 power-domains = <&rpmhpd RPMHPD_MMCX>; 2881 2882 status = "disabled"; 2883 2884 ports { 2885 #address-cells = <1>; 2886 #size-cells = <0>; 2887 2888 port@0 { 2889 reg = <0>; 2890 mdss_dp0_in: endpoint { 2891 remote-endpoint = <&dpu_intf0_out>; 2892 }; 2893 }; 2894 }; 2895 2896 dp_opp_table: opp-table { 2897 compatible = "operating-points-v2"; 2898 2899 opp-160000000 { 2900 opp-hz = /bits/ 64 <160000000>; 2901 required-opps = <&rpmhpd_opp_low_svs>; 2902 }; 2903 2904 opp-270000000 { 2905 opp-hz = /bits/ 64 <270000000>; 2906 required-opps = <&rpmhpd_opp_svs>; 2907 }; 2908 2909 opp-540000000 { 2910 opp-hz = /bits/ 64 <540000000>; 2911 required-opps = <&rpmhpd_opp_svs_l1>; 2912 }; 2913 2914 opp-810000000 { 2915 opp-hz = /bits/ 64 <810000000>; 2916 required-opps = <&rpmhpd_opp_nom>; 2917 }; 2918 }; 2919 }; 2920 2921 mdss_dsi0: dsi@ae94000 { 2922 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2923 reg = <0 0x0ae94000 0 0x400>; 2924 reg-names = "dsi_ctrl"; 2925 2926 interrupt-parent = <&mdss>; 2927 interrupts = <4>; 2928 2929 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2930 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2931 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2932 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2933 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2934 <&gcc GCC_DISP_HF_AXI_CLK>; 2935 clock-names = "byte", 2936 "byte_intf", 2937 "pixel", 2938 "core", 2939 "iface", 2940 "bus"; 2941 2942 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2943 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 2944 2945 operating-points-v2 = <&mdss_dsi_opp_table>; 2946 power-domains = <&rpmhpd RPMHPD_MMCX>; 2947 2948 phys = <&mdss_dsi0_phy>; 2949 phy-names = "dsi"; 2950 2951 #address-cells = <1>; 2952 #size-cells = <0>; 2953 2954 status = "disabled"; 2955 2956 ports { 2957 #address-cells = <1>; 2958 #size-cells = <0>; 2959 2960 port@0 { 2961 reg = <0>; 2962 mdss_dsi0_in: endpoint { 2963 remote-endpoint = <&dpu_intf1_out>; 2964 }; 2965 }; 2966 2967 port@1 { 2968 reg = <1>; 2969 mdss_dsi0_out: endpoint { 2970 }; 2971 }; 2972 }; 2973 2974 mdss_dsi_opp_table: opp-table { 2975 compatible = "operating-points-v2"; 2976 2977 opp-187500000 { 2978 opp-hz = /bits/ 64 <187500000>; 2979 required-opps = <&rpmhpd_opp_low_svs>; 2980 }; 2981 2982 opp-300000000 { 2983 opp-hz = /bits/ 64 <300000000>; 2984 required-opps = <&rpmhpd_opp_svs>; 2985 }; 2986 2987 opp-358000000 { 2988 opp-hz = /bits/ 64 <358000000>; 2989 required-opps = <&rpmhpd_opp_svs_l1>; 2990 }; 2991 }; 2992 }; 2993 2994 mdss_dsi0_phy: phy@ae94400 { 2995 compatible = "qcom,sm8450-dsi-phy-5nm"; 2996 reg = <0 0x0ae94400 0 0x200>, 2997 <0 0x0ae94600 0 0x280>, 2998 <0 0x0ae94900 0 0x260>; 2999 reg-names = "dsi_phy", 3000 "dsi_phy_lane", 3001 "dsi_pll"; 3002 3003 #clock-cells = <1>; 3004 #phy-cells = <0>; 3005 3006 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3007 <&rpmhcc RPMH_CXO_CLK>; 3008 clock-names = "iface", "ref"; 3009 3010 status = "disabled"; 3011 }; 3012 3013 mdss_dsi1: dsi@ae96000 { 3014 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3015 reg = <0 0x0ae96000 0 0x400>; 3016 reg-names = "dsi_ctrl"; 3017 3018 interrupt-parent = <&mdss>; 3019 interrupts = <5>; 3020 3021 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3022 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3023 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3024 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3025 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3026 <&gcc GCC_DISP_HF_AXI_CLK>; 3027 clock-names = "byte", 3028 "byte_intf", 3029 "pixel", 3030 "core", 3031 "iface", 3032 "bus"; 3033 3034 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3035 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 3036 3037 operating-points-v2 = <&mdss_dsi_opp_table>; 3038 power-domains = <&rpmhpd RPMHPD_MMCX>; 3039 3040 phys = <&mdss_dsi1_phy>; 3041 phy-names = "dsi"; 3042 3043 #address-cells = <1>; 3044 #size-cells = <0>; 3045 3046 status = "disabled"; 3047 3048 ports { 3049 #address-cells = <1>; 3050 #size-cells = <0>; 3051 3052 port@0 { 3053 reg = <0>; 3054 mdss_dsi1_in: endpoint { 3055 remote-endpoint = <&dpu_intf2_out>; 3056 }; 3057 }; 3058 3059 port@1 { 3060 reg = <1>; 3061 mdss_dsi1_out: endpoint { 3062 }; 3063 }; 3064 }; 3065 }; 3066 3067 mdss_dsi1_phy: phy@ae96400 { 3068 compatible = "qcom,sm8450-dsi-phy-5nm"; 3069 reg = <0 0x0ae96400 0 0x200>, 3070 <0 0x0ae96600 0 0x280>, 3071 <0 0x0ae96900 0 0x260>; 3072 reg-names = "dsi_phy", 3073 "dsi_phy_lane", 3074 "dsi_pll"; 3075 3076 #clock-cells = <1>; 3077 #phy-cells = <0>; 3078 3079 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3080 <&rpmhcc RPMH_CXO_CLK>; 3081 clock-names = "iface", "ref"; 3082 3083 status = "disabled"; 3084 }; 3085 }; 3086 3087 dispcc: clock-controller@af00000 { 3088 compatible = "qcom,sm8450-dispcc"; 3089 reg = <0 0x0af00000 0 0x20000>; 3090 clocks = <&rpmhcc RPMH_CXO_CLK>, 3091 <&rpmhcc RPMH_CXO_CLK_A>, 3092 <&gcc GCC_DISP_AHB_CLK>, 3093 <&sleep_clk>, 3094 <&mdss_dsi0_phy 0>, 3095 <&mdss_dsi0_phy 1>, 3096 <&mdss_dsi1_phy 0>, 3097 <&mdss_dsi1_phy 1>, 3098 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3099 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3100 <0>, /* dp1 */ 3101 <0>, 3102 <0>, /* dp2 */ 3103 <0>, 3104 <0>, /* dp3 */ 3105 <0>; 3106 power-domains = <&rpmhpd RPMHPD_MMCX>; 3107 required-opps = <&rpmhpd_opp_low_svs>; 3108 #clock-cells = <1>; 3109 #reset-cells = <1>; 3110 #power-domain-cells = <1>; 3111 status = "disabled"; 3112 }; 3113 3114 pdc: interrupt-controller@b220000 { 3115 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 3116 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3117 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 3118 <94 609 31>, <125 63 1>, <126 716 12>; 3119 #interrupt-cells = <2>; 3120 interrupt-parent = <&intc>; 3121 interrupt-controller; 3122 }; 3123 3124 tsens0: thermal-sensor@c263000 { 3125 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3126 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3127 <0 0x0c222000 0 0x1000>; /* SROT */ 3128 #qcom,sensors = <16>; 3129 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3131 interrupt-names = "uplow", "critical"; 3132 #thermal-sensor-cells = <1>; 3133 }; 3134 3135 tsens1: thermal-sensor@c265000 { 3136 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3137 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3138 <0 0x0c223000 0 0x1000>; /* SROT */ 3139 #qcom,sensors = <16>; 3140 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3142 interrupt-names = "uplow", "critical"; 3143 #thermal-sensor-cells = <1>; 3144 }; 3145 3146 aoss_qmp: power-management@c300000 { 3147 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3148 reg = <0 0x0c300000 0 0x400>; 3149 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3150 IRQ_TYPE_EDGE_RISING>; 3151 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3152 3153 #clock-cells = <0>; 3154 }; 3155 3156 sram@c3f0000 { 3157 compatible = "qcom,rpmh-stats"; 3158 reg = <0 0x0c3f0000 0 0x400>; 3159 }; 3160 3161 spmi_bus: spmi@c400000 { 3162 compatible = "qcom,spmi-pmic-arb"; 3163 reg = <0 0x0c400000 0 0x00003000>, 3164 <0 0x0c500000 0 0x00400000>, 3165 <0 0x0c440000 0 0x00080000>, 3166 <0 0x0c4c0000 0 0x00010000>, 3167 <0 0x0c42d000 0 0x00010000>; 3168 reg-names = "core", 3169 "chnls", 3170 "obsrvr", 3171 "intr", 3172 "cnfg"; 3173 interrupt-names = "periph_irq"; 3174 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3175 qcom,ee = <0>; 3176 qcom,channel = <0>; 3177 interrupt-controller; 3178 #interrupt-cells = <4>; 3179 #address-cells = <2>; 3180 #size-cells = <0>; 3181 }; 3182 3183 ipcc: mailbox@ed18000 { 3184 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3185 reg = <0 0x0ed18000 0 0x1000>; 3186 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3187 interrupt-controller; 3188 #interrupt-cells = <3>; 3189 #mbox-cells = <2>; 3190 }; 3191 3192 tlmm: pinctrl@f100000 { 3193 compatible = "qcom,sm8450-tlmm"; 3194 reg = <0 0x0f100000 0 0x300000>; 3195 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3196 gpio-controller; 3197 #gpio-cells = <2>; 3198 interrupt-controller; 3199 #interrupt-cells = <2>; 3200 gpio-ranges = <&tlmm 0 0 211>; 3201 wakeup-parent = <&pdc>; 3202 3203 sdc2_default_state: sdc2-default-state { 3204 clk-pins { 3205 pins = "sdc2_clk"; 3206 drive-strength = <16>; 3207 bias-disable; 3208 }; 3209 3210 cmd-pins { 3211 pins = "sdc2_cmd"; 3212 drive-strength = <16>; 3213 bias-pull-up; 3214 }; 3215 3216 data-pins { 3217 pins = "sdc2_data"; 3218 drive-strength = <16>; 3219 bias-pull-up; 3220 }; 3221 }; 3222 3223 sdc2_sleep_state: sdc2-sleep-state { 3224 clk-pins { 3225 pins = "sdc2_clk"; 3226 drive-strength = <2>; 3227 bias-disable; 3228 }; 3229 3230 cmd-pins { 3231 pins = "sdc2_cmd"; 3232 drive-strength = <2>; 3233 bias-pull-up; 3234 }; 3235 3236 data-pins { 3237 pins = "sdc2_data"; 3238 drive-strength = <2>; 3239 bias-pull-up; 3240 }; 3241 }; 3242 3243 cci0_default: cci0-default-state { 3244 /* SDA, SCL */ 3245 pins = "gpio110", "gpio111"; 3246 function = "cci_i2c"; 3247 drive-strength = <2>; 3248 bias-pull-up; 3249 }; 3250 3251 cci0_sleep: cci0-sleep-state { 3252 /* SDA, SCL */ 3253 pins = "gpio110", "gpio111"; 3254 function = "cci_i2c"; 3255 drive-strength = <2>; 3256 bias-pull-down; 3257 }; 3258 3259 cci1_default: cci1-default-state { 3260 /* SDA, SCL */ 3261 pins = "gpio112", "gpio113"; 3262 function = "cci_i2c"; 3263 drive-strength = <2>; 3264 bias-pull-up; 3265 }; 3266 3267 cci1_sleep: cci1-sleep-state { 3268 /* SDA, SCL */ 3269 pins = "gpio112", "gpio113"; 3270 function = "cci_i2c"; 3271 drive-strength = <2>; 3272 bias-pull-down; 3273 }; 3274 3275 cci2_default: cci2-default-state { 3276 /* SDA, SCL */ 3277 pins = "gpio114", "gpio115"; 3278 function = "cci_i2c"; 3279 drive-strength = <2>; 3280 bias-pull-up; 3281 }; 3282 3283 cci2_sleep: cci2-sleep-state { 3284 /* SDA, SCL */ 3285 pins = "gpio114", "gpio115"; 3286 function = "cci_i2c"; 3287 drive-strength = <2>; 3288 bias-pull-down; 3289 }; 3290 3291 cci3_default: cci3-default-state { 3292 /* SDA, SCL */ 3293 pins = "gpio208", "gpio209"; 3294 function = "cci_i2c"; 3295 drive-strength = <2>; 3296 bias-pull-up; 3297 }; 3298 3299 cci3_sleep: cci3-sleep-state { 3300 /* SDA, SCL */ 3301 pins = "gpio208", "gpio209"; 3302 function = "cci_i2c"; 3303 drive-strength = <2>; 3304 bias-pull-down; 3305 }; 3306 3307 pcie0_default_state: pcie0-default-state { 3308 perst-pins { 3309 pins = "gpio94"; 3310 function = "gpio"; 3311 drive-strength = <2>; 3312 bias-pull-down; 3313 }; 3314 3315 clkreq-pins { 3316 pins = "gpio95"; 3317 function = "pcie0_clkreqn"; 3318 drive-strength = <2>; 3319 bias-pull-up; 3320 }; 3321 3322 wake-pins { 3323 pins = "gpio96"; 3324 function = "gpio"; 3325 drive-strength = <2>; 3326 bias-pull-up; 3327 }; 3328 }; 3329 3330 pcie1_default_state: pcie1-default-state { 3331 perst-pins { 3332 pins = "gpio97"; 3333 function = "gpio"; 3334 drive-strength = <2>; 3335 bias-pull-down; 3336 }; 3337 3338 clkreq-pins { 3339 pins = "gpio98"; 3340 function = "pcie1_clkreqn"; 3341 drive-strength = <2>; 3342 bias-pull-up; 3343 }; 3344 3345 wake-pins { 3346 pins = "gpio99"; 3347 function = "gpio"; 3348 drive-strength = <2>; 3349 bias-pull-up; 3350 }; 3351 }; 3352 3353 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3354 pins = "gpio0", "gpio1"; 3355 function = "qup0"; 3356 }; 3357 3358 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3359 pins = "gpio4", "gpio5"; 3360 function = "qup1"; 3361 }; 3362 3363 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3364 pins = "gpio8", "gpio9"; 3365 function = "qup2"; 3366 }; 3367 3368 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3369 pins = "gpio12", "gpio13"; 3370 function = "qup3"; 3371 }; 3372 3373 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3374 pins = "gpio16", "gpio17"; 3375 function = "qup4"; 3376 }; 3377 3378 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3379 pins = "gpio206", "gpio207"; 3380 function = "qup5"; 3381 }; 3382 3383 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3384 pins = "gpio20", "gpio21"; 3385 function = "qup6"; 3386 }; 3387 3388 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3389 pins = "gpio28", "gpio29"; 3390 function = "qup8"; 3391 }; 3392 3393 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3394 pins = "gpio32", "gpio33"; 3395 function = "qup9"; 3396 }; 3397 3398 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3399 pins = "gpio36", "gpio37"; 3400 function = "qup10"; 3401 }; 3402 3403 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3404 pins = "gpio40", "gpio41"; 3405 function = "qup11"; 3406 }; 3407 3408 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3409 pins = "gpio44", "gpio45"; 3410 function = "qup12"; 3411 }; 3412 3413 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3414 pins = "gpio48", "gpio49"; 3415 function = "qup13"; 3416 drive-strength = <2>; 3417 bias-pull-up; 3418 }; 3419 3420 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3421 pins = "gpio52", "gpio53"; 3422 function = "qup14"; 3423 drive-strength = <2>; 3424 bias-pull-up; 3425 }; 3426 3427 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3428 pins = "gpio56", "gpio57"; 3429 function = "qup15"; 3430 }; 3431 3432 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 3433 pins = "gpio60", "gpio61"; 3434 function = "qup16"; 3435 }; 3436 3437 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 3438 pins = "gpio64", "gpio65"; 3439 function = "qup17"; 3440 }; 3441 3442 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 3443 pins = "gpio68", "gpio69"; 3444 function = "qup18"; 3445 }; 3446 3447 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 3448 pins = "gpio72", "gpio73"; 3449 function = "qup19"; 3450 }; 3451 3452 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 3453 pins = "gpio76", "gpio77"; 3454 function = "qup20"; 3455 }; 3456 3457 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 3458 pins = "gpio80", "gpio81"; 3459 function = "qup21"; 3460 }; 3461 3462 qup_spi0_cs: qup-spi0-cs-state { 3463 pins = "gpio3"; 3464 function = "qup0"; 3465 }; 3466 3467 qup_spi0_data_clk: qup-spi0-data-clk-state { 3468 pins = "gpio0", "gpio1", "gpio2"; 3469 function = "qup0"; 3470 }; 3471 3472 qup_spi1_cs: qup-spi1-cs-state { 3473 pins = "gpio7"; 3474 function = "qup1"; 3475 }; 3476 3477 qup_spi1_data_clk: qup-spi1-data-clk-state { 3478 pins = "gpio4", "gpio5", "gpio6"; 3479 function = "qup1"; 3480 }; 3481 3482 qup_spi2_cs: qup-spi2-cs-state { 3483 pins = "gpio11"; 3484 function = "qup2"; 3485 }; 3486 3487 qup_spi2_data_clk: qup-spi2-data-clk-state { 3488 pins = "gpio8", "gpio9", "gpio10"; 3489 function = "qup2"; 3490 }; 3491 3492 qup_spi3_cs: qup-spi3-cs-state { 3493 pins = "gpio15"; 3494 function = "qup3"; 3495 }; 3496 3497 qup_spi3_data_clk: qup-spi3-data-clk-state { 3498 pins = "gpio12", "gpio13", "gpio14"; 3499 function = "qup3"; 3500 }; 3501 3502 qup_spi4_cs: qup-spi4-cs-state { 3503 pins = "gpio19"; 3504 function = "qup4"; 3505 drive-strength = <6>; 3506 bias-disable; 3507 }; 3508 3509 qup_spi4_data_clk: qup-spi4-data-clk-state { 3510 pins = "gpio16", "gpio17", "gpio18"; 3511 function = "qup4"; 3512 }; 3513 3514 qup_spi5_cs: qup-spi5-cs-state { 3515 pins = "gpio85"; 3516 function = "qup5"; 3517 }; 3518 3519 qup_spi5_data_clk: qup-spi5-data-clk-state { 3520 pins = "gpio206", "gpio207", "gpio84"; 3521 function = "qup5"; 3522 }; 3523 3524 qup_spi6_cs: qup-spi6-cs-state { 3525 pins = "gpio23"; 3526 function = "qup6"; 3527 }; 3528 3529 qup_spi6_data_clk: qup-spi6-data-clk-state { 3530 pins = "gpio20", "gpio21", "gpio22"; 3531 function = "qup6"; 3532 }; 3533 3534 qup_spi8_cs: qup-spi8-cs-state { 3535 pins = "gpio31"; 3536 function = "qup8"; 3537 }; 3538 3539 qup_spi8_data_clk: qup-spi8-data-clk-state { 3540 pins = "gpio28", "gpio29", "gpio30"; 3541 function = "qup8"; 3542 }; 3543 3544 qup_spi9_cs: qup-spi9-cs-state { 3545 pins = "gpio35"; 3546 function = "qup9"; 3547 }; 3548 3549 qup_spi9_data_clk: qup-spi9-data-clk-state { 3550 pins = "gpio32", "gpio33", "gpio34"; 3551 function = "qup9"; 3552 }; 3553 3554 qup_spi10_cs: qup-spi10-cs-state { 3555 pins = "gpio39"; 3556 function = "qup10"; 3557 }; 3558 3559 qup_spi10_data_clk: qup-spi10-data-clk-state { 3560 pins = "gpio36", "gpio37", "gpio38"; 3561 function = "qup10"; 3562 }; 3563 3564 qup_spi11_cs: qup-spi11-cs-state { 3565 pins = "gpio43"; 3566 function = "qup11"; 3567 }; 3568 3569 qup_spi11_data_clk: qup-spi11-data-clk-state { 3570 pins = "gpio40", "gpio41", "gpio42"; 3571 function = "qup11"; 3572 }; 3573 3574 qup_spi12_cs: qup-spi12-cs-state { 3575 pins = "gpio47"; 3576 function = "qup12"; 3577 }; 3578 3579 qup_spi12_data_clk: qup-spi12-data-clk-state { 3580 pins = "gpio44", "gpio45", "gpio46"; 3581 function = "qup12"; 3582 }; 3583 3584 qup_spi13_cs: qup-spi13-cs-state { 3585 pins = "gpio51"; 3586 function = "qup13"; 3587 }; 3588 3589 qup_spi13_data_clk: qup-spi13-data-clk-state { 3590 pins = "gpio48", "gpio49", "gpio50"; 3591 function = "qup13"; 3592 }; 3593 3594 qup_spi14_cs: qup-spi14-cs-state { 3595 pins = "gpio55"; 3596 function = "qup14"; 3597 }; 3598 3599 qup_spi14_data_clk: qup-spi14-data-clk-state { 3600 pins = "gpio52", "gpio53", "gpio54"; 3601 function = "qup14"; 3602 }; 3603 3604 qup_spi15_cs: qup-spi15-cs-state { 3605 pins = "gpio59"; 3606 function = "qup15"; 3607 }; 3608 3609 qup_spi15_data_clk: qup-spi15-data-clk-state { 3610 pins = "gpio56", "gpio57", "gpio58"; 3611 function = "qup15"; 3612 }; 3613 3614 qup_spi16_cs: qup-spi16-cs-state { 3615 pins = "gpio63"; 3616 function = "qup16"; 3617 }; 3618 3619 qup_spi16_data_clk: qup-spi16-data-clk-state { 3620 pins = "gpio60", "gpio61", "gpio62"; 3621 function = "qup16"; 3622 }; 3623 3624 qup_spi17_cs: qup-spi17-cs-state { 3625 pins = "gpio67"; 3626 function = "qup17"; 3627 }; 3628 3629 qup_spi17_data_clk: qup-spi17-data-clk-state { 3630 pins = "gpio64", "gpio65", "gpio66"; 3631 function = "qup17"; 3632 }; 3633 3634 qup_spi18_cs: qup-spi18-cs-state { 3635 pins = "gpio71"; 3636 function = "qup18"; 3637 drive-strength = <6>; 3638 bias-disable; 3639 }; 3640 3641 qup_spi18_data_clk: qup-spi18-data-clk-state { 3642 pins = "gpio68", "gpio69", "gpio70"; 3643 function = "qup18"; 3644 drive-strength = <6>; 3645 bias-disable; 3646 }; 3647 3648 qup_spi19_cs: qup-spi19-cs-state { 3649 pins = "gpio75"; 3650 function = "qup19"; 3651 drive-strength = <6>; 3652 bias-disable; 3653 }; 3654 3655 qup_spi19_data_clk: qup-spi19-data-clk-state { 3656 pins = "gpio72", "gpio73", "gpio74"; 3657 function = "qup19"; 3658 drive-strength = <6>; 3659 bias-disable; 3660 }; 3661 3662 qup_spi20_cs: qup-spi20-cs-state { 3663 pins = "gpio79"; 3664 function = "qup20"; 3665 }; 3666 3667 qup_spi20_data_clk: qup-spi20-data-clk-state { 3668 pins = "gpio76", "gpio77", "gpio78"; 3669 function = "qup20"; 3670 }; 3671 3672 qup_spi21_cs: qup-spi21-cs-state { 3673 pins = "gpio83"; 3674 function = "qup21"; 3675 }; 3676 3677 qup_spi21_data_clk: qup-spi21-data-clk-state { 3678 pins = "gpio80", "gpio81", "gpio82"; 3679 function = "qup21"; 3680 }; 3681 3682 qup_uart7_rx: qup-uart7-rx-state { 3683 pins = "gpio26"; 3684 function = "qup7"; 3685 drive-strength = <2>; 3686 bias-disable; 3687 }; 3688 3689 qup_uart7_tx: qup-uart7-tx-state { 3690 pins = "gpio27"; 3691 function = "qup7"; 3692 drive-strength = <2>; 3693 bias-disable; 3694 }; 3695 3696 qup_uart20_default: qup-uart20-default-state { 3697 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 3698 function = "qup20"; 3699 }; 3700 }; 3701 3702 lpass_tlmm: pinctrl@3440000 { 3703 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 3704 reg = <0 0x03440000 0x0 0x20000>, 3705 <0 0x034d0000 0x0 0x10000>; 3706 gpio-controller; 3707 #gpio-cells = <2>; 3708 gpio-ranges = <&lpass_tlmm 0 0 23>; 3709 3710 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3711 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3712 clock-names = "core", "audio"; 3713 3714 tx_swr_active: tx-swr-active-state { 3715 clk-pins { 3716 pins = "gpio0"; 3717 function = "swr_tx_clk"; 3718 drive-strength = <2>; 3719 slew-rate = <1>; 3720 bias-disable; 3721 }; 3722 3723 data-pins { 3724 pins = "gpio1", "gpio2", "gpio14"; 3725 function = "swr_tx_data"; 3726 drive-strength = <2>; 3727 slew-rate = <1>; 3728 bias-bus-hold; 3729 }; 3730 }; 3731 3732 rx_swr_active: rx-swr-active-state { 3733 clk-pins { 3734 pins = "gpio3"; 3735 function = "swr_rx_clk"; 3736 drive-strength = <2>; 3737 slew-rate = <1>; 3738 bias-disable; 3739 }; 3740 3741 data-pins { 3742 pins = "gpio4", "gpio5"; 3743 function = "swr_rx_data"; 3744 drive-strength = <2>; 3745 slew-rate = <1>; 3746 bias-bus-hold; 3747 }; 3748 }; 3749 3750 dmic01_default: dmic01-default-state { 3751 clk-pins { 3752 pins = "gpio6"; 3753 function = "dmic1_clk"; 3754 drive-strength = <8>; 3755 output-high; 3756 }; 3757 3758 data-pins { 3759 pins = "gpio7"; 3760 function = "dmic1_data"; 3761 drive-strength = <8>; 3762 }; 3763 }; 3764 3765 dmic02_default: dmic02-default-state { 3766 clk-pins { 3767 pins = "gpio8"; 3768 function = "dmic2_clk"; 3769 drive-strength = <8>; 3770 output-high; 3771 }; 3772 3773 data-pins { 3774 pins = "gpio9"; 3775 function = "dmic2_data"; 3776 drive-strength = <8>; 3777 }; 3778 }; 3779 3780 wsa_swr_active: wsa-swr-active-state { 3781 clk-pins { 3782 pins = "gpio10"; 3783 function = "wsa_swr_clk"; 3784 drive-strength = <2>; 3785 slew-rate = <1>; 3786 bias-disable; 3787 }; 3788 3789 data-pins { 3790 pins = "gpio11"; 3791 function = "wsa_swr_data"; 3792 drive-strength = <2>; 3793 slew-rate = <1>; 3794 bias-bus-hold; 3795 }; 3796 }; 3797 3798 wsa2_swr_active: wsa2-swr-active-state { 3799 clk-pins { 3800 pins = "gpio15"; 3801 function = "wsa2_swr_clk"; 3802 drive-strength = <2>; 3803 slew-rate = <1>; 3804 bias-disable; 3805 }; 3806 3807 data-pins { 3808 pins = "gpio16"; 3809 function = "wsa2_swr_data"; 3810 drive-strength = <2>; 3811 slew-rate = <1>; 3812 bias-bus-hold; 3813 }; 3814 }; 3815 }; 3816 3817 sram@146aa000 { 3818 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; 3819 reg = <0 0x146aa000 0 0x1000>; 3820 ranges = <0 0 0x146aa000 0x1000>; 3821 3822 #address-cells = <1>; 3823 #size-cells = <1>; 3824 3825 pil-reloc@94c { 3826 compatible = "qcom,pil-reloc-info"; 3827 reg = <0x94c 0xc8>; 3828 }; 3829 }; 3830 3831 apps_smmu: iommu@15000000 { 3832 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 3833 reg = <0 0x15000000 0 0x100000>; 3834 #iommu-cells = <2>; 3835 #global-interrupts = <1>; 3836 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3837 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3838 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3839 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3840 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3841 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3842 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3843 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3845 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3846 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3853 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3854 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3855 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3856 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3857 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3858 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3859 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3860 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3861 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3862 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3863 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3864 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3865 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3866 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3867 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3868 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3869 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3870 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3871 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3872 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3873 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3874 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3875 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3876 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3877 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3878 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3879 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3880 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3881 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3882 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3883 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3884 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3885 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3886 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3887 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3888 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3889 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3890 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3891 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3892 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3893 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3894 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3895 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3896 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3897 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3898 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3899 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3900 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3901 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3902 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3903 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3904 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3905 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3906 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3907 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3908 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3909 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3910 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3911 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3912 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3913 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3914 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3915 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3916 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3917 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3918 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3919 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3920 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3921 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3922 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3923 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3924 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3925 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3926 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3927 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3928 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3929 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3930 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3931 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3932 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 3933 }; 3934 3935 intc: interrupt-controller@17100000 { 3936 compatible = "arm,gic-v3"; 3937 #interrupt-cells = <3>; 3938 interrupt-controller; 3939 #redistributor-regions = <1>; 3940 redistributor-stride = <0x0 0x40000>; 3941 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 3942 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 3943 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3944 #address-cells = <2>; 3945 #size-cells = <2>; 3946 ranges; 3947 3948 gic_its: msi-controller@17140000 { 3949 compatible = "arm,gic-v3-its"; 3950 reg = <0x0 0x17140000 0x0 0x20000>; 3951 msi-controller; 3952 #msi-cells = <1>; 3953 }; 3954 }; 3955 3956 timer@17420000 { 3957 compatible = "arm,armv7-timer-mem"; 3958 #address-cells = <1>; 3959 #size-cells = <1>; 3960 ranges = <0 0 0 0x20000000>; 3961 reg = <0x0 0x17420000 0x0 0x1000>; 3962 clock-frequency = <19200000>; 3963 3964 frame@17421000 { 3965 frame-number = <0>; 3966 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3967 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3968 reg = <0x17421000 0x1000>, 3969 <0x17422000 0x1000>; 3970 }; 3971 3972 frame@17423000 { 3973 frame-number = <1>; 3974 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3975 reg = <0x17423000 0x1000>; 3976 status = "disabled"; 3977 }; 3978 3979 frame@17425000 { 3980 frame-number = <2>; 3981 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3982 reg = <0x17425000 0x1000>; 3983 status = "disabled"; 3984 }; 3985 3986 frame@17427000 { 3987 frame-number = <3>; 3988 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3989 reg = <0x17427000 0x1000>; 3990 status = "disabled"; 3991 }; 3992 3993 frame@17429000 { 3994 frame-number = <4>; 3995 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3996 reg = <0x17429000 0x1000>; 3997 status = "disabled"; 3998 }; 3999 4000 frame@1742b000 { 4001 frame-number = <5>; 4002 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4003 reg = <0x1742b000 0x1000>; 4004 status = "disabled"; 4005 }; 4006 4007 frame@1742d000 { 4008 frame-number = <6>; 4009 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4010 reg = <0x1742d000 0x1000>; 4011 status = "disabled"; 4012 }; 4013 }; 4014 4015 apps_rsc: rsc@17a00000 { 4016 label = "apps_rsc"; 4017 compatible = "qcom,rpmh-rsc"; 4018 reg = <0x0 0x17a00000 0x0 0x10000>, 4019 <0x0 0x17a10000 0x0 0x10000>, 4020 <0x0 0x17a20000 0x0 0x10000>, 4021 <0x0 0x17a30000 0x0 0x10000>; 4022 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 4023 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4024 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4025 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4026 qcom,tcs-offset = <0xd00>; 4027 qcom,drv-id = <2>; 4028 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4029 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4030 power-domains = <&CLUSTER_PD>; 4031 4032 apps_bcm_voter: bcm-voter { 4033 compatible = "qcom,bcm-voter"; 4034 }; 4035 4036 rpmhcc: clock-controller { 4037 compatible = "qcom,sm8450-rpmh-clk"; 4038 #clock-cells = <1>; 4039 clock-names = "xo"; 4040 clocks = <&xo_board>; 4041 }; 4042 4043 rpmhpd: power-controller { 4044 compatible = "qcom,sm8450-rpmhpd"; 4045 #power-domain-cells = <1>; 4046 operating-points-v2 = <&rpmhpd_opp_table>; 4047 4048 rpmhpd_opp_table: opp-table { 4049 compatible = "operating-points-v2"; 4050 4051 rpmhpd_opp_ret: opp1 { 4052 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4053 }; 4054 4055 rpmhpd_opp_min_svs: opp2 { 4056 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4057 }; 4058 4059 rpmhpd_opp_low_svs_d1: opp3 { 4060 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4061 }; 4062 4063 rpmhpd_opp_low_svs: opp4 { 4064 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4065 }; 4066 4067 rpmhpd_opp_low_svs_l1: opp5 { 4068 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4069 }; 4070 4071 rpmhpd_opp_svs: opp6 { 4072 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4073 }; 4074 4075 rpmhpd_opp_svs_l0: opp7 { 4076 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4077 }; 4078 4079 rpmhpd_opp_svs_l1: opp8 { 4080 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4081 }; 4082 4083 rpmhpd_opp_svs_l2: opp9 { 4084 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4085 }; 4086 4087 rpmhpd_opp_nom: opp10 { 4088 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4089 }; 4090 4091 rpmhpd_opp_nom_l1: opp11 { 4092 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4093 }; 4094 4095 rpmhpd_opp_nom_l2: opp12 { 4096 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4097 }; 4098 4099 rpmhpd_opp_turbo: opp13 { 4100 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4101 }; 4102 4103 rpmhpd_opp_turbo_l1: opp14 { 4104 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4105 }; 4106 }; 4107 }; 4108 }; 4109 4110 cpufreq_hw: cpufreq@17d91000 { 4111 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 4112 reg = <0 0x17d91000 0 0x1000>, 4113 <0 0x17d92000 0 0x1000>, 4114 <0 0x17d93000 0 0x1000>; 4115 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4116 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4117 clock-names = "xo", "alternate"; 4118 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4121 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4122 #freq-domain-cells = <1>; 4123 #clock-cells = <1>; 4124 }; 4125 4126 gem_noc: interconnect@19100000 { 4127 compatible = "qcom,sm8450-gem-noc"; 4128 reg = <0 0x19100000 0 0xbb800>; 4129 #interconnect-cells = <2>; 4130 qcom,bcm-voters = <&apps_bcm_voter>; 4131 }; 4132 4133 system-cache-controller@19200000 { 4134 compatible = "qcom,sm8450-llcc"; 4135 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, 4136 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, 4137 <0 0x19a00000 0 0x80000>; 4138 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4139 "llcc3_base", "llcc_broadcast_base"; 4140 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4141 }; 4142 4143 ufs_mem_hc: ufshc@1d84000 { 4144 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 4145 "jedec,ufs-2.0"; 4146 reg = <0 0x01d84000 0 0x3000>; 4147 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 4148 phys = <&ufs_mem_phy_lanes>; 4149 phy-names = "ufsphy"; 4150 lanes-per-direction = <2>; 4151 #reset-cells = <1>; 4152 resets = <&gcc GCC_UFS_PHY_BCR>; 4153 reset-names = "rst"; 4154 4155 power-domains = <&gcc UFS_PHY_GDSC>; 4156 4157 iommus = <&apps_smmu 0xe0 0x0>; 4158 dma-coherent; 4159 4160 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 4161 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 4162 interconnect-names = "ufs-ddr", "cpu-ufs"; 4163 clock-names = 4164 "core_clk", 4165 "bus_aggr_clk", 4166 "iface_clk", 4167 "core_clk_unipro", 4168 "ref_clk", 4169 "tx_lane0_sync_clk", 4170 "rx_lane0_sync_clk", 4171 "rx_lane1_sync_clk"; 4172 clocks = 4173 <&gcc GCC_UFS_PHY_AXI_CLK>, 4174 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 4175 <&gcc GCC_UFS_PHY_AHB_CLK>, 4176 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 4177 <&rpmhcc RPMH_CXO_CLK>, 4178 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 4179 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 4180 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 4181 freq-table-hz = 4182 <75000000 300000000>, 4183 <0 0>, 4184 <0 0>, 4185 <75000000 300000000>, 4186 <75000000 300000000>, 4187 <0 0>, 4188 <0 0>, 4189 <0 0>; 4190 qcom,ice = <&ice>; 4191 4192 status = "disabled"; 4193 }; 4194 4195 ufs_mem_phy: phy@1d87000 { 4196 compatible = "qcom,sm8450-qmp-ufs-phy"; 4197 reg = <0 0x01d87000 0 0x1c4>; 4198 #address-cells = <2>; 4199 #size-cells = <2>; 4200 ranges; 4201 clock-names = "ref", "ref_aux", "qref"; 4202 clocks = <&rpmhcc RPMH_CXO_CLK>, 4203 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 4204 <&gcc GCC_UFS_0_CLKREF_EN>; 4205 4206 power-domains = <&gcc UFS_PHY_GDSC>; 4207 4208 resets = <&ufs_mem_hc 0>; 4209 reset-names = "ufsphy"; 4210 status = "disabled"; 4211 4212 ufs_mem_phy_lanes: phy@1d87400 { 4213 reg = <0 0x01d87400 0 0x188>, 4214 <0 0x01d87600 0 0x200>, 4215 <0 0x01d87c00 0 0x200>, 4216 <0 0x01d87800 0 0x188>, 4217 <0 0x01d87a00 0 0x200>; 4218 #clock-cells = <1>; 4219 #phy-cells = <0>; 4220 }; 4221 }; 4222 4223 ice: crypto@1d88000 { 4224 compatible = "qcom,sm8450-inline-crypto-engine", 4225 "qcom,inline-crypto-engine"; 4226 reg = <0 0x01d88000 0 0x8000>; 4227 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4228 }; 4229 4230 cryptobam: dma-controller@1dc4000 { 4231 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 4232 reg = <0 0x01dc4000 0 0x28000>; 4233 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 4234 #dma-cells = <1>; 4235 qcom,ee = <0>; 4236 qcom,num-ees = <4>; 4237 num-channels = <16>; 4238 qcom,controlled-remotely; 4239 iommus = <&apps_smmu 0x584 0x11>, 4240 <&apps_smmu 0x588 0x0>, 4241 <&apps_smmu 0x598 0x5>, 4242 <&apps_smmu 0x59a 0x0>, 4243 <&apps_smmu 0x59f 0x0>; 4244 }; 4245 4246 crypto: crypto@1dfa000 { 4247 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; 4248 reg = <0 0x01dfa000 0 0x6000>; 4249 dmas = <&cryptobam 4>, <&cryptobam 5>; 4250 dma-names = "rx", "tx"; 4251 iommus = <&apps_smmu 0x584 0x11>, 4252 <&apps_smmu 0x588 0x0>, 4253 <&apps_smmu 0x598 0x5>, 4254 <&apps_smmu 0x59a 0x0>, 4255 <&apps_smmu 0x59f 0x0>; 4256 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 4257 interconnect-names = "memory"; 4258 }; 4259 4260 sdhc_2: mmc@8804000 { 4261 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 4262 reg = <0 0x08804000 0 0x1000>; 4263 4264 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4265 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4266 interrupt-names = "hc_irq", "pwr_irq"; 4267 4268 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4269 <&gcc GCC_SDCC2_APPS_CLK>, 4270 <&rpmhcc RPMH_CXO_CLK>; 4271 clock-names = "iface", "core", "xo"; 4272 resets = <&gcc GCC_SDCC2_BCR>; 4273 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4274 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 4275 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4276 iommus = <&apps_smmu 0x4a0 0x0>; 4277 power-domains = <&rpmhpd RPMHPD_CX>; 4278 operating-points-v2 = <&sdhc2_opp_table>; 4279 bus-width = <4>; 4280 dma-coherent; 4281 4282 /* Forbid SDR104/SDR50 - broken hw! */ 4283 sdhci-caps-mask = <0x3 0x0>; 4284 4285 status = "disabled"; 4286 4287 sdhc2_opp_table: opp-table { 4288 compatible = "operating-points-v2"; 4289 4290 opp-100000000 { 4291 opp-hz = /bits/ 64 <100000000>; 4292 required-opps = <&rpmhpd_opp_low_svs>; 4293 }; 4294 4295 opp-202000000 { 4296 opp-hz = /bits/ 64 <202000000>; 4297 required-opps = <&rpmhpd_opp_svs_l1>; 4298 }; 4299 }; 4300 }; 4301 4302 usb_1: usb@a6f8800 { 4303 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 4304 reg = <0 0x0a6f8800 0 0x400>; 4305 status = "disabled"; 4306 #address-cells = <2>; 4307 #size-cells = <2>; 4308 ranges; 4309 4310 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4311 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4312 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4313 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4314 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4315 <&gcc GCC_USB3_0_CLKREF_EN>; 4316 clock-names = "cfg_noc", 4317 "core", 4318 "iface", 4319 "sleep", 4320 "mock_utmi", 4321 "xo"; 4322 4323 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4324 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4325 assigned-clock-rates = <19200000>, <200000000>; 4326 4327 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4328 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 4329 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4330 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 4331 interrupt-names = "hs_phy_irq", 4332 "ss_phy_irq", 4333 "dm_hs_phy_irq", 4334 "dp_hs_phy_irq"; 4335 4336 power-domains = <&gcc USB30_PRIM_GDSC>; 4337 4338 resets = <&gcc GCC_USB30_PRIM_BCR>; 4339 4340 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4341 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4342 interconnect-names = "usb-ddr", "apps-usb"; 4343 4344 usb_1_dwc3: usb@a600000 { 4345 compatible = "snps,dwc3"; 4346 reg = <0 0x0a600000 0 0xcd00>; 4347 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4348 iommus = <&apps_smmu 0x0 0x0>; 4349 snps,dis_u2_susphy_quirk; 4350 snps,dis_enblslpm_quirk; 4351 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4352 phy-names = "usb2-phy", "usb3-phy"; 4353 4354 ports { 4355 #address-cells = <1>; 4356 #size-cells = <0>; 4357 4358 port@0 { 4359 reg = <0>; 4360 4361 usb_1_dwc3_hs: endpoint { 4362 }; 4363 }; 4364 4365 port@1 { 4366 reg = <1>; 4367 4368 usb_1_dwc3_ss: endpoint { 4369 }; 4370 }; 4371 }; 4372 }; 4373 }; 4374 4375 nsp_noc: interconnect@320c0000 { 4376 compatible = "qcom,sm8450-nsp-noc"; 4377 reg = <0 0x320c0000 0 0x10000>; 4378 #interconnect-cells = <2>; 4379 qcom,bcm-voters = <&apps_bcm_voter>; 4380 }; 4381 4382 lpass_ag_noc: interconnect@3c40000 { 4383 compatible = "qcom,sm8450-lpass-ag-noc"; 4384 reg = <0 0x03c40000 0 0x17200>; 4385 #interconnect-cells = <2>; 4386 qcom,bcm-voters = <&apps_bcm_voter>; 4387 }; 4388 }; 4389 4390 sound: sound { 4391 }; 4392 4393 thermal-zones { 4394 aoss0-thermal { 4395 polling-delay-passive = <0>; 4396 polling-delay = <0>; 4397 thermal-sensors = <&tsens0 0>; 4398 4399 trips { 4400 thermal-engine-config { 4401 temperature = <125000>; 4402 hysteresis = <1000>; 4403 type = "passive"; 4404 }; 4405 4406 reset-mon-cfg { 4407 temperature = <115000>; 4408 hysteresis = <5000>; 4409 type = "passive"; 4410 }; 4411 }; 4412 }; 4413 4414 cpuss0-thermal { 4415 polling-delay-passive = <0>; 4416 polling-delay = <0>; 4417 thermal-sensors = <&tsens0 1>; 4418 4419 trips { 4420 thermal-engine-config { 4421 temperature = <125000>; 4422 hysteresis = <1000>; 4423 type = "passive"; 4424 }; 4425 4426 reset-mon-cfg { 4427 temperature = <115000>; 4428 hysteresis = <5000>; 4429 type = "passive"; 4430 }; 4431 }; 4432 }; 4433 4434 cpuss1-thermal { 4435 polling-delay-passive = <0>; 4436 polling-delay = <0>; 4437 thermal-sensors = <&tsens0 2>; 4438 4439 trips { 4440 thermal-engine-config { 4441 temperature = <125000>; 4442 hysteresis = <1000>; 4443 type = "passive"; 4444 }; 4445 4446 reset-mon-cfg { 4447 temperature = <115000>; 4448 hysteresis = <5000>; 4449 type = "passive"; 4450 }; 4451 }; 4452 }; 4453 4454 cpuss3-thermal { 4455 polling-delay-passive = <0>; 4456 polling-delay = <0>; 4457 thermal-sensors = <&tsens0 3>; 4458 4459 trips { 4460 thermal-engine-config { 4461 temperature = <125000>; 4462 hysteresis = <1000>; 4463 type = "passive"; 4464 }; 4465 4466 reset-mon-cfg { 4467 temperature = <115000>; 4468 hysteresis = <5000>; 4469 type = "passive"; 4470 }; 4471 }; 4472 }; 4473 4474 cpuss4-thermal { 4475 polling-delay-passive = <0>; 4476 polling-delay = <0>; 4477 thermal-sensors = <&tsens0 4>; 4478 4479 trips { 4480 thermal-engine-config { 4481 temperature = <125000>; 4482 hysteresis = <1000>; 4483 type = "passive"; 4484 }; 4485 4486 reset-mon-cfg { 4487 temperature = <115000>; 4488 hysteresis = <5000>; 4489 type = "passive"; 4490 }; 4491 }; 4492 }; 4493 4494 cpu4-top-thermal { 4495 polling-delay-passive = <0>; 4496 polling-delay = <0>; 4497 thermal-sensors = <&tsens0 5>; 4498 4499 trips { 4500 cpu4_top_alert0: trip-point0 { 4501 temperature = <90000>; 4502 hysteresis = <2000>; 4503 type = "passive"; 4504 }; 4505 4506 cpu4_top_alert1: trip-point1 { 4507 temperature = <95000>; 4508 hysteresis = <2000>; 4509 type = "passive"; 4510 }; 4511 4512 cpu4_top_crit: cpu-crit { 4513 temperature = <110000>; 4514 hysteresis = <1000>; 4515 type = "critical"; 4516 }; 4517 }; 4518 }; 4519 4520 cpu4-bottom-thermal { 4521 polling-delay-passive = <0>; 4522 polling-delay = <0>; 4523 thermal-sensors = <&tsens0 6>; 4524 4525 trips { 4526 cpu4_bottom_alert0: trip-point0 { 4527 temperature = <90000>; 4528 hysteresis = <2000>; 4529 type = "passive"; 4530 }; 4531 4532 cpu4_bottom_alert1: trip-point1 { 4533 temperature = <95000>; 4534 hysteresis = <2000>; 4535 type = "passive"; 4536 }; 4537 4538 cpu4_bottom_crit: cpu-crit { 4539 temperature = <110000>; 4540 hysteresis = <1000>; 4541 type = "critical"; 4542 }; 4543 }; 4544 }; 4545 4546 cpu5-top-thermal { 4547 polling-delay-passive = <0>; 4548 polling-delay = <0>; 4549 thermal-sensors = <&tsens0 7>; 4550 4551 trips { 4552 cpu5_top_alert0: trip-point0 { 4553 temperature = <90000>; 4554 hysteresis = <2000>; 4555 type = "passive"; 4556 }; 4557 4558 cpu5_top_alert1: trip-point1 { 4559 temperature = <95000>; 4560 hysteresis = <2000>; 4561 type = "passive"; 4562 }; 4563 4564 cpu5_top_crit: cpu-crit { 4565 temperature = <110000>; 4566 hysteresis = <1000>; 4567 type = "critical"; 4568 }; 4569 }; 4570 }; 4571 4572 cpu5-bottom-thermal { 4573 polling-delay-passive = <0>; 4574 polling-delay = <0>; 4575 thermal-sensors = <&tsens0 8>; 4576 4577 trips { 4578 cpu5_bottom_alert0: trip-point0 { 4579 temperature = <90000>; 4580 hysteresis = <2000>; 4581 type = "passive"; 4582 }; 4583 4584 cpu5_bottom_alert1: trip-point1 { 4585 temperature = <95000>; 4586 hysteresis = <2000>; 4587 type = "passive"; 4588 }; 4589 4590 cpu5_bottom_crit: cpu-crit { 4591 temperature = <110000>; 4592 hysteresis = <1000>; 4593 type = "critical"; 4594 }; 4595 }; 4596 }; 4597 4598 cpu6-top-thermal { 4599 polling-delay-passive = <0>; 4600 polling-delay = <0>; 4601 thermal-sensors = <&tsens0 9>; 4602 4603 trips { 4604 cpu6_top_alert0: trip-point0 { 4605 temperature = <90000>; 4606 hysteresis = <2000>; 4607 type = "passive"; 4608 }; 4609 4610 cpu6_top_alert1: trip-point1 { 4611 temperature = <95000>; 4612 hysteresis = <2000>; 4613 type = "passive"; 4614 }; 4615 4616 cpu6_top_crit: cpu-crit { 4617 temperature = <110000>; 4618 hysteresis = <1000>; 4619 type = "critical"; 4620 }; 4621 }; 4622 }; 4623 4624 cpu6-bottom-thermal { 4625 polling-delay-passive = <0>; 4626 polling-delay = <0>; 4627 thermal-sensors = <&tsens0 10>; 4628 4629 trips { 4630 cpu6_bottom_alert0: trip-point0 { 4631 temperature = <90000>; 4632 hysteresis = <2000>; 4633 type = "passive"; 4634 }; 4635 4636 cpu6_bottom_alert1: trip-point1 { 4637 temperature = <95000>; 4638 hysteresis = <2000>; 4639 type = "passive"; 4640 }; 4641 4642 cpu6_bottom_crit: cpu-crit { 4643 temperature = <110000>; 4644 hysteresis = <1000>; 4645 type = "critical"; 4646 }; 4647 }; 4648 }; 4649 4650 cpu7-top-thermal { 4651 polling-delay-passive = <0>; 4652 polling-delay = <0>; 4653 thermal-sensors = <&tsens0 11>; 4654 4655 trips { 4656 cpu7_top_alert0: trip-point0 { 4657 temperature = <90000>; 4658 hysteresis = <2000>; 4659 type = "passive"; 4660 }; 4661 4662 cpu7_top_alert1: trip-point1 { 4663 temperature = <95000>; 4664 hysteresis = <2000>; 4665 type = "passive"; 4666 }; 4667 4668 cpu7_top_crit: cpu-crit { 4669 temperature = <110000>; 4670 hysteresis = <1000>; 4671 type = "critical"; 4672 }; 4673 }; 4674 }; 4675 4676 cpu7-middle-thermal { 4677 polling-delay-passive = <0>; 4678 polling-delay = <0>; 4679 thermal-sensors = <&tsens0 12>; 4680 4681 trips { 4682 cpu7_middle_alert0: trip-point0 { 4683 temperature = <90000>; 4684 hysteresis = <2000>; 4685 type = "passive"; 4686 }; 4687 4688 cpu7_middle_alert1: trip-point1 { 4689 temperature = <95000>; 4690 hysteresis = <2000>; 4691 type = "passive"; 4692 }; 4693 4694 cpu7_middle_crit: cpu-crit { 4695 temperature = <110000>; 4696 hysteresis = <1000>; 4697 type = "critical"; 4698 }; 4699 }; 4700 }; 4701 4702 cpu7-bottom-thermal { 4703 polling-delay-passive = <0>; 4704 polling-delay = <0>; 4705 thermal-sensors = <&tsens0 13>; 4706 4707 trips { 4708 cpu7_bottom_alert0: trip-point0 { 4709 temperature = <90000>; 4710 hysteresis = <2000>; 4711 type = "passive"; 4712 }; 4713 4714 cpu7_bottom_alert1: trip-point1 { 4715 temperature = <95000>; 4716 hysteresis = <2000>; 4717 type = "passive"; 4718 }; 4719 4720 cpu7_bottom_crit: cpu-crit { 4721 temperature = <110000>; 4722 hysteresis = <1000>; 4723 type = "critical"; 4724 }; 4725 }; 4726 }; 4727 4728 gpu-top-thermal { 4729 polling-delay-passive = <10>; 4730 polling-delay = <0>; 4731 thermal-sensors = <&tsens0 14>; 4732 4733 trips { 4734 thermal-engine-config { 4735 temperature = <125000>; 4736 hysteresis = <1000>; 4737 type = "passive"; 4738 }; 4739 4740 thermal-hal-config { 4741 temperature = <125000>; 4742 hysteresis = <1000>; 4743 type = "passive"; 4744 }; 4745 4746 reset-mon-cfg { 4747 temperature = <115000>; 4748 hysteresis = <5000>; 4749 type = "passive"; 4750 }; 4751 4752 gpu0_tj_cfg: tj-cfg { 4753 temperature = <95000>; 4754 hysteresis = <5000>; 4755 type = "passive"; 4756 }; 4757 }; 4758 }; 4759 4760 gpu-bottom-thermal { 4761 polling-delay-passive = <10>; 4762 polling-delay = <0>; 4763 thermal-sensors = <&tsens0 15>; 4764 4765 trips { 4766 thermal-engine-config { 4767 temperature = <125000>; 4768 hysteresis = <1000>; 4769 type = "passive"; 4770 }; 4771 4772 thermal-hal-config { 4773 temperature = <125000>; 4774 hysteresis = <1000>; 4775 type = "passive"; 4776 }; 4777 4778 reset-mon-cfg { 4779 temperature = <115000>; 4780 hysteresis = <5000>; 4781 type = "passive"; 4782 }; 4783 4784 gpu1_tj_cfg: tj-cfg { 4785 temperature = <95000>; 4786 hysteresis = <5000>; 4787 type = "passive"; 4788 }; 4789 }; 4790 }; 4791 4792 aoss1-thermal { 4793 polling-delay-passive = <0>; 4794 polling-delay = <0>; 4795 thermal-sensors = <&tsens1 0>; 4796 4797 trips { 4798 thermal-engine-config { 4799 temperature = <125000>; 4800 hysteresis = <1000>; 4801 type = "passive"; 4802 }; 4803 4804 reset-mon-cfg { 4805 temperature = <115000>; 4806 hysteresis = <5000>; 4807 type = "passive"; 4808 }; 4809 }; 4810 }; 4811 4812 cpu0-thermal { 4813 polling-delay-passive = <0>; 4814 polling-delay = <0>; 4815 thermal-sensors = <&tsens1 1>; 4816 4817 trips { 4818 cpu0_alert0: trip-point0 { 4819 temperature = <90000>; 4820 hysteresis = <2000>; 4821 type = "passive"; 4822 }; 4823 4824 cpu0_alert1: trip-point1 { 4825 temperature = <95000>; 4826 hysteresis = <2000>; 4827 type = "passive"; 4828 }; 4829 4830 cpu0_crit: cpu-crit { 4831 temperature = <110000>; 4832 hysteresis = <1000>; 4833 type = "critical"; 4834 }; 4835 }; 4836 }; 4837 4838 cpu1-thermal { 4839 polling-delay-passive = <0>; 4840 polling-delay = <0>; 4841 thermal-sensors = <&tsens1 2>; 4842 4843 trips { 4844 cpu1_alert0: trip-point0 { 4845 temperature = <90000>; 4846 hysteresis = <2000>; 4847 type = "passive"; 4848 }; 4849 4850 cpu1_alert1: trip-point1 { 4851 temperature = <95000>; 4852 hysteresis = <2000>; 4853 type = "passive"; 4854 }; 4855 4856 cpu1_crit: cpu-crit { 4857 temperature = <110000>; 4858 hysteresis = <1000>; 4859 type = "critical"; 4860 }; 4861 }; 4862 }; 4863 4864 cpu2-thermal { 4865 polling-delay-passive = <0>; 4866 polling-delay = <0>; 4867 thermal-sensors = <&tsens1 3>; 4868 4869 trips { 4870 cpu2_alert0: trip-point0 { 4871 temperature = <90000>; 4872 hysteresis = <2000>; 4873 type = "passive"; 4874 }; 4875 4876 cpu2_alert1: trip-point1 { 4877 temperature = <95000>; 4878 hysteresis = <2000>; 4879 type = "passive"; 4880 }; 4881 4882 cpu2_crit: cpu-crit { 4883 temperature = <110000>; 4884 hysteresis = <1000>; 4885 type = "critical"; 4886 }; 4887 }; 4888 }; 4889 4890 cpu3-thermal { 4891 polling-delay-passive = <0>; 4892 polling-delay = <0>; 4893 thermal-sensors = <&tsens1 4>; 4894 4895 trips { 4896 cpu3_alert0: trip-point0 { 4897 temperature = <90000>; 4898 hysteresis = <2000>; 4899 type = "passive"; 4900 }; 4901 4902 cpu3_alert1: trip-point1 { 4903 temperature = <95000>; 4904 hysteresis = <2000>; 4905 type = "passive"; 4906 }; 4907 4908 cpu3_crit: cpu-crit { 4909 temperature = <110000>; 4910 hysteresis = <1000>; 4911 type = "critical"; 4912 }; 4913 }; 4914 }; 4915 4916 cdsp0-thermal { 4917 polling-delay-passive = <10>; 4918 polling-delay = <0>; 4919 thermal-sensors = <&tsens1 5>; 4920 4921 trips { 4922 thermal-engine-config { 4923 temperature = <125000>; 4924 hysteresis = <1000>; 4925 type = "passive"; 4926 }; 4927 4928 thermal-hal-config { 4929 temperature = <125000>; 4930 hysteresis = <1000>; 4931 type = "passive"; 4932 }; 4933 4934 reset-mon-cfg { 4935 temperature = <115000>; 4936 hysteresis = <5000>; 4937 type = "passive"; 4938 }; 4939 4940 cdsp_0_config: junction-config { 4941 temperature = <95000>; 4942 hysteresis = <5000>; 4943 type = "passive"; 4944 }; 4945 }; 4946 }; 4947 4948 cdsp1-thermal { 4949 polling-delay-passive = <10>; 4950 polling-delay = <0>; 4951 thermal-sensors = <&tsens1 6>; 4952 4953 trips { 4954 thermal-engine-config { 4955 temperature = <125000>; 4956 hysteresis = <1000>; 4957 type = "passive"; 4958 }; 4959 4960 thermal-hal-config { 4961 temperature = <125000>; 4962 hysteresis = <1000>; 4963 type = "passive"; 4964 }; 4965 4966 reset-mon-cfg { 4967 temperature = <115000>; 4968 hysteresis = <5000>; 4969 type = "passive"; 4970 }; 4971 4972 cdsp_1_config: junction-config { 4973 temperature = <95000>; 4974 hysteresis = <5000>; 4975 type = "passive"; 4976 }; 4977 }; 4978 }; 4979 4980 cdsp2-thermal { 4981 polling-delay-passive = <10>; 4982 polling-delay = <0>; 4983 thermal-sensors = <&tsens1 7>; 4984 4985 trips { 4986 thermal-engine-config { 4987 temperature = <125000>; 4988 hysteresis = <1000>; 4989 type = "passive"; 4990 }; 4991 4992 thermal-hal-config { 4993 temperature = <125000>; 4994 hysteresis = <1000>; 4995 type = "passive"; 4996 }; 4997 4998 reset-mon-cfg { 4999 temperature = <115000>; 5000 hysteresis = <5000>; 5001 type = "passive"; 5002 }; 5003 5004 cdsp_2_config: junction-config { 5005 temperature = <95000>; 5006 hysteresis = <5000>; 5007 type = "passive"; 5008 }; 5009 }; 5010 }; 5011 5012 video-thermal { 5013 polling-delay-passive = <0>; 5014 polling-delay = <0>; 5015 thermal-sensors = <&tsens1 8>; 5016 5017 trips { 5018 thermal-engine-config { 5019 temperature = <125000>; 5020 hysteresis = <1000>; 5021 type = "passive"; 5022 }; 5023 5024 reset-mon-cfg { 5025 temperature = <115000>; 5026 hysteresis = <5000>; 5027 type = "passive"; 5028 }; 5029 }; 5030 }; 5031 5032 mem-thermal { 5033 polling-delay-passive = <10>; 5034 polling-delay = <0>; 5035 thermal-sensors = <&tsens1 9>; 5036 5037 trips { 5038 thermal-engine-config { 5039 temperature = <125000>; 5040 hysteresis = <1000>; 5041 type = "passive"; 5042 }; 5043 5044 ddr_config0: ddr0-config { 5045 temperature = <90000>; 5046 hysteresis = <5000>; 5047 type = "passive"; 5048 }; 5049 5050 reset-mon-cfg { 5051 temperature = <115000>; 5052 hysteresis = <5000>; 5053 type = "passive"; 5054 }; 5055 }; 5056 }; 5057 5058 modem0-thermal { 5059 polling-delay-passive = <0>; 5060 polling-delay = <0>; 5061 thermal-sensors = <&tsens1 10>; 5062 5063 trips { 5064 thermal-engine-config { 5065 temperature = <125000>; 5066 hysteresis = <1000>; 5067 type = "passive"; 5068 }; 5069 5070 mdmss0_config0: mdmss0-config0 { 5071 temperature = <102000>; 5072 hysteresis = <3000>; 5073 type = "passive"; 5074 }; 5075 5076 mdmss0_config1: mdmss0-config1 { 5077 temperature = <105000>; 5078 hysteresis = <3000>; 5079 type = "passive"; 5080 }; 5081 5082 reset-mon-cfg { 5083 temperature = <115000>; 5084 hysteresis = <5000>; 5085 type = "passive"; 5086 }; 5087 }; 5088 }; 5089 5090 modem1-thermal { 5091 polling-delay-passive = <0>; 5092 polling-delay = <0>; 5093 thermal-sensors = <&tsens1 11>; 5094 5095 trips { 5096 thermal-engine-config { 5097 temperature = <125000>; 5098 hysteresis = <1000>; 5099 type = "passive"; 5100 }; 5101 5102 mdmss1_config0: mdmss1-config0 { 5103 temperature = <102000>; 5104 hysteresis = <3000>; 5105 type = "passive"; 5106 }; 5107 5108 mdmss1_config1: mdmss1-config1 { 5109 temperature = <105000>; 5110 hysteresis = <3000>; 5111 type = "passive"; 5112 }; 5113 5114 reset-mon-cfg { 5115 temperature = <115000>; 5116 hysteresis = <5000>; 5117 type = "passive"; 5118 }; 5119 }; 5120 }; 5121 5122 modem2-thermal { 5123 polling-delay-passive = <0>; 5124 polling-delay = <0>; 5125 thermal-sensors = <&tsens1 12>; 5126 5127 trips { 5128 thermal-engine-config { 5129 temperature = <125000>; 5130 hysteresis = <1000>; 5131 type = "passive"; 5132 }; 5133 5134 mdmss2_config0: mdmss2-config0 { 5135 temperature = <102000>; 5136 hysteresis = <3000>; 5137 type = "passive"; 5138 }; 5139 5140 mdmss2_config1: mdmss2-config1 { 5141 temperature = <105000>; 5142 hysteresis = <3000>; 5143 type = "passive"; 5144 }; 5145 5146 reset-mon-cfg { 5147 temperature = <115000>; 5148 hysteresis = <5000>; 5149 type = "passive"; 5150 }; 5151 }; 5152 }; 5153 5154 modem3-thermal { 5155 polling-delay-passive = <0>; 5156 polling-delay = <0>; 5157 thermal-sensors = <&tsens1 13>; 5158 5159 trips { 5160 thermal-engine-config { 5161 temperature = <125000>; 5162 hysteresis = <1000>; 5163 type = "passive"; 5164 }; 5165 5166 mdmss3_config0: mdmss3-config0 { 5167 temperature = <102000>; 5168 hysteresis = <3000>; 5169 type = "passive"; 5170 }; 5171 5172 mdmss3_config1: mdmss3-config1 { 5173 temperature = <105000>; 5174 hysteresis = <3000>; 5175 type = "passive"; 5176 }; 5177 5178 reset-mon-cfg { 5179 temperature = <115000>; 5180 hysteresis = <5000>; 5181 type = "passive"; 5182 }; 5183 }; 5184 }; 5185 5186 camera0-thermal { 5187 polling-delay-passive = <0>; 5188 polling-delay = <0>; 5189 thermal-sensors = <&tsens1 14>; 5190 5191 trips { 5192 thermal-engine-config { 5193 temperature = <125000>; 5194 hysteresis = <1000>; 5195 type = "passive"; 5196 }; 5197 5198 reset-mon-cfg { 5199 temperature = <115000>; 5200 hysteresis = <5000>; 5201 type = "passive"; 5202 }; 5203 }; 5204 }; 5205 5206 camera1-thermal { 5207 polling-delay-passive = <0>; 5208 polling-delay = <0>; 5209 thermal-sensors = <&tsens1 15>; 5210 5211 trips { 5212 thermal-engine-config { 5213 temperature = <125000>; 5214 hysteresis = <1000>; 5215 type = "passive"; 5216 }; 5217 5218 reset-mon-cfg { 5219 temperature = <115000>; 5220 hysteresis = <5000>; 5221 type = "passive"; 5222 }; 5223 }; 5224 }; 5225 }; 5226 5227 timer { 5228 compatible = "arm,armv8-timer"; 5229 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5230 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5231 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5232 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5233 clock-frequency = <19200000>; 5234 }; 5235}; 5236