1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8450-videocc.h> 8#include <dt-bindings/clock/qcom,sm8550-gcc.h> 9#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 10#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 11#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/soc/qcom,gpr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 22#include <dt-bindings/phy/phy-qcom-qmp.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 }; 38 39 sleep_clk: sleep-clk { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 }; 43 44 bi_tcxo_div2: bi-tcxo-div2-clk { 45 #clock-cells = <0>; 46 compatible = "fixed-factor-clock"; 47 clocks = <&rpmhcc RPMH_CXO_CLK>; 48 clock-mult = <1>; 49 clock-div = <2>; 50 }; 51 52 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 53 #clock-cells = <0>; 54 compatible = "fixed-factor-clock"; 55 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 56 clock-mult = <1>; 57 clock-div = <2>; 58 }; 59 60 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 }; 64 }; 65 66 cpus { 67 #address-cells = <2>; 68 #size-cells = <0>; 69 70 CPU0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a510"; 73 reg = <0 0>; 74 clocks = <&cpufreq_hw 0>; 75 enable-method = "psci"; 76 next-level-cache = <&L2_0>; 77 power-domains = <&CPU_PD0>; 78 power-domain-names = "psci"; 79 qcom,freq-domain = <&cpufreq_hw 0>; 80 capacity-dmips-mhz = <1024>; 81 dynamic-power-coefficient = <100>; 82 #cooling-cells = <2>; 83 L2_0: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 next-level-cache = <&L3_0>; 88 L3_0: l3-cache { 89 compatible = "cache"; 90 cache-level = <3>; 91 cache-unified; 92 }; 93 }; 94 }; 95 96 CPU1: cpu@100 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a510"; 99 reg = <0 0x100>; 100 clocks = <&cpufreq_hw 0>; 101 enable-method = "psci"; 102 next-level-cache = <&L2_100>; 103 power-domains = <&CPU_PD1>; 104 power-domain-names = "psci"; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 capacity-dmips-mhz = <1024>; 107 dynamic-power-coefficient = <100>; 108 #cooling-cells = <2>; 109 L2_100: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 next-level-cache = <&L3_0>; 114 }; 115 }; 116 117 CPU2: cpu@200 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a510"; 120 reg = <0 0x200>; 121 clocks = <&cpufreq_hw 0>; 122 enable-method = "psci"; 123 next-level-cache = <&L2_200>; 124 power-domains = <&CPU_PD2>; 125 power-domain-names = "psci"; 126 qcom,freq-domain = <&cpufreq_hw 0>; 127 capacity-dmips-mhz = <1024>; 128 dynamic-power-coefficient = <100>; 129 #cooling-cells = <2>; 130 L2_200: l2-cache { 131 compatible = "cache"; 132 cache-level = <2>; 133 cache-unified; 134 next-level-cache = <&L3_0>; 135 }; 136 }; 137 138 CPU3: cpu@300 { 139 device_type = "cpu"; 140 compatible = "arm,cortex-a715"; 141 reg = <0 0x300>; 142 clocks = <&cpufreq_hw 1>; 143 enable-method = "psci"; 144 next-level-cache = <&L2_300>; 145 power-domains = <&CPU_PD3>; 146 power-domain-names = "psci"; 147 qcom,freq-domain = <&cpufreq_hw 1>; 148 capacity-dmips-mhz = <1792>; 149 dynamic-power-coefficient = <270>; 150 #cooling-cells = <2>; 151 L2_300: l2-cache { 152 compatible = "cache"; 153 cache-level = <2>; 154 cache-unified; 155 next-level-cache = <&L3_0>; 156 }; 157 }; 158 159 CPU4: cpu@400 { 160 device_type = "cpu"; 161 compatible = "arm,cortex-a715"; 162 reg = <0 0x400>; 163 clocks = <&cpufreq_hw 1>; 164 enable-method = "psci"; 165 next-level-cache = <&L2_400>; 166 power-domains = <&CPU_PD4>; 167 power-domain-names = "psci"; 168 qcom,freq-domain = <&cpufreq_hw 1>; 169 capacity-dmips-mhz = <1792>; 170 dynamic-power-coefficient = <270>; 171 #cooling-cells = <2>; 172 L2_400: l2-cache { 173 compatible = "cache"; 174 cache-level = <2>; 175 cache-unified; 176 next-level-cache = <&L3_0>; 177 }; 178 }; 179 180 CPU5: cpu@500 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a710"; 183 reg = <0 0x500>; 184 clocks = <&cpufreq_hw 1>; 185 enable-method = "psci"; 186 next-level-cache = <&L2_500>; 187 power-domains = <&CPU_PD5>; 188 power-domain-names = "psci"; 189 qcom,freq-domain = <&cpufreq_hw 1>; 190 capacity-dmips-mhz = <1792>; 191 dynamic-power-coefficient = <270>; 192 #cooling-cells = <2>; 193 L2_500: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 next-level-cache = <&L3_0>; 198 }; 199 }; 200 201 CPU6: cpu@600 { 202 device_type = "cpu"; 203 compatible = "arm,cortex-a710"; 204 reg = <0 0x600>; 205 clocks = <&cpufreq_hw 1>; 206 enable-method = "psci"; 207 next-level-cache = <&L2_600>; 208 power-domains = <&CPU_PD6>; 209 power-domain-names = "psci"; 210 qcom,freq-domain = <&cpufreq_hw 1>; 211 capacity-dmips-mhz = <1792>; 212 dynamic-power-coefficient = <270>; 213 #cooling-cells = <2>; 214 L2_600: l2-cache { 215 compatible = "cache"; 216 cache-level = <2>; 217 cache-unified; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU7: cpu@700 { 223 device_type = "cpu"; 224 compatible = "arm,cortex-x3"; 225 reg = <0 0x700>; 226 clocks = <&cpufreq_hw 2>; 227 enable-method = "psci"; 228 next-level-cache = <&L2_700>; 229 power-domains = <&CPU_PD7>; 230 power-domain-names = "psci"; 231 qcom,freq-domain = <&cpufreq_hw 2>; 232 capacity-dmips-mhz = <1894>; 233 dynamic-power-coefficient = <588>; 234 #cooling-cells = <2>; 235 L2_700: l2-cache { 236 compatible = "cache"; 237 cache-level = <2>; 238 cache-unified; 239 next-level-cache = <&L3_0>; 240 }; 241 }; 242 243 cpu-map { 244 cluster0 { 245 core0 { 246 cpu = <&CPU0>; 247 }; 248 249 core1 { 250 cpu = <&CPU1>; 251 }; 252 253 core2 { 254 cpu = <&CPU2>; 255 }; 256 257 core3 { 258 cpu = <&CPU3>; 259 }; 260 261 core4 { 262 cpu = <&CPU4>; 263 }; 264 265 core5 { 266 cpu = <&CPU5>; 267 }; 268 269 core6 { 270 cpu = <&CPU6>; 271 }; 272 273 core7 { 274 cpu = <&CPU7>; 275 }; 276 }; 277 }; 278 279 idle-states { 280 entry-method = "psci"; 281 282 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 283 compatible = "arm,idle-state"; 284 idle-state-name = "silver-rail-power-collapse"; 285 arm,psci-suspend-param = <0x40000004>; 286 entry-latency-us = <550>; 287 exit-latency-us = <750>; 288 min-residency-us = <6700>; 289 local-timer-stop; 290 }; 291 292 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 293 compatible = "arm,idle-state"; 294 idle-state-name = "gold-rail-power-collapse"; 295 arm,psci-suspend-param = <0x40000004>; 296 entry-latency-us = <600>; 297 exit-latency-us = <1300>; 298 min-residency-us = <8136>; 299 local-timer-stop; 300 }; 301 302 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 { 303 compatible = "arm,idle-state"; 304 idle-state-name = "goldplus-rail-power-collapse"; 305 arm,psci-suspend-param = <0x40000004>; 306 entry-latency-us = <500>; 307 exit-latency-us = <1350>; 308 min-residency-us = <7480>; 309 local-timer-stop; 310 }; 311 }; 312 313 domain-idle-states { 314 CLUSTER_SLEEP_0: cluster-sleep-0 { 315 compatible = "domain-idle-state"; 316 arm,psci-suspend-param = <0x41000044>; 317 entry-latency-us = <750>; 318 exit-latency-us = <2350>; 319 min-residency-us = <9144>; 320 }; 321 322 CLUSTER_SLEEP_1: cluster-sleep-1 { 323 compatible = "domain-idle-state"; 324 arm,psci-suspend-param = <0x4100c344>; 325 entry-latency-us = <2800>; 326 exit-latency-us = <4400>; 327 min-residency-us = <10150>; 328 }; 329 }; 330 }; 331 332 firmware { 333 scm: scm { 334 compatible = "qcom,scm-sm8550", "qcom,scm"; 335 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 336 }; 337 }; 338 339 clk_virt: interconnect-0 { 340 compatible = "qcom,sm8550-clk-virt"; 341 #interconnect-cells = <2>; 342 qcom,bcm-voters = <&apps_bcm_voter>; 343 }; 344 345 mc_virt: interconnect-1 { 346 compatible = "qcom,sm8550-mc-virt"; 347 #interconnect-cells = <2>; 348 qcom,bcm-voters = <&apps_bcm_voter>; 349 }; 350 351 memory@a0000000 { 352 device_type = "memory"; 353 /* We expect the bootloader to fill in the size */ 354 reg = <0 0xa0000000 0 0>; 355 }; 356 357 pmu { 358 compatible = "arm,armv8-pmuv3"; 359 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 360 }; 361 362 psci { 363 compatible = "arm,psci-1.0"; 364 method = "smc"; 365 366 CPU_PD0: power-domain-cpu0 { 367 #power-domain-cells = <0>; 368 power-domains = <&CLUSTER_PD>; 369 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 370 }; 371 372 CPU_PD1: power-domain-cpu1 { 373 #power-domain-cells = <0>; 374 power-domains = <&CLUSTER_PD>; 375 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 376 }; 377 378 CPU_PD2: power-domain-cpu2 { 379 #power-domain-cells = <0>; 380 power-domains = <&CLUSTER_PD>; 381 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 382 }; 383 384 CPU_PD3: power-domain-cpu3 { 385 #power-domain-cells = <0>; 386 power-domains = <&CLUSTER_PD>; 387 domain-idle-states = <&BIG_CPU_SLEEP_0>; 388 }; 389 390 CPU_PD4: power-domain-cpu4 { 391 #power-domain-cells = <0>; 392 power-domains = <&CLUSTER_PD>; 393 domain-idle-states = <&BIG_CPU_SLEEP_0>; 394 }; 395 396 CPU_PD5: power-domain-cpu5 { 397 #power-domain-cells = <0>; 398 power-domains = <&CLUSTER_PD>; 399 domain-idle-states = <&BIG_CPU_SLEEP_0>; 400 }; 401 402 CPU_PD6: power-domain-cpu6 { 403 #power-domain-cells = <0>; 404 power-domains = <&CLUSTER_PD>; 405 domain-idle-states = <&BIG_CPU_SLEEP_0>; 406 }; 407 408 CPU_PD7: power-domain-cpu7 { 409 #power-domain-cells = <0>; 410 power-domains = <&CLUSTER_PD>; 411 domain-idle-states = <&PRIME_CPU_SLEEP_0>; 412 }; 413 414 CLUSTER_PD: power-domain-cluster { 415 #power-domain-cells = <0>; 416 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 417 }; 418 }; 419 420 reserved_memory: reserved-memory { 421 #address-cells = <2>; 422 #size-cells = <2>; 423 ranges; 424 425 hyp_mem: hyp-region@80000000 { 426 reg = <0 0x80000000 0 0xa00000>; 427 no-map; 428 }; 429 430 cpusys_vm_mem: cpusys-vm-region@80a00000 { 431 reg = <0 0x80a00000 0 0x400000>; 432 no-map; 433 }; 434 435 hyp_tags_mem: hyp-tags-region@80e00000 { 436 reg = <0 0x80e00000 0 0x3d0000>; 437 no-map; 438 }; 439 440 xbl_sc_mem: xbl-sc-region@d8100000 { 441 reg = <0 0xd8100000 0 0x40000>; 442 no-map; 443 }; 444 445 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 446 reg = <0 0x811d0000 0 0x30000>; 447 no-map; 448 }; 449 450 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 451 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 452 reg = <0 0x81a00000 0 0x260000>; 453 no-map; 454 }; 455 456 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 457 compatible = "qcom,cmd-db"; 458 reg = <0 0x81c60000 0 0x20000>; 459 no-map; 460 }; 461 462 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 463 aop_config_merged_mem: aop-config-merged-region@81c80000 { 464 reg = <0 0x81c80000 0 0x74000>; 465 no-map; 466 }; 467 468 /* secdata region can be reused by apps */ 469 smem: smem@81d00000 { 470 compatible = "qcom,smem"; 471 reg = <0 0x81d00000 0 0x200000>; 472 hwlocks = <&tcsr_mutex 3>; 473 no-map; 474 }; 475 476 adsp_mhi_mem: adsp-mhi-region@81f00000 { 477 reg = <0 0x81f00000 0 0x20000>; 478 no-map; 479 }; 480 481 global_sync_mem: global-sync-region@82600000 { 482 reg = <0 0x82600000 0 0x100000>; 483 no-map; 484 }; 485 486 tz_stat_mem: tz-stat-region@82700000 { 487 reg = <0 0x82700000 0 0x100000>; 488 no-map; 489 }; 490 491 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 492 reg = <0 0x82800000 0 0x4600000>; 493 no-map; 494 }; 495 496 mpss_mem: mpss-region@8a800000 { 497 reg = <0 0x8a800000 0 0x10800000>; 498 no-map; 499 }; 500 501 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 502 reg = <0 0x9b000000 0 0x80000>; 503 no-map; 504 }; 505 506 ipa_fw_mem: ipa-fw-region@9b080000 { 507 reg = <0 0x9b080000 0 0x10000>; 508 no-map; 509 }; 510 511 ipa_gsi_mem: ipa-gsi-region@9b090000 { 512 reg = <0 0x9b090000 0 0xa000>; 513 no-map; 514 }; 515 516 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 517 reg = <0 0x9b09a000 0 0x2000>; 518 no-map; 519 }; 520 521 spss_region_mem: spss-region@9b100000 { 522 reg = <0 0x9b100000 0 0x180000>; 523 no-map; 524 }; 525 526 /* First part of the "SPU secure shared memory" region */ 527 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 528 reg = <0 0x9b280000 0 0x60000>; 529 no-map; 530 }; 531 532 /* Second part of the "SPU secure shared memory" region */ 533 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 534 reg = <0 0x9b2e0000 0 0x20000>; 535 no-map; 536 }; 537 538 camera_mem: camera-region@9b300000 { 539 reg = <0 0x9b300000 0 0x800000>; 540 no-map; 541 }; 542 543 video_mem: video-region@9bb00000 { 544 reg = <0 0x9bb00000 0 0x700000>; 545 no-map; 546 }; 547 548 cvp_mem: cvp-region@9c200000 { 549 reg = <0 0x9c200000 0 0x700000>; 550 no-map; 551 }; 552 553 cdsp_mem: cdsp-region@9c900000 { 554 reg = <0 0x9c900000 0 0x2000000>; 555 no-map; 556 }; 557 558 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 559 reg = <0 0x9e900000 0 0x80000>; 560 no-map; 561 }; 562 563 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 564 reg = <0 0x9e980000 0 0x80000>; 565 no-map; 566 }; 567 568 adspslpi_mem: adspslpi-region@9ea00000 { 569 reg = <0 0x9ea00000 0 0x4080000>; 570 no-map; 571 }; 572 573 /* uefi region can be reused by apps */ 574 575 /* Linux kernel image is loaded at 0xa8000000 */ 576 577 rmtfs_mem: rmtfs-region@d4a80000 { 578 compatible = "qcom,rmtfs-mem"; 579 reg = <0x0 0xd4a80000 0x0 0x280000>; 580 no-map; 581 582 qcom,client-id = <1>; 583 qcom,vmid = <15>; 584 }; 585 586 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 587 reg = <0 0xd4d00000 0 0x3300000>; 588 no-map; 589 }; 590 591 tz_reserved_mem: tz-reserved-region@d8000000 { 592 reg = <0 0xd8000000 0 0x100000>; 593 no-map; 594 }; 595 596 cpucp_fw_mem: cpucp-fw-region@d8140000 { 597 reg = <0 0xd8140000 0 0x1c0000>; 598 no-map; 599 }; 600 601 qtee_mem: qtee-region@d8300000 { 602 reg = <0 0xd8300000 0 0x500000>; 603 no-map; 604 }; 605 606 ta_mem: ta-region@d8800000 { 607 reg = <0 0xd8800000 0 0x8a00000>; 608 no-map; 609 }; 610 611 tz_tags_mem: tz-tags-region@e1200000 { 612 reg = <0 0xe1200000 0 0x2740000>; 613 no-map; 614 }; 615 616 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 617 reg = <0 0xe6440000 0 0x279000>; 618 no-map; 619 }; 620 621 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 622 reg = <0 0xf3600000 0 0x4aee000>; 623 no-map; 624 }; 625 626 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 627 reg = <0 0xf80ee000 0 0x1000>; 628 no-map; 629 }; 630 631 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 632 reg = <0 0xf80ef000 0 0x9000>; 633 no-map; 634 }; 635 636 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 637 reg = <0 0xf80f8000 0 0x4000>; 638 no-map; 639 }; 640 641 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 642 reg = <0 0xf80fc000 0 0x4000>; 643 no-map; 644 }; 645 646 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 647 reg = <0 0xf8100000 0 0x100000>; 648 no-map; 649 }; 650 651 oem_vm_mem: oem-vm-region@f8400000 { 652 reg = <0 0xf8400000 0 0x4800000>; 653 no-map; 654 }; 655 656 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 657 reg = <0 0xfcc00000 0 0x4000>; 658 no-map; 659 }; 660 661 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 662 reg = <0 0xfcc04000 0 0x100000>; 663 no-map; 664 }; 665 666 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 667 reg = <0 0xfce00000 0 0x2900000>; 668 no-map; 669 }; 670 671 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 672 reg = <0 0xff700000 0 0x100000>; 673 no-map; 674 }; 675 }; 676 677 smp2p-adsp { 678 compatible = "qcom,smp2p"; 679 qcom,smem = <443>, <429>; 680 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 681 IPCC_MPROC_SIGNAL_SMP2P 682 IRQ_TYPE_EDGE_RISING>; 683 mboxes = <&ipcc IPCC_CLIENT_LPASS 684 IPCC_MPROC_SIGNAL_SMP2P>; 685 686 qcom,local-pid = <0>; 687 qcom,remote-pid = <2>; 688 689 smp2p_adsp_out: master-kernel { 690 qcom,entry-name = "master-kernel"; 691 #qcom,smem-state-cells = <1>; 692 }; 693 694 smp2p_adsp_in: slave-kernel { 695 qcom,entry-name = "slave-kernel"; 696 interrupt-controller; 697 #interrupt-cells = <2>; 698 }; 699 }; 700 701 smp2p-cdsp { 702 compatible = "qcom,smp2p"; 703 qcom,smem = <94>, <432>; 704 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 705 IPCC_MPROC_SIGNAL_SMP2P 706 IRQ_TYPE_EDGE_RISING>; 707 mboxes = <&ipcc IPCC_CLIENT_CDSP 708 IPCC_MPROC_SIGNAL_SMP2P>; 709 710 qcom,local-pid = <0>; 711 qcom,remote-pid = <5>; 712 713 smp2p_cdsp_out: master-kernel { 714 qcom,entry-name = "master-kernel"; 715 #qcom,smem-state-cells = <1>; 716 }; 717 718 smp2p_cdsp_in: slave-kernel { 719 qcom,entry-name = "slave-kernel"; 720 interrupt-controller; 721 #interrupt-cells = <2>; 722 }; 723 }; 724 725 smp2p-modem { 726 compatible = "qcom,smp2p"; 727 qcom,smem = <435>, <428>; 728 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 729 IPCC_MPROC_SIGNAL_SMP2P 730 IRQ_TYPE_EDGE_RISING>; 731 mboxes = <&ipcc IPCC_CLIENT_MPSS 732 IPCC_MPROC_SIGNAL_SMP2P>; 733 734 qcom,local-pid = <0>; 735 qcom,remote-pid = <1>; 736 737 smp2p_modem_out: master-kernel { 738 qcom,entry-name = "master-kernel"; 739 #qcom,smem-state-cells = <1>; 740 }; 741 742 smp2p_modem_in: slave-kernel { 743 qcom,entry-name = "slave-kernel"; 744 interrupt-controller; 745 #interrupt-cells = <2>; 746 }; 747 748 ipa_smp2p_out: ipa-ap-to-modem { 749 qcom,entry-name = "ipa"; 750 #qcom,smem-state-cells = <1>; 751 }; 752 753 ipa_smp2p_in: ipa-modem-to-ap { 754 qcom,entry-name = "ipa"; 755 interrupt-controller; 756 #interrupt-cells = <2>; 757 }; 758 }; 759 760 soc: soc@0 { 761 compatible = "simple-bus"; 762 ranges = <0 0 0 0 0x10 0>; 763 dma-ranges = <0 0 0 0 0x10 0>; 764 765 #address-cells = <2>; 766 #size-cells = <2>; 767 768 gcc: clock-controller@100000 { 769 compatible = "qcom,sm8550-gcc"; 770 reg = <0 0x00100000 0 0x1f4200>; 771 #clock-cells = <1>; 772 #reset-cells = <1>; 773 #power-domain-cells = <1>; 774 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 775 <&pcie0_phy>, 776 <&pcie1_phy>, 777 <&pcie_1_phy_aux_clk>, 778 <&ufs_mem_phy 0>, 779 <&ufs_mem_phy 1>, 780 <&ufs_mem_phy 2>, 781 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 782 }; 783 784 ipcc: mailbox@408000 { 785 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 786 reg = <0 0x00408000 0 0x1000>; 787 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 788 interrupt-controller; 789 #interrupt-cells = <3>; 790 #mbox-cells = <2>; 791 }; 792 793 gpi_dma2: dma-controller@800000 { 794 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 795 #dma-cells = <3>; 796 reg = <0 0x00800000 0 0x60000>; 797 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 809 dma-channels = <12>; 810 dma-channel-mask = <0x3e>; 811 iommus = <&apps_smmu 0x436 0>; 812 status = "disabled"; 813 }; 814 815 qupv3_id_1: geniqup@8c0000 { 816 compatible = "qcom,geni-se-qup"; 817 reg = <0 0x008c0000 0 0x2000>; 818 ranges; 819 clock-names = "m-ahb", "s-ahb"; 820 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 821 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 822 iommus = <&apps_smmu 0x423 0>; 823 #address-cells = <2>; 824 #size-cells = <2>; 825 status = "disabled"; 826 827 i2c8: i2c@880000 { 828 compatible = "qcom,geni-i2c"; 829 reg = <0 0x00880000 0 0x4000>; 830 clock-names = "se"; 831 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 832 pinctrl-names = "default"; 833 pinctrl-0 = <&qup_i2c8_data_clk>; 834 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 838 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 839 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 840 interconnect-names = "qup-core", "qup-config", "qup-memory"; 841 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 842 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 843 dma-names = "tx", "rx"; 844 status = "disabled"; 845 }; 846 847 spi8: spi@880000 { 848 compatible = "qcom,geni-spi"; 849 reg = <0 0x00880000 0 0x4000>; 850 clock-names = "se"; 851 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 852 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 855 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 856 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 857 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 858 interconnect-names = "qup-core", "qup-config", "qup-memory"; 859 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 860 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 861 dma-names = "tx", "rx"; 862 #address-cells = <1>; 863 #size-cells = <0>; 864 status = "disabled"; 865 }; 866 867 i2c9: i2c@884000 { 868 compatible = "qcom,geni-i2c"; 869 reg = <0 0x00884000 0 0x4000>; 870 clock-names = "se"; 871 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 872 pinctrl-names = "default"; 873 pinctrl-0 = <&qup_i2c9_data_clk>; 874 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 878 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 879 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 880 interconnect-names = "qup-core", "qup-config", "qup-memory"; 881 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 882 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 883 dma-names = "tx", "rx"; 884 status = "disabled"; 885 }; 886 887 spi9: spi@884000 { 888 compatible = "qcom,geni-spi"; 889 reg = <0 0x00884000 0 0x4000>; 890 clock-names = "se"; 891 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 892 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 893 pinctrl-names = "default"; 894 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 895 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 896 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 897 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 898 interconnect-names = "qup-core", "qup-config", "qup-memory"; 899 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 900 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 901 dma-names = "tx", "rx"; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 status = "disabled"; 905 }; 906 907 i2c10: i2c@888000 { 908 compatible = "qcom,geni-i2c"; 909 reg = <0 0x00888000 0 0x4000>; 910 clock-names = "se"; 911 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_i2c10_data_clk>; 914 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 918 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 919 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 920 interconnect-names = "qup-core", "qup-config", "qup-memory"; 921 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 922 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 923 dma-names = "tx", "rx"; 924 status = "disabled"; 925 }; 926 927 spi10: spi@888000 { 928 compatible = "qcom,geni-spi"; 929 reg = <0 0x00888000 0 0x4000>; 930 clock-names = "se"; 931 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 932 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 933 pinctrl-names = "default"; 934 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 936 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 937 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 938 interconnect-names = "qup-core", "qup-config", "qup-memory"; 939 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 940 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 941 dma-names = "tx", "rx"; 942 #address-cells = <1>; 943 #size-cells = <0>; 944 status = "disabled"; 945 }; 946 947 i2c11: i2c@88c000 { 948 compatible = "qcom,geni-i2c"; 949 reg = <0 0x0088c000 0 0x4000>; 950 clock-names = "se"; 951 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&qup_i2c11_data_clk>; 954 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 958 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 959 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 960 interconnect-names = "qup-core", "qup-config", "qup-memory"; 961 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 962 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 963 dma-names = "tx", "rx"; 964 status = "disabled"; 965 }; 966 967 spi11: spi@88c000 { 968 compatible = "qcom,geni-spi"; 969 reg = <0 0x0088c000 0 0x4000>; 970 clock-names = "se"; 971 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 972 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 973 pinctrl-names = "default"; 974 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 975 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 976 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 977 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 978 interconnect-names = "qup-core", "qup-config", "qup-memory"; 979 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 980 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 981 dma-names = "tx", "rx"; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 i2c12: i2c@890000 { 988 compatible = "qcom,geni-i2c"; 989 reg = <0 0x00890000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&qup_i2c12_data_clk>; 994 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 998 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 999 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1000 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1001 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1002 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1003 dma-names = "tx", "rx"; 1004 status = "disabled"; 1005 }; 1006 1007 spi12: spi@890000 { 1008 compatible = "qcom,geni-spi"; 1009 reg = <0 0x00890000 0 0x4000>; 1010 clock-names = "se"; 1011 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1012 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1013 pinctrl-names = "default"; 1014 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1015 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1016 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1017 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1018 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1019 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1020 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1021 dma-names = "tx", "rx"; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 status = "disabled"; 1025 }; 1026 1027 i2c13: i2c@894000 { 1028 compatible = "qcom,geni-i2c"; 1029 reg = <0 0x00894000 0 0x4000>; 1030 clock-names = "se"; 1031 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1032 pinctrl-names = "default"; 1033 pinctrl-0 = <&qup_i2c13_data_clk>; 1034 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1038 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1039 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1040 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1041 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1042 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1043 dma-names = "tx", "rx"; 1044 status = "disabled"; 1045 }; 1046 1047 spi13: spi@894000 { 1048 compatible = "qcom,geni-spi"; 1049 reg = <0 0x00894000 0 0x4000>; 1050 clock-names = "se"; 1051 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1052 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1053 pinctrl-names = "default"; 1054 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1055 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1056 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1057 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1058 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1059 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1060 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1061 dma-names = "tx", "rx"; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 uart14: serial@898000 { 1068 compatible = "qcom,geni-uart"; 1069 reg = <0 0x898000 0 0x4000>; 1070 clock-names = "se"; 1071 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1072 pinctrl-names = "default"; 1073 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1074 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1075 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1076 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1077 interconnect-names = "qup-core", "qup-config"; 1078 status = "disabled"; 1079 }; 1080 1081 i2c15: i2c@89c000 { 1082 compatible = "qcom,geni-i2c"; 1083 reg = <0 0x0089c000 0 0x4000>; 1084 clock-names = "se"; 1085 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1086 pinctrl-names = "default"; 1087 pinctrl-0 = <&qup_i2c15_data_clk>; 1088 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1092 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1093 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1094 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1095 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1096 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1097 dma-names = "tx", "rx"; 1098 status = "disabled"; 1099 }; 1100 1101 spi15: spi@89c000 { 1102 compatible = "qcom,geni-spi"; 1103 reg = <0 0x0089c000 0 0x4000>; 1104 clock-names = "se"; 1105 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1106 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1107 pinctrl-names = "default"; 1108 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1109 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1110 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1111 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1112 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1113 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1114 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1115 dma-names = "tx", "rx"; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 status = "disabled"; 1119 }; 1120 }; 1121 1122 i2c_master_hub_0: geniqup@9c0000 { 1123 compatible = "qcom,geni-se-i2c-master-hub"; 1124 reg = <0x0 0x009c0000 0x0 0x2000>; 1125 clock-names = "s-ahb"; 1126 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1127 #address-cells = <2>; 1128 #size-cells = <2>; 1129 ranges; 1130 status = "disabled"; 1131 1132 i2c_hub_0: i2c@980000 { 1133 compatible = "qcom,geni-i2c-master-hub"; 1134 reg = <0x0 0x00980000 0x0 0x4000>; 1135 clock-names = "se", "core"; 1136 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1137 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&hub_i2c0_data_clk>; 1140 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1144 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1145 interconnect-names = "qup-core", "qup-config"; 1146 status = "disabled"; 1147 }; 1148 1149 i2c_hub_1: i2c@984000 { 1150 compatible = "qcom,geni-i2c-master-hub"; 1151 reg = <0x0 0x00984000 0x0 0x4000>; 1152 clock-names = "se", "core"; 1153 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1154 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1155 pinctrl-names = "default"; 1156 pinctrl-0 = <&hub_i2c1_data_clk>; 1157 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1161 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1162 interconnect-names = "qup-core", "qup-config"; 1163 status = "disabled"; 1164 }; 1165 1166 i2c_hub_2: i2c@988000 { 1167 compatible = "qcom,geni-i2c-master-hub"; 1168 reg = <0x0 0x00988000 0x0 0x4000>; 1169 clock-names = "se", "core"; 1170 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1171 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1172 pinctrl-names = "default"; 1173 pinctrl-0 = <&hub_i2c2_data_clk>; 1174 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1178 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1179 interconnect-names = "qup-core", "qup-config"; 1180 status = "disabled"; 1181 }; 1182 1183 i2c_hub_3: i2c@98c000 { 1184 compatible = "qcom,geni-i2c-master-hub"; 1185 reg = <0x0 0x0098c000 0x0 0x4000>; 1186 clock-names = "se", "core"; 1187 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1188 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1189 pinctrl-names = "default"; 1190 pinctrl-0 = <&hub_i2c3_data_clk>; 1191 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1195 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1196 interconnect-names = "qup-core", "qup-config"; 1197 status = "disabled"; 1198 }; 1199 1200 i2c_hub_4: i2c@990000 { 1201 compatible = "qcom,geni-i2c-master-hub"; 1202 reg = <0x0 0x00990000 0x0 0x4000>; 1203 clock-names = "se", "core"; 1204 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1205 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1206 pinctrl-names = "default"; 1207 pinctrl-0 = <&hub_i2c4_data_clk>; 1208 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1212 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1213 interconnect-names = "qup-core", "qup-config"; 1214 status = "disabled"; 1215 }; 1216 1217 i2c_hub_5: i2c@994000 { 1218 compatible = "qcom,geni-i2c-master-hub"; 1219 reg = <0 0x00994000 0 0x4000>; 1220 clock-names = "se", "core"; 1221 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1222 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&hub_i2c5_data_clk>; 1225 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1229 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1230 interconnect-names = "qup-core", "qup-config"; 1231 status = "disabled"; 1232 }; 1233 1234 i2c_hub_6: i2c@998000 { 1235 compatible = "qcom,geni-i2c-master-hub"; 1236 reg = <0 0x00998000 0 0x4000>; 1237 clock-names = "se", "core"; 1238 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1239 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1240 pinctrl-names = "default"; 1241 pinctrl-0 = <&hub_i2c6_data_clk>; 1242 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1246 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1247 interconnect-names = "qup-core", "qup-config"; 1248 status = "disabled"; 1249 }; 1250 1251 i2c_hub_7: i2c@99c000 { 1252 compatible = "qcom,geni-i2c-master-hub"; 1253 reg = <0 0x0099c000 0 0x4000>; 1254 clock-names = "se", "core"; 1255 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1256 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1257 pinctrl-names = "default"; 1258 pinctrl-0 = <&hub_i2c7_data_clk>; 1259 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1263 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1264 interconnect-names = "qup-core", "qup-config"; 1265 status = "disabled"; 1266 }; 1267 1268 i2c_hub_8: i2c@9a0000 { 1269 compatible = "qcom,geni-i2c-master-hub"; 1270 reg = <0 0x009a0000 0 0x4000>; 1271 clock-names = "se", "core"; 1272 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1273 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1274 pinctrl-names = "default"; 1275 pinctrl-0 = <&hub_i2c8_data_clk>; 1276 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1280 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1281 interconnect-names = "qup-core", "qup-config"; 1282 status = "disabled"; 1283 }; 1284 1285 i2c_hub_9: i2c@9a4000 { 1286 compatible = "qcom,geni-i2c-master-hub"; 1287 reg = <0 0x009a4000 0 0x4000>; 1288 clock-names = "se", "core"; 1289 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1290 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1291 pinctrl-names = "default"; 1292 pinctrl-0 = <&hub_i2c9_data_clk>; 1293 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1297 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1298 interconnect-names = "qup-core", "qup-config"; 1299 status = "disabled"; 1300 }; 1301 }; 1302 1303 gpi_dma1: dma-controller@a00000 { 1304 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1305 #dma-cells = <3>; 1306 reg = <0 0x00a00000 0 0x60000>; 1307 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1311 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1313 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1319 dma-channels = <12>; 1320 dma-channel-mask = <0x1e>; 1321 iommus = <&apps_smmu 0xb6 0>; 1322 status = "disabled"; 1323 }; 1324 1325 qupv3_id_0: geniqup@ac0000 { 1326 compatible = "qcom,geni-se-qup"; 1327 reg = <0 0x00ac0000 0 0x2000>; 1328 ranges; 1329 clock-names = "m-ahb", "s-ahb"; 1330 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1331 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1332 iommus = <&apps_smmu 0xa3 0>; 1333 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1334 interconnect-names = "qup-core"; 1335 #address-cells = <2>; 1336 #size-cells = <2>; 1337 status = "disabled"; 1338 1339 i2c0: i2c@a80000 { 1340 compatible = "qcom,geni-i2c"; 1341 reg = <0 0x00a80000 0 0x4000>; 1342 clock-names = "se"; 1343 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1344 pinctrl-names = "default"; 1345 pinctrl-0 = <&qup_i2c0_data_clk>; 1346 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1347 #address-cells = <1>; 1348 #size-cells = <0>; 1349 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1350 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1351 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1352 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1353 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1354 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1355 dma-names = "tx", "rx"; 1356 status = "disabled"; 1357 }; 1358 1359 spi0: spi@a80000 { 1360 compatible = "qcom,geni-spi"; 1361 reg = <0 0x00a80000 0 0x4000>; 1362 clock-names = "se"; 1363 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1364 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1365 pinctrl-names = "default"; 1366 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1367 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1368 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1369 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1370 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1371 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1372 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1373 dma-names = "tx", "rx"; 1374 #address-cells = <1>; 1375 #size-cells = <0>; 1376 status = "disabled"; 1377 }; 1378 1379 i2c1: i2c@a84000 { 1380 compatible = "qcom,geni-i2c"; 1381 reg = <0 0x00a84000 0 0x4000>; 1382 clock-names = "se"; 1383 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1384 pinctrl-names = "default"; 1385 pinctrl-0 = <&qup_i2c1_data_clk>; 1386 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1390 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1391 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1392 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1393 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1394 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1395 dma-names = "tx", "rx"; 1396 status = "disabled"; 1397 }; 1398 1399 spi1: spi@a84000 { 1400 compatible = "qcom,geni-spi"; 1401 reg = <0 0x00a84000 0 0x4000>; 1402 clock-names = "se"; 1403 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1404 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1405 pinctrl-names = "default"; 1406 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1407 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1408 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1409 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1410 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1411 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1412 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1413 dma-names = "tx", "rx"; 1414 #address-cells = <1>; 1415 #size-cells = <0>; 1416 status = "disabled"; 1417 }; 1418 1419 i2c2: i2c@a88000 { 1420 compatible = "qcom,geni-i2c"; 1421 reg = <0 0x00a88000 0 0x4000>; 1422 clock-names = "se"; 1423 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1424 pinctrl-names = "default"; 1425 pinctrl-0 = <&qup_i2c2_data_clk>; 1426 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1430 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1431 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1432 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1433 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1434 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1435 dma-names = "tx", "rx"; 1436 status = "disabled"; 1437 }; 1438 1439 spi2: spi@a88000 { 1440 compatible = "qcom,geni-spi"; 1441 reg = <0 0x00a88000 0 0x4000>; 1442 clock-names = "se"; 1443 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1444 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1445 pinctrl-names = "default"; 1446 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1447 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1448 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1449 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1450 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1451 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1452 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1453 dma-names = "tx", "rx"; 1454 #address-cells = <1>; 1455 #size-cells = <0>; 1456 status = "disabled"; 1457 }; 1458 1459 i2c3: i2c@a8c000 { 1460 compatible = "qcom,geni-i2c"; 1461 reg = <0 0x00a8c000 0 0x4000>; 1462 clock-names = "se"; 1463 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1464 pinctrl-names = "default"; 1465 pinctrl-0 = <&qup_i2c3_data_clk>; 1466 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1470 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1471 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1472 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1473 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1474 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1475 dma-names = "tx", "rx"; 1476 status = "disabled"; 1477 }; 1478 1479 spi3: spi@a8c000 { 1480 compatible = "qcom,geni-spi"; 1481 reg = <0 0x00a8c000 0 0x4000>; 1482 clock-names = "se"; 1483 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1484 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1485 pinctrl-names = "default"; 1486 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1487 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1488 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1489 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1490 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1491 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1492 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1493 dma-names = "tx", "rx"; 1494 #address-cells = <1>; 1495 #size-cells = <0>; 1496 status = "disabled"; 1497 }; 1498 1499 i2c4: i2c@a90000 { 1500 compatible = "qcom,geni-i2c"; 1501 reg = <0 0x00a90000 0 0x4000>; 1502 clock-names = "se"; 1503 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1504 pinctrl-names = "default"; 1505 pinctrl-0 = <&qup_i2c4_data_clk>; 1506 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1510 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1511 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1512 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1513 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1514 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1515 dma-names = "tx", "rx"; 1516 status = "disabled"; 1517 }; 1518 1519 spi4: spi@a90000 { 1520 compatible = "qcom,geni-spi"; 1521 reg = <0 0x00a90000 0 0x4000>; 1522 clock-names = "se"; 1523 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1524 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1525 pinctrl-names = "default"; 1526 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1527 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1528 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1529 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1530 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1531 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1532 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1533 dma-names = "tx", "rx"; 1534 #address-cells = <1>; 1535 #size-cells = <0>; 1536 status = "disabled"; 1537 }; 1538 1539 i2c5: i2c@a94000 { 1540 compatible = "qcom,geni-i2c"; 1541 reg = <0 0x00a94000 0 0x4000>; 1542 clock-names = "se"; 1543 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1544 pinctrl-names = "default"; 1545 pinctrl-0 = <&qup_i2c5_data_clk>; 1546 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1547 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1548 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1549 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1550 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1551 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1552 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1553 dma-names = "tx", "rx"; 1554 #address-cells = <1>; 1555 #size-cells = <0>; 1556 status = "disabled"; 1557 }; 1558 1559 spi5: spi@a94000 { 1560 compatible = "qcom,geni-spi"; 1561 reg = <0 0x00a94000 0 0x4000>; 1562 clock-names = "se"; 1563 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1564 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1565 pinctrl-names = "default"; 1566 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1567 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1568 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1569 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1570 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1571 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1572 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1573 dma-names = "tx", "rx"; 1574 #address-cells = <1>; 1575 #size-cells = <0>; 1576 status = "disabled"; 1577 }; 1578 1579 i2c6: i2c@a98000 { 1580 compatible = "qcom,geni-i2c"; 1581 reg = <0 0x00a98000 0 0x4000>; 1582 clock-names = "se"; 1583 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1584 pinctrl-names = "default"; 1585 pinctrl-0 = <&qup_i2c6_data_clk>; 1586 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1587 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1588 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1589 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1590 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1591 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1592 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1593 dma-names = "tx", "rx"; 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 status = "disabled"; 1597 }; 1598 1599 spi6: spi@a98000 { 1600 compatible = "qcom,geni-spi"; 1601 reg = <0 0x00a98000 0 0x4000>; 1602 clock-names = "se"; 1603 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1604 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1605 pinctrl-names = "default"; 1606 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1607 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1608 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1609 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1610 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1611 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1612 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1613 dma-names = "tx", "rx"; 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 status = "disabled"; 1617 }; 1618 1619 uart7: serial@a9c000 { 1620 compatible = "qcom,geni-debug-uart"; 1621 reg = <0 0x00a9c000 0 0x4000>; 1622 clock-names = "se"; 1623 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1624 pinctrl-names = "default"; 1625 pinctrl-0 = <&qup_uart7_default>; 1626 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1627 interconnect-names = "qup-core", "qup-config"; 1628 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1629 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1630 status = "disabled"; 1631 }; 1632 }; 1633 1634 cnoc_main: interconnect@1500000 { 1635 compatible = "qcom,sm8550-cnoc-main"; 1636 reg = <0 0x01500000 0 0x13080>; 1637 #interconnect-cells = <2>; 1638 qcom,bcm-voters = <&apps_bcm_voter>; 1639 }; 1640 1641 config_noc: interconnect@1600000 { 1642 compatible = "qcom,sm8550-config-noc"; 1643 reg = <0 0x01600000 0 0x6200>; 1644 #interconnect-cells = <2>; 1645 qcom,bcm-voters = <&apps_bcm_voter>; 1646 }; 1647 1648 system_noc: interconnect@1680000 { 1649 compatible = "qcom,sm8550-system-noc"; 1650 reg = <0 0x01680000 0 0x1d080>; 1651 #interconnect-cells = <2>; 1652 qcom,bcm-voters = <&apps_bcm_voter>; 1653 }; 1654 1655 pcie_noc: interconnect@16c0000 { 1656 compatible = "qcom,sm8550-pcie-anoc"; 1657 reg = <0 0x016c0000 0 0x12200>; 1658 #interconnect-cells = <2>; 1659 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1660 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1661 qcom,bcm-voters = <&apps_bcm_voter>; 1662 }; 1663 1664 aggre1_noc: interconnect@16e0000 { 1665 compatible = "qcom,sm8550-aggre1-noc"; 1666 reg = <0 0x016e0000 0 0x14400>; 1667 #interconnect-cells = <2>; 1668 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1669 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1670 qcom,bcm-voters = <&apps_bcm_voter>; 1671 }; 1672 1673 aggre2_noc: interconnect@1700000 { 1674 compatible = "qcom,sm8550-aggre2-noc"; 1675 reg = <0 0x01700000 0 0x1e400>; 1676 #interconnect-cells = <2>; 1677 clocks = <&rpmhcc RPMH_IPA_CLK>; 1678 qcom,bcm-voters = <&apps_bcm_voter>; 1679 }; 1680 1681 mmss_noc: interconnect@1780000 { 1682 compatible = "qcom,sm8550-mmss-noc"; 1683 reg = <0 0x01780000 0 0x5b800>; 1684 #interconnect-cells = <2>; 1685 qcom,bcm-voters = <&apps_bcm_voter>; 1686 }; 1687 1688 pcie0: pci@1c00000 { 1689 device_type = "pci"; 1690 compatible = "qcom,pcie-sm8550"; 1691 reg = <0 0x01c00000 0 0x3000>, 1692 <0 0x60000000 0 0xf1d>, 1693 <0 0x60000f20 0 0xa8>, 1694 <0 0x60001000 0 0x1000>, 1695 <0 0x60100000 0 0x100000>; 1696 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1697 #address-cells = <3>; 1698 #size-cells = <2>; 1699 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1700 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1701 bus-range = <0x00 0xff>; 1702 1703 dma-coherent; 1704 1705 linux,pci-domain = <0>; 1706 num-lanes = <2>; 1707 1708 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1709 interrupt-names = "msi"; 1710 1711 #interrupt-cells = <1>; 1712 interrupt-map-mask = <0 0 0 0x7>; 1713 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1714 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1715 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1716 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1717 1718 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1719 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1720 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1721 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1722 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1723 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1724 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1725 clock-names = "aux", 1726 "cfg", 1727 "bus_master", 1728 "bus_slave", 1729 "slave_q2a", 1730 "ddrss_sf_tbu", 1731 "noc_aggr"; 1732 1733 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 1734 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; 1735 interconnect-names = "pcie-mem", "cpu-pcie"; 1736 1737 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 1738 <0x100 &apps_smmu 0x1401 0x1>; 1739 1740 resets = <&gcc GCC_PCIE_0_BCR>; 1741 reset-names = "pci"; 1742 1743 power-domains = <&gcc PCIE_0_GDSC>; 1744 1745 phys = <&pcie0_phy>; 1746 phy-names = "pciephy"; 1747 1748 status = "disabled"; 1749 }; 1750 1751 pcie0_phy: phy@1c06000 { 1752 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 1753 reg = <0 0x01c06000 0 0x2000>; 1754 1755 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1756 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1757 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1758 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1759 <&gcc GCC_PCIE_0_PIPE_CLK>; 1760 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1761 "pipe"; 1762 1763 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1764 reset-names = "phy"; 1765 1766 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1767 assigned-clock-rates = <100000000>; 1768 1769 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1770 1771 #clock-cells = <0>; 1772 clock-output-names = "pcie0_pipe_clk"; 1773 1774 #phy-cells = <0>; 1775 1776 status = "disabled"; 1777 }; 1778 1779 pcie1: pci@1c08000 { 1780 device_type = "pci"; 1781 compatible = "qcom,pcie-sm8550"; 1782 reg = <0x0 0x01c08000 0x0 0x3000>, 1783 <0x0 0x40000000 0x0 0xf1d>, 1784 <0x0 0x40000f20 0x0 0xa8>, 1785 <0x0 0x40001000 0x0 0x1000>, 1786 <0x0 0x40100000 0x0 0x100000>; 1787 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1788 #address-cells = <3>; 1789 #size-cells = <2>; 1790 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1791 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1792 bus-range = <0x00 0xff>; 1793 1794 dma-coherent; 1795 1796 linux,pci-domain = <1>; 1797 num-lanes = <2>; 1798 1799 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1800 interrupt-names = "msi"; 1801 1802 #interrupt-cells = <1>; 1803 interrupt-map-mask = <0 0 0 0x7>; 1804 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1805 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1806 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1807 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1808 1809 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1810 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1811 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1812 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1813 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1814 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1815 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1816 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 1817 clock-names = "aux", 1818 "cfg", 1819 "bus_master", 1820 "bus_slave", 1821 "slave_q2a", 1822 "ddrss_sf_tbu", 1823 "noc_aggr", 1824 "cnoc_sf_axi"; 1825 1826 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1827 assigned-clock-rates = <19200000>; 1828 1829 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 1830 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; 1831 interconnect-names = "pcie-mem", "cpu-pcie"; 1832 1833 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 1834 <0x100 &apps_smmu 0x1481 0x1>; 1835 1836 resets = <&gcc GCC_PCIE_1_BCR>, 1837 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1838 reset-names = "pci", "link_down"; 1839 1840 power-domains = <&gcc PCIE_1_GDSC>; 1841 1842 phys = <&pcie1_phy>; 1843 phy-names = "pciephy"; 1844 1845 status = "disabled"; 1846 }; 1847 1848 pcie1_phy: phy@1c0e000 { 1849 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 1850 reg = <0x0 0x01c0e000 0x0 0x2000>; 1851 1852 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1853 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1854 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1855 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1856 <&gcc GCC_PCIE_1_PIPE_CLK>; 1857 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1858 "pipe"; 1859 1860 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 1861 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 1862 reset-names = "phy", "phy_nocsr"; 1863 1864 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1865 assigned-clock-rates = <100000000>; 1866 1867 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1868 1869 #clock-cells = <0>; 1870 clock-output-names = "pcie1_pipe_clk"; 1871 1872 #phy-cells = <0>; 1873 1874 status = "disabled"; 1875 }; 1876 1877 cryptobam: dma-controller@1dc4000 { 1878 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1879 reg = <0x0 0x01dc4000 0x0 0x28000>; 1880 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1881 #dma-cells = <1>; 1882 qcom,ee = <0>; 1883 qcom,num-ees = <4>; 1884 num-channels = <20>; 1885 qcom,controlled-remotely; 1886 iommus = <&apps_smmu 0x480 0x0>, 1887 <&apps_smmu 0x481 0x0>; 1888 }; 1889 1890 crypto: crypto@1dfa000 { 1891 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 1892 reg = <0x0 0x01dfa000 0x0 0x6000>; 1893 dmas = <&cryptobam 4>, <&cryptobam 5>; 1894 dma-names = "rx", "tx"; 1895 iommus = <&apps_smmu 0x480 0x0>, 1896 <&apps_smmu 0x481 0x0>; 1897 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1898 interconnect-names = "memory"; 1899 }; 1900 1901 ufs_mem_phy: phy@1d80000 { 1902 compatible = "qcom,sm8550-qmp-ufs-phy"; 1903 reg = <0x0 0x01d80000 0x0 0x2000>; 1904 clocks = <&tcsr TCSR_UFS_CLKREF_EN>, 1905 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1906 clock-names = "ref", "ref_aux"; 1907 1908 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1909 1910 resets = <&ufs_mem_hc 0>; 1911 reset-names = "ufsphy"; 1912 1913 #clock-cells = <1>; 1914 #phy-cells = <0>; 1915 1916 status = "disabled"; 1917 }; 1918 1919 ufs_mem_hc: ufs@1d84000 { 1920 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 1921 "jedec,ufs-2.0"; 1922 reg = <0x0 0x01d84000 0x0 0x3000>; 1923 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1924 phys = <&ufs_mem_phy>; 1925 phy-names = "ufsphy"; 1926 lanes-per-direction = <2>; 1927 #reset-cells = <1>; 1928 resets = <&gcc GCC_UFS_PHY_BCR>; 1929 reset-names = "rst"; 1930 1931 power-domains = <&gcc UFS_PHY_GDSC>; 1932 required-opps = <&rpmhpd_opp_nom>; 1933 1934 iommus = <&apps_smmu 0x60 0x0>; 1935 dma-coherent; 1936 1937 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 1938 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 1939 1940 interconnect-names = "ufs-ddr", "cpu-ufs"; 1941 clock-names = "core_clk", 1942 "bus_aggr_clk", 1943 "iface_clk", 1944 "core_clk_unipro", 1945 "ref_clk", 1946 "tx_lane0_sync_clk", 1947 "rx_lane0_sync_clk", 1948 "rx_lane1_sync_clk"; 1949 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1950 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1951 <&gcc GCC_UFS_PHY_AHB_CLK>, 1952 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1953 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 1954 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1955 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1956 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1957 freq-table-hz = 1958 <75000000 300000000>, 1959 <0 0>, 1960 <0 0>, 1961 <75000000 300000000>, 1962 <100000000 403000000>, 1963 <0 0>, 1964 <0 0>, 1965 <0 0>; 1966 qcom,ice = <&ice>; 1967 1968 status = "disabled"; 1969 }; 1970 1971 ice: crypto@1d88000 { 1972 compatible = "qcom,sm8550-inline-crypto-engine", 1973 "qcom,inline-crypto-engine"; 1974 reg = <0 0x01d88000 0 0x8000>; 1975 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1976 }; 1977 1978 tcsr_mutex: hwlock@1f40000 { 1979 compatible = "qcom,tcsr-mutex"; 1980 reg = <0 0x01f40000 0 0x20000>; 1981 #hwlock-cells = <1>; 1982 }; 1983 1984 tcsr: clock-controller@1fc0000 { 1985 compatible = "qcom,sm8550-tcsr", "syscon"; 1986 reg = <0 0x01fc0000 0 0x30000>; 1987 clocks = <&rpmhcc RPMH_CXO_CLK>; 1988 #clock-cells = <1>; 1989 #reset-cells = <1>; 1990 }; 1991 1992 gpucc: clock-controller@3d90000 { 1993 compatible = "qcom,sm8550-gpucc"; 1994 reg = <0 0x03d90000 0 0xa000>; 1995 clocks = <&bi_tcxo_div2>, 1996 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1997 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1998 #clock-cells = <1>; 1999 #reset-cells = <1>; 2000 #power-domain-cells = <1>; 2001 }; 2002 2003 remoteproc_mpss: remoteproc@4080000 { 2004 compatible = "qcom,sm8550-mpss-pas"; 2005 reg = <0x0 0x04080000 0x0 0x10000>; 2006 2007 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2008 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2009 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2010 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2011 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2012 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2013 interrupt-names = "wdog", "fatal", "ready", "handover", 2014 "stop-ack", "shutdown-ack"; 2015 2016 clocks = <&rpmhcc RPMH_CXO_CLK>; 2017 clock-names = "xo"; 2018 2019 power-domains = <&rpmhpd RPMHPD_CX>, 2020 <&rpmhpd RPMHPD_MSS>; 2021 power-domain-names = "cx", "mss"; 2022 2023 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2024 2025 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 2026 2027 qcom,qmp = <&aoss_qmp>; 2028 2029 qcom,smem-states = <&smp2p_modem_out 0>; 2030 qcom,smem-state-names = "stop"; 2031 2032 status = "disabled"; 2033 2034 glink-edge { 2035 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2036 IPCC_MPROC_SIGNAL_GLINK_QMP 2037 IRQ_TYPE_EDGE_RISING>; 2038 mboxes = <&ipcc IPCC_CLIENT_MPSS 2039 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2040 label = "mpss"; 2041 qcom,remote-pid = <1>; 2042 }; 2043 }; 2044 2045 remoteproc_adsp: remoteproc@6800000 { 2046 compatible = "qcom,sm8550-adsp-pas"; 2047 reg = <0x0 0x06800000 0x0 0x10000>; 2048 2049 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2050 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2051 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2052 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2053 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2054 interrupt-names = "wdog", "fatal", "ready", 2055 "handover", "stop-ack"; 2056 2057 clocks = <&rpmhcc RPMH_CXO_CLK>; 2058 clock-names = "xo"; 2059 2060 power-domains = <&rpmhpd RPMHPD_LCX>, 2061 <&rpmhpd RPMHPD_LMX>; 2062 power-domain-names = "lcx", "lmx"; 2063 2064 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 2065 2066 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2067 2068 qcom,qmp = <&aoss_qmp>; 2069 2070 qcom,smem-states = <&smp2p_adsp_out 0>; 2071 qcom,smem-state-names = "stop"; 2072 2073 status = "disabled"; 2074 2075 remoteproc_adsp_glink: glink-edge { 2076 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2077 IPCC_MPROC_SIGNAL_GLINK_QMP 2078 IRQ_TYPE_EDGE_RISING>; 2079 mboxes = <&ipcc IPCC_CLIENT_LPASS 2080 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2081 2082 label = "lpass"; 2083 qcom,remote-pid = <2>; 2084 2085 fastrpc { 2086 compatible = "qcom,fastrpc"; 2087 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2088 label = "adsp"; 2089 qcom,non-secure-domain; 2090 #address-cells = <1>; 2091 #size-cells = <0>; 2092 2093 compute-cb@3 { 2094 compatible = "qcom,fastrpc-compute-cb"; 2095 reg = <3>; 2096 iommus = <&apps_smmu 0x1003 0x80>, 2097 <&apps_smmu 0x1063 0x0>; 2098 dma-coherent; 2099 }; 2100 2101 compute-cb@4 { 2102 compatible = "qcom,fastrpc-compute-cb"; 2103 reg = <4>; 2104 iommus = <&apps_smmu 0x1004 0x80>, 2105 <&apps_smmu 0x1064 0x0>; 2106 dma-coherent; 2107 }; 2108 2109 compute-cb@5 { 2110 compatible = "qcom,fastrpc-compute-cb"; 2111 reg = <5>; 2112 iommus = <&apps_smmu 0x1005 0x80>, 2113 <&apps_smmu 0x1065 0x0>; 2114 dma-coherent; 2115 }; 2116 2117 compute-cb@6 { 2118 compatible = "qcom,fastrpc-compute-cb"; 2119 reg = <6>; 2120 iommus = <&apps_smmu 0x1006 0x80>, 2121 <&apps_smmu 0x1066 0x0>; 2122 dma-coherent; 2123 }; 2124 2125 compute-cb@7 { 2126 compatible = "qcom,fastrpc-compute-cb"; 2127 reg = <7>; 2128 iommus = <&apps_smmu 0x1007 0x80>, 2129 <&apps_smmu 0x1067 0x0>; 2130 dma-coherent; 2131 }; 2132 }; 2133 2134 gpr { 2135 compatible = "qcom,gpr"; 2136 qcom,glink-channels = "adsp_apps"; 2137 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2138 qcom,intents = <512 20>; 2139 #address-cells = <1>; 2140 #size-cells = <0>; 2141 2142 q6apm: service@1 { 2143 compatible = "qcom,q6apm"; 2144 reg = <GPR_APM_MODULE_IID>; 2145 #sound-dai-cells = <0>; 2146 qcom,protection-domain = "avs/audio", 2147 "msm/adsp/audio_pd"; 2148 2149 q6apmdai: dais { 2150 compatible = "qcom,q6apm-dais"; 2151 iommus = <&apps_smmu 0x1001 0x80>, 2152 <&apps_smmu 0x1061 0x0>; 2153 }; 2154 2155 q6apmbedai: bedais { 2156 compatible = "qcom,q6apm-lpass-dais"; 2157 #sound-dai-cells = <1>; 2158 }; 2159 }; 2160 2161 q6prm: service@2 { 2162 compatible = "qcom,q6prm"; 2163 reg = <GPR_PRM_MODULE_IID>; 2164 qcom,protection-domain = "avs/audio", 2165 "msm/adsp/audio_pd"; 2166 2167 q6prmcc: clock-controller { 2168 compatible = "qcom,q6prm-lpass-clocks"; 2169 #clock-cells = <2>; 2170 }; 2171 }; 2172 }; 2173 }; 2174 }; 2175 2176 lpass_wsa2macro: codec@6aa0000 { 2177 compatible = "qcom,sm8550-lpass-wsa-macro"; 2178 reg = <0 0x06aa0000 0 0x1000>; 2179 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2180 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2181 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2182 <&lpass_vamacro>; 2183 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2184 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2185 assigned-clock-rates = <19200000>; 2186 2187 #clock-cells = <0>; 2188 clock-output-names = "wsa2-mclk"; 2189 pinctrl-names = "default"; 2190 pinctrl-0 = <&wsa2_swr_active>; 2191 #sound-dai-cells = <1>; 2192 }; 2193 2194 swr3: soundwire@6ab0000 { 2195 compatible = "qcom,soundwire-v2.0.0"; 2196 reg = <0 0x06ab0000 0 0x10000>; 2197 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2198 clocks = <&lpass_wsa2macro>; 2199 clock-names = "iface"; 2200 label = "WSA2"; 2201 2202 qcom,din-ports = <4>; 2203 qcom,dout-ports = <9>; 2204 2205 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2206 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2207 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2208 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2209 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2210 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2211 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2212 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2213 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2214 2215 #address-cells = <2>; 2216 #size-cells = <0>; 2217 #sound-dai-cells = <1>; 2218 status = "disabled"; 2219 }; 2220 2221 lpass_rxmacro: codec@6ac0000 { 2222 compatible = "qcom,sm8550-lpass-rx-macro"; 2223 reg = <0 0x06ac0000 0 0x1000>; 2224 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2225 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2226 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2227 <&lpass_vamacro>; 2228 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2229 2230 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2231 assigned-clock-rates = <19200000>; 2232 2233 #clock-cells = <0>; 2234 clock-output-names = "mclk"; 2235 pinctrl-names = "default"; 2236 pinctrl-0 = <&rx_swr_active>; 2237 #sound-dai-cells = <1>; 2238 }; 2239 2240 swr1: soundwire@6ad0000 { 2241 compatible = "qcom,soundwire-v2.0.0"; 2242 reg = <0 0x06ad0000 0 0x10000>; 2243 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2244 clocks = <&lpass_rxmacro>; 2245 clock-names = "iface"; 2246 label = "RX"; 2247 2248 qcom,din-ports = <0>; 2249 qcom,dout-ports = <10>; 2250 2251 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>; 2252 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>; 2253 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; 2254 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; 2255 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; 2256 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>; 2257 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; 2258 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2259 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; 2260 2261 #address-cells = <2>; 2262 #size-cells = <0>; 2263 #sound-dai-cells = <1>; 2264 status = "disabled"; 2265 }; 2266 2267 lpass_txmacro: codec@6ae0000 { 2268 compatible = "qcom,sm8550-lpass-tx-macro"; 2269 reg = <0 0x06ae0000 0 0x1000>; 2270 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2271 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2272 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2273 <&lpass_vamacro>; 2274 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2275 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2276 2277 assigned-clock-rates = <19200000>; 2278 2279 #clock-cells = <0>; 2280 clock-output-names = "mclk"; 2281 pinctrl-names = "default"; 2282 pinctrl-0 = <&tx_swr_active>; 2283 #sound-dai-cells = <1>; 2284 }; 2285 2286 lpass_wsamacro: codec@6b00000 { 2287 compatible = "qcom,sm8550-lpass-wsa-macro"; 2288 reg = <0 0x06b00000 0 0x1000>; 2289 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2290 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2291 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2292 <&lpass_vamacro>; 2293 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2294 2295 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2296 assigned-clock-rates = <19200000>; 2297 2298 #clock-cells = <0>; 2299 clock-output-names = "mclk"; 2300 pinctrl-names = "default"; 2301 pinctrl-0 = <&wsa_swr_active>; 2302 #sound-dai-cells = <1>; 2303 }; 2304 2305 swr0: soundwire@6b10000 { 2306 compatible = "qcom,soundwire-v2.0.0"; 2307 reg = <0 0x06b10000 0 0x10000>; 2308 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2309 clocks = <&lpass_wsamacro>; 2310 clock-names = "iface"; 2311 label = "WSA"; 2312 2313 qcom,din-ports = <4>; 2314 qcom,dout-ports = <9>; 2315 2316 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2317 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2318 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2319 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2320 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2321 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2322 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2323 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2324 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2325 2326 #address-cells = <2>; 2327 #size-cells = <0>; 2328 #sound-dai-cells = <1>; 2329 status = "disabled"; 2330 }; 2331 2332 swr2: soundwire@6d30000 { 2333 compatible = "qcom,soundwire-v2.0.0"; 2334 reg = <0 0x06d30000 0 0x10000>; 2335 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2336 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2337 interrupt-names = "core", "wakeup"; 2338 clocks = <&lpass_txmacro>; 2339 clock-names = "iface"; 2340 label = "TX"; 2341 2342 qcom,din-ports = <4>; 2343 qcom,dout-ports = <0>; 2344 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2345 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2346 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2347 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2348 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2349 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2350 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2351 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2352 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2353 2354 #address-cells = <2>; 2355 #size-cells = <0>; 2356 #sound-dai-cells = <1>; 2357 status = "disabled"; 2358 }; 2359 2360 lpass_vamacro: codec@6d44000 { 2361 compatible = "qcom,sm8550-lpass-va-macro"; 2362 reg = <0 0x06d44000 0 0x1000>; 2363 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2364 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2365 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2366 clock-names = "mclk", "macro", "dcodec"; 2367 2368 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2369 assigned-clock-rates = <19200000>; 2370 2371 #clock-cells = <0>; 2372 clock-output-names = "fsgen"; 2373 #sound-dai-cells = <1>; 2374 }; 2375 2376 lpass_tlmm: pinctrl@6e80000 { 2377 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 2378 reg = <0 0x06e80000 0 0x20000>, 2379 <0 0x07250000 0 0x10000>; 2380 gpio-controller; 2381 #gpio-cells = <2>; 2382 gpio-ranges = <&lpass_tlmm 0 0 23>; 2383 2384 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2385 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2386 clock-names = "core", "audio"; 2387 2388 tx_swr_active: tx-swr-active-state { 2389 clk-pins { 2390 pins = "gpio0"; 2391 function = "swr_tx_clk"; 2392 drive-strength = <2>; 2393 slew-rate = <1>; 2394 bias-disable; 2395 }; 2396 2397 data-pins { 2398 pins = "gpio1", "gpio2", "gpio14"; 2399 function = "swr_tx_data"; 2400 drive-strength = <2>; 2401 slew-rate = <1>; 2402 bias-bus-hold; 2403 }; 2404 }; 2405 2406 rx_swr_active: rx-swr-active-state { 2407 clk-pins { 2408 pins = "gpio3"; 2409 function = "swr_rx_clk"; 2410 drive-strength = <2>; 2411 slew-rate = <1>; 2412 bias-disable; 2413 }; 2414 2415 data-pins { 2416 pins = "gpio4", "gpio5"; 2417 function = "swr_rx_data"; 2418 drive-strength = <2>; 2419 slew-rate = <1>; 2420 bias-bus-hold; 2421 }; 2422 }; 2423 2424 dmic01_default: dmic01-default-state { 2425 clk-pins { 2426 pins = "gpio6"; 2427 function = "dmic1_clk"; 2428 drive-strength = <8>; 2429 output-high; 2430 }; 2431 2432 data-pins { 2433 pins = "gpio7"; 2434 function = "dmic1_data"; 2435 drive-strength = <8>; 2436 input-enable; 2437 }; 2438 }; 2439 2440 dmic02_default: dmic02-default-state { 2441 clk-pins { 2442 pins = "gpio8"; 2443 function = "dmic2_clk"; 2444 drive-strength = <8>; 2445 output-high; 2446 }; 2447 2448 data-pins { 2449 pins = "gpio9"; 2450 function = "dmic2_data"; 2451 drive-strength = <8>; 2452 input-enable; 2453 }; 2454 }; 2455 2456 wsa_swr_active: wsa-swr-active-state { 2457 clk-pins { 2458 pins = "gpio10"; 2459 function = "wsa_swr_clk"; 2460 drive-strength = <2>; 2461 slew-rate = <1>; 2462 bias-disable; 2463 }; 2464 2465 data-pins { 2466 pins = "gpio11"; 2467 function = "wsa_swr_data"; 2468 drive-strength = <2>; 2469 slew-rate = <1>; 2470 bias-bus-hold; 2471 }; 2472 }; 2473 2474 wsa2_swr_active: wsa2-swr-active-state { 2475 clk-pins { 2476 pins = "gpio15"; 2477 function = "wsa2_swr_clk"; 2478 drive-strength = <2>; 2479 slew-rate = <1>; 2480 bias-disable; 2481 }; 2482 2483 data-pins { 2484 pins = "gpio16"; 2485 function = "wsa2_swr_data"; 2486 drive-strength = <2>; 2487 slew-rate = <1>; 2488 bias-bus-hold; 2489 }; 2490 }; 2491 }; 2492 2493 lpass_lpiaon_noc: interconnect@7400000 { 2494 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 2495 reg = <0 0x07400000 0 0x19080>; 2496 #interconnect-cells = <2>; 2497 qcom,bcm-voters = <&apps_bcm_voter>; 2498 }; 2499 2500 lpass_lpicx_noc: interconnect@7430000 { 2501 compatible = "qcom,sm8550-lpass-lpicx-noc"; 2502 reg = <0 0x07430000 0 0x3a200>; 2503 #interconnect-cells = <2>; 2504 qcom,bcm-voters = <&apps_bcm_voter>; 2505 }; 2506 2507 lpass_ag_noc: interconnect@7e40000 { 2508 compatible = "qcom,sm8550-lpass-ag-noc"; 2509 reg = <0 0x07e40000 0 0xe080>; 2510 #interconnect-cells = <2>; 2511 qcom,bcm-voters = <&apps_bcm_voter>; 2512 }; 2513 2514 sdhc_2: mmc@8804000 { 2515 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 2516 reg = <0 0x08804000 0 0x1000>; 2517 2518 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2519 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2520 interrupt-names = "hc_irq", "pwr_irq"; 2521 2522 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2523 <&gcc GCC_SDCC2_APPS_CLK>, 2524 <&rpmhcc RPMH_CXO_CLK>; 2525 clock-names = "iface", "core", "xo"; 2526 iommus = <&apps_smmu 0x540 0>; 2527 qcom,dll-config = <0x0007642c>; 2528 qcom,ddr-config = <0x80040868>; 2529 power-domains = <&rpmhpd RPMHPD_CX>; 2530 operating-points-v2 = <&sdhc2_opp_table>; 2531 2532 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2533 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2534 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 2535 bus-width = <4>; 2536 dma-coherent; 2537 2538 /* Forbid SDR104/SDR50 - broken hw! */ 2539 sdhci-caps-mask = <0x3 0>; 2540 2541 status = "disabled"; 2542 2543 sdhc2_opp_table: opp-table { 2544 compatible = "operating-points-v2"; 2545 2546 opp-19200000 { 2547 opp-hz = /bits/ 64 <19200000>; 2548 required-opps = <&rpmhpd_opp_min_svs>; 2549 }; 2550 2551 opp-50000000 { 2552 opp-hz = /bits/ 64 <50000000>; 2553 required-opps = <&rpmhpd_opp_low_svs>; 2554 }; 2555 2556 opp-100000000 { 2557 opp-hz = /bits/ 64 <100000000>; 2558 required-opps = <&rpmhpd_opp_svs>; 2559 }; 2560 2561 opp-202000000 { 2562 opp-hz = /bits/ 64 <202000000>; 2563 required-opps = <&rpmhpd_opp_svs_l1>; 2564 }; 2565 }; 2566 }; 2567 2568 videocc: clock-controller@aaf0000 { 2569 compatible = "qcom,sm8550-videocc"; 2570 reg = <0 0x0aaf0000 0 0x10000>; 2571 clocks = <&bi_tcxo_div2>, 2572 <&gcc GCC_VIDEO_AHB_CLK>; 2573 power-domains = <&rpmhpd RPMHPD_MMCX>; 2574 required-opps = <&rpmhpd_opp_low_svs>; 2575 #clock-cells = <1>; 2576 #reset-cells = <1>; 2577 #power-domain-cells = <1>; 2578 }; 2579 2580 mdss: display-subsystem@ae00000 { 2581 compatible = "qcom,sm8550-mdss"; 2582 reg = <0 0x0ae00000 0 0x1000>; 2583 reg-names = "mdss"; 2584 2585 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2586 interrupt-controller; 2587 #interrupt-cells = <1>; 2588 2589 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2590 <&gcc GCC_DISP_AHB_CLK>, 2591 <&gcc GCC_DISP_HF_AXI_CLK>, 2592 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2593 2594 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2595 2596 power-domains = <&dispcc MDSS_GDSC>; 2597 2598 interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>; 2599 interconnect-names = "mdp0-mem"; 2600 2601 iommus = <&apps_smmu 0x1c00 0x2>; 2602 2603 #address-cells = <2>; 2604 #size-cells = <2>; 2605 ranges; 2606 2607 status = "disabled"; 2608 2609 mdss_mdp: display-controller@ae01000 { 2610 compatible = "qcom,sm8550-dpu"; 2611 reg = <0 0x0ae01000 0 0x8f000>, 2612 <0 0x0aeb0000 0 0x2008>; 2613 reg-names = "mdp", "vbif"; 2614 2615 interrupt-parent = <&mdss>; 2616 interrupts = <0>; 2617 2618 clocks = <&gcc GCC_DISP_AHB_CLK>, 2619 <&gcc GCC_DISP_HF_AXI_CLK>, 2620 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2621 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2622 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2623 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2624 clock-names = "bus", 2625 "nrt_bus", 2626 "iface", 2627 "lut", 2628 "core", 2629 "vsync"; 2630 2631 power-domains = <&rpmhpd RPMHPD_MMCX>; 2632 2633 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2634 assigned-clock-rates = <19200000>; 2635 2636 operating-points-v2 = <&mdp_opp_table>; 2637 2638 ports { 2639 #address-cells = <1>; 2640 #size-cells = <0>; 2641 2642 port@0 { 2643 reg = <0>; 2644 dpu_intf1_out: endpoint { 2645 remote-endpoint = <&mdss_dsi0_in>; 2646 }; 2647 }; 2648 2649 port@1 { 2650 reg = <1>; 2651 dpu_intf2_out: endpoint { 2652 remote-endpoint = <&mdss_dsi1_in>; 2653 }; 2654 }; 2655 2656 port@2 { 2657 reg = <2>; 2658 dpu_intf0_out: endpoint { 2659 remote-endpoint = <&mdss_dp0_in>; 2660 }; 2661 }; 2662 }; 2663 2664 mdp_opp_table: opp-table { 2665 compatible = "operating-points-v2"; 2666 2667 opp-200000000 { 2668 opp-hz = /bits/ 64 <200000000>; 2669 required-opps = <&rpmhpd_opp_low_svs>; 2670 }; 2671 2672 opp-325000000 { 2673 opp-hz = /bits/ 64 <325000000>; 2674 required-opps = <&rpmhpd_opp_svs>; 2675 }; 2676 2677 opp-375000000 { 2678 opp-hz = /bits/ 64 <375000000>; 2679 required-opps = <&rpmhpd_opp_svs_l1>; 2680 }; 2681 2682 opp-514000000 { 2683 opp-hz = /bits/ 64 <514000000>; 2684 required-opps = <&rpmhpd_opp_nom>; 2685 }; 2686 }; 2687 }; 2688 2689 mdss_dp0: displayport-controller@ae90000 { 2690 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 2691 reg = <0 0xae90000 0 0x200>, 2692 <0 0xae90200 0 0x200>, 2693 <0 0xae90400 0 0xc00>, 2694 <0 0xae91000 0 0x400>, 2695 <0 0xae91400 0 0x400>; 2696 interrupt-parent = <&mdss>; 2697 interrupts = <12>; 2698 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2699 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2700 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2701 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2702 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2703 clock-names = "core_iface", 2704 "core_aux", 2705 "ctrl_link", 2706 "ctrl_link_iface", 2707 "stream_pixel"; 2708 2709 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2710 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2711 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2712 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2713 2714 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 2715 phy-names = "dp"; 2716 2717 #sound-dai-cells = <0>; 2718 2719 operating-points-v2 = <&dp_opp_table>; 2720 power-domains = <&rpmhpd RPMHPD_MMCX>; 2721 2722 status = "disabled"; 2723 2724 ports { 2725 #address-cells = <1>; 2726 #size-cells = <0>; 2727 2728 port@0 { 2729 reg = <0>; 2730 mdss_dp0_in: endpoint { 2731 remote-endpoint = <&dpu_intf0_out>; 2732 }; 2733 }; 2734 2735 port@1 { 2736 reg = <1>; 2737 mdss_dp0_out: endpoint { 2738 }; 2739 }; 2740 }; 2741 2742 dp_opp_table: opp-table { 2743 compatible = "operating-points-v2"; 2744 2745 opp-162000000 { 2746 opp-hz = /bits/ 64 <162000000>; 2747 required-opps = <&rpmhpd_opp_low_svs_d1>; 2748 }; 2749 2750 opp-270000000 { 2751 opp-hz = /bits/ 64 <270000000>; 2752 required-opps = <&rpmhpd_opp_low_svs>; 2753 }; 2754 2755 opp-540000000 { 2756 opp-hz = /bits/ 64 <540000000>; 2757 required-opps = <&rpmhpd_opp_svs_l1>; 2758 }; 2759 2760 opp-810000000 { 2761 opp-hz = /bits/ 64 <810000000>; 2762 required-opps = <&rpmhpd_opp_nom>; 2763 }; 2764 }; 2765 }; 2766 2767 mdss_dsi0: dsi@ae94000 { 2768 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2769 reg = <0 0x0ae94000 0 0x400>; 2770 reg-names = "dsi_ctrl"; 2771 2772 interrupt-parent = <&mdss>; 2773 interrupts = <4>; 2774 2775 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2776 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2777 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2778 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2779 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2780 <&gcc GCC_DISP_HF_AXI_CLK>; 2781 clock-names = "byte", 2782 "byte_intf", 2783 "pixel", 2784 "core", 2785 "iface", 2786 "bus"; 2787 2788 power-domains = <&rpmhpd RPMHPD_MMCX>; 2789 2790 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2791 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2792 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2793 <&mdss_dsi0_phy 1>; 2794 2795 operating-points-v2 = <&mdss_dsi_opp_table>; 2796 2797 phys = <&mdss_dsi0_phy>; 2798 phy-names = "dsi"; 2799 2800 #address-cells = <1>; 2801 #size-cells = <0>; 2802 2803 status = "disabled"; 2804 2805 ports { 2806 #address-cells = <1>; 2807 #size-cells = <0>; 2808 2809 port@0 { 2810 reg = <0>; 2811 mdss_dsi0_in: endpoint { 2812 remote-endpoint = <&dpu_intf1_out>; 2813 }; 2814 }; 2815 2816 port@1 { 2817 reg = <1>; 2818 mdss_dsi0_out: endpoint { 2819 }; 2820 }; 2821 }; 2822 2823 mdss_dsi_opp_table: opp-table { 2824 compatible = "operating-points-v2"; 2825 2826 opp-187500000 { 2827 opp-hz = /bits/ 64 <187500000>; 2828 required-opps = <&rpmhpd_opp_low_svs>; 2829 }; 2830 2831 opp-300000000 { 2832 opp-hz = /bits/ 64 <300000000>; 2833 required-opps = <&rpmhpd_opp_svs>; 2834 }; 2835 2836 opp-358000000 { 2837 opp-hz = /bits/ 64 <358000000>; 2838 required-opps = <&rpmhpd_opp_svs_l1>; 2839 }; 2840 }; 2841 }; 2842 2843 mdss_dsi0_phy: phy@ae95000 { 2844 compatible = "qcom,sm8550-dsi-phy-4nm"; 2845 reg = <0 0x0ae95000 0 0x200>, 2846 <0 0x0ae95200 0 0x280>, 2847 <0 0x0ae95500 0 0x400>; 2848 reg-names = "dsi_phy", 2849 "dsi_phy_lane", 2850 "dsi_pll"; 2851 2852 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2853 <&rpmhcc RPMH_CXO_CLK>; 2854 clock-names = "iface", "ref"; 2855 2856 #clock-cells = <1>; 2857 #phy-cells = <0>; 2858 2859 status = "disabled"; 2860 }; 2861 2862 mdss_dsi1: dsi@ae96000 { 2863 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2864 reg = <0 0x0ae96000 0 0x400>; 2865 reg-names = "dsi_ctrl"; 2866 2867 interrupt-parent = <&mdss>; 2868 interrupts = <5>; 2869 2870 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2871 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2872 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2873 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2874 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2875 <&gcc GCC_DISP_HF_AXI_CLK>; 2876 clock-names = "byte", 2877 "byte_intf", 2878 "pixel", 2879 "core", 2880 "iface", 2881 "bus"; 2882 2883 power-domains = <&rpmhpd RPMHPD_MMCX>; 2884 2885 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2886 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2887 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2888 <&mdss_dsi1_phy 1>; 2889 2890 operating-points-v2 = <&mdss_dsi_opp_table>; 2891 2892 phys = <&mdss_dsi1_phy>; 2893 phy-names = "dsi"; 2894 2895 #address-cells = <1>; 2896 #size-cells = <0>; 2897 2898 status = "disabled"; 2899 2900 ports { 2901 #address-cells = <1>; 2902 #size-cells = <0>; 2903 2904 port@0 { 2905 reg = <0>; 2906 mdss_dsi1_in: endpoint { 2907 remote-endpoint = <&dpu_intf2_out>; 2908 }; 2909 }; 2910 2911 port@1 { 2912 reg = <1>; 2913 mdss_dsi1_out: endpoint { 2914 }; 2915 }; 2916 }; 2917 }; 2918 2919 mdss_dsi1_phy: phy@ae97000 { 2920 compatible = "qcom,sm8550-dsi-phy-4nm"; 2921 reg = <0 0x0ae97000 0 0x200>, 2922 <0 0x0ae97200 0 0x280>, 2923 <0 0x0ae97500 0 0x400>; 2924 reg-names = "dsi_phy", 2925 "dsi_phy_lane", 2926 "dsi_pll"; 2927 2928 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2929 <&rpmhcc RPMH_CXO_CLK>; 2930 clock-names = "iface", "ref"; 2931 2932 #clock-cells = <1>; 2933 #phy-cells = <0>; 2934 2935 status = "disabled"; 2936 }; 2937 }; 2938 2939 dispcc: clock-controller@af00000 { 2940 compatible = "qcom,sm8550-dispcc"; 2941 reg = <0 0x0af00000 0 0x20000>; 2942 clocks = <&bi_tcxo_div2>, 2943 <&bi_tcxo_ao_div2>, 2944 <&gcc GCC_DISP_AHB_CLK>, 2945 <&sleep_clk>, 2946 <&mdss_dsi0_phy 0>, 2947 <&mdss_dsi0_phy 1>, 2948 <&mdss_dsi1_phy 0>, 2949 <&mdss_dsi1_phy 1>, 2950 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2951 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 2952 <0>, /* dp1 */ 2953 <0>, 2954 <0>, /* dp2 */ 2955 <0>, 2956 <0>, /* dp3 */ 2957 <0>; 2958 power-domains = <&rpmhpd RPMHPD_MMCX>; 2959 required-opps = <&rpmhpd_opp_low_svs>; 2960 #clock-cells = <1>; 2961 #reset-cells = <1>; 2962 #power-domain-cells = <1>; 2963 }; 2964 2965 usb_1_hsphy: phy@88e3000 { 2966 compatible = "qcom,sm8550-snps-eusb2-phy"; 2967 reg = <0x0 0x088e3000 0x0 0x154>; 2968 #phy-cells = <0>; 2969 2970 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 2971 clock-names = "ref"; 2972 2973 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2974 2975 status = "disabled"; 2976 }; 2977 2978 usb_dp_qmpphy: phy@88e8000 { 2979 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 2980 reg = <0x0 0x088e8000 0x0 0x3000>; 2981 2982 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2983 <&rpmhcc RPMH_CXO_CLK>, 2984 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2985 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2986 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2987 2988 power-domains = <&gcc USB3_PHY_GDSC>; 2989 2990 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2991 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2992 reset-names = "phy", "common"; 2993 2994 #clock-cells = <1>; 2995 #phy-cells = <1>; 2996 2997 status = "disabled"; 2998 2999 ports { 3000 #address-cells = <1>; 3001 #size-cells = <0>; 3002 3003 port@0 { 3004 reg = <0>; 3005 3006 usb_dp_qmpphy_out: endpoint { 3007 }; 3008 }; 3009 3010 port@1 { 3011 reg = <1>; 3012 3013 usb_dp_qmpphy_usb_ss_in: endpoint { 3014 }; 3015 }; 3016 3017 port@2 { 3018 reg = <2>; 3019 3020 usb_dp_qmpphy_dp_in: endpoint { 3021 }; 3022 }; 3023 }; 3024 }; 3025 3026 usb_1: usb@a6f8800 { 3027 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 3028 reg = <0x0 0x0a6f8800 0x0 0x400>; 3029 #address-cells = <2>; 3030 #size-cells = <2>; 3031 ranges; 3032 3033 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3034 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3035 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3036 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3037 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3038 <&tcsr TCSR_USB3_CLKREF_EN>; 3039 clock-names = "cfg_noc", 3040 "core", 3041 "iface", 3042 "sleep", 3043 "mock_utmi", 3044 "xo"; 3045 3046 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3047 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3048 assigned-clock-rates = <19200000>, <200000000>; 3049 3050 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3051 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3052 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3053 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 3054 interrupt-names = "hs_phy_irq", 3055 "ss_phy_irq", 3056 "dm_hs_phy_irq", 3057 "dp_hs_phy_irq"; 3058 3059 power-domains = <&gcc USB30_PRIM_GDSC>; 3060 required-opps = <&rpmhpd_opp_nom>; 3061 3062 resets = <&gcc GCC_USB30_PRIM_BCR>; 3063 3064 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3065 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3066 interconnect-names = "usb-ddr", "apps-usb"; 3067 3068 status = "disabled"; 3069 3070 usb_1_dwc3: usb@a600000 { 3071 compatible = "snps,dwc3"; 3072 reg = <0x0 0x0a600000 0x0 0xcd00>; 3073 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3074 iommus = <&apps_smmu 0x40 0x0>; 3075 snps,dis_u2_susphy_quirk; 3076 snps,dis_enblslpm_quirk; 3077 snps,usb3_lpm_capable; 3078 phys = <&usb_1_hsphy>, 3079 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 3080 phy-names = "usb2-phy", "usb3-phy"; 3081 3082 ports { 3083 #address-cells = <1>; 3084 #size-cells = <0>; 3085 3086 port@0 { 3087 reg = <0>; 3088 3089 usb_1_dwc3_hs: endpoint { 3090 }; 3091 }; 3092 3093 port@1 { 3094 reg = <1>; 3095 3096 usb_1_dwc3_ss: endpoint { 3097 }; 3098 }; 3099 }; 3100 }; 3101 }; 3102 3103 pdc: interrupt-controller@b220000 { 3104 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 3105 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3106 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3107 <125 63 1>, <126 716 12>, 3108 <138 251 5>; 3109 #interrupt-cells = <2>; 3110 interrupt-parent = <&intc>; 3111 interrupt-controller; 3112 }; 3113 3114 tsens0: thermal-sensor@c271000 { 3115 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3116 reg = <0 0x0c271000 0 0x1000>, /* TM */ 3117 <0 0x0c222000 0 0x1000>; /* SROT */ 3118 #qcom,sensors = <16>; 3119 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 3121 interrupt-names = "uplow", "critical"; 3122 #thermal-sensor-cells = <1>; 3123 }; 3124 3125 tsens1: thermal-sensor@c272000 { 3126 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3127 reg = <0 0x0c272000 0 0x1000>, /* TM */ 3128 <0 0x0c223000 0 0x1000>; /* SROT */ 3129 #qcom,sensors = <16>; 3130 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 3132 interrupt-names = "uplow", "critical"; 3133 #thermal-sensor-cells = <1>; 3134 }; 3135 3136 tsens2: thermal-sensor@c273000 { 3137 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3138 reg = <0 0x0c273000 0 0x1000>, /* TM */ 3139 <0 0x0c224000 0 0x1000>; /* SROT */ 3140 #qcom,sensors = <16>; 3141 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 3143 interrupt-names = "uplow", "critical"; 3144 #thermal-sensor-cells = <1>; 3145 }; 3146 3147 aoss_qmp: power-management@c300000 { 3148 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 3149 reg = <0 0x0c300000 0 0x400>; 3150 interrupt-parent = <&ipcc>; 3151 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3152 IRQ_TYPE_EDGE_RISING>; 3153 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3154 3155 #clock-cells = <0>; 3156 }; 3157 3158 sram@c3f0000 { 3159 compatible = "qcom,rpmh-stats"; 3160 reg = <0 0x0c3f0000 0 0x400>; 3161 }; 3162 3163 spmi_bus: spmi@c400000 { 3164 compatible = "qcom,spmi-pmic-arb"; 3165 reg = <0 0x0c400000 0 0x3000>, 3166 <0 0x0c500000 0 0x400000>, 3167 <0 0x0c440000 0 0x80000>, 3168 <0 0x0c4c0000 0 0x20000>, 3169 <0 0x0c42d000 0 0x4000>; 3170 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3171 interrupt-names = "periph_irq"; 3172 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3173 qcom,ee = <0>; 3174 qcom,channel = <0>; 3175 qcom,bus-id = <0>; 3176 #address-cells = <2>; 3177 #size-cells = <0>; 3178 interrupt-controller; 3179 #interrupt-cells = <4>; 3180 }; 3181 3182 tlmm: pinctrl@f100000 { 3183 compatible = "qcom,sm8550-tlmm"; 3184 reg = <0 0x0f100000 0 0x300000>; 3185 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3186 gpio-controller; 3187 #gpio-cells = <2>; 3188 interrupt-controller; 3189 #interrupt-cells = <2>; 3190 gpio-ranges = <&tlmm 0 0 211>; 3191 wakeup-parent = <&pdc>; 3192 3193 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3194 /* SDA, SCL */ 3195 pins = "gpio16", "gpio17"; 3196 function = "i2chub0_se0"; 3197 drive-strength = <2>; 3198 bias-pull-up; 3199 }; 3200 3201 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 3202 /* SDA, SCL */ 3203 pins = "gpio18", "gpio19"; 3204 function = "i2chub0_se1"; 3205 drive-strength = <2>; 3206 bias-pull-up; 3207 }; 3208 3209 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 3210 /* SDA, SCL */ 3211 pins = "gpio20", "gpio21"; 3212 function = "i2chub0_se2"; 3213 drive-strength = <2>; 3214 bias-pull-up; 3215 }; 3216 3217 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 3218 /* SDA, SCL */ 3219 pins = "gpio22", "gpio23"; 3220 function = "i2chub0_se3"; 3221 drive-strength = <2>; 3222 bias-pull-up; 3223 }; 3224 3225 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 3226 /* SDA, SCL */ 3227 pins = "gpio4", "gpio5"; 3228 function = "i2chub0_se4"; 3229 drive-strength = <2>; 3230 bias-pull-up; 3231 }; 3232 3233 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 3234 /* SDA, SCL */ 3235 pins = "gpio6", "gpio7"; 3236 function = "i2chub0_se5"; 3237 drive-strength = <2>; 3238 bias-pull-up; 3239 }; 3240 3241 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 3242 /* SDA, SCL */ 3243 pins = "gpio8", "gpio9"; 3244 function = "i2chub0_se6"; 3245 drive-strength = <2>; 3246 bias-pull-up; 3247 }; 3248 3249 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 3250 /* SDA, SCL */ 3251 pins = "gpio10", "gpio11"; 3252 function = "i2chub0_se7"; 3253 drive-strength = <2>; 3254 bias-pull-up; 3255 }; 3256 3257 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 3258 /* SDA, SCL */ 3259 pins = "gpio206", "gpio207"; 3260 function = "i2chub0_se8"; 3261 drive-strength = <2>; 3262 bias-pull-up; 3263 }; 3264 3265 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 3266 /* SDA, SCL */ 3267 pins = "gpio84", "gpio85"; 3268 function = "i2chub0_se9"; 3269 drive-strength = <2>; 3270 bias-pull-up; 3271 }; 3272 3273 pcie0_default_state: pcie0-default-state { 3274 perst-pins { 3275 pins = "gpio94"; 3276 function = "gpio"; 3277 drive-strength = <2>; 3278 bias-pull-down; 3279 }; 3280 3281 clkreq-pins { 3282 pins = "gpio95"; 3283 function = "pcie0_clk_req_n"; 3284 drive-strength = <2>; 3285 bias-pull-up; 3286 }; 3287 3288 wake-pins { 3289 pins = "gpio96"; 3290 function = "gpio"; 3291 drive-strength = <2>; 3292 bias-pull-up; 3293 }; 3294 }; 3295 3296 pcie1_default_state: pcie1-default-state { 3297 perst-pins { 3298 pins = "gpio97"; 3299 function = "gpio"; 3300 drive-strength = <2>; 3301 bias-pull-down; 3302 }; 3303 3304 clkreq-pins { 3305 pins = "gpio98"; 3306 function = "pcie1_clk_req_n"; 3307 drive-strength = <2>; 3308 bias-pull-up; 3309 }; 3310 3311 wake-pins { 3312 pins = "gpio99"; 3313 function = "gpio"; 3314 drive-strength = <2>; 3315 bias-pull-up; 3316 }; 3317 }; 3318 3319 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3320 /* SDA, SCL */ 3321 pins = "gpio28", "gpio29"; 3322 function = "qup1_se0"; 3323 drive-strength = <2>; 3324 bias-pull-up = <2200>; 3325 }; 3326 3327 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3328 /* SDA, SCL */ 3329 pins = "gpio32", "gpio33"; 3330 function = "qup1_se1"; 3331 drive-strength = <2>; 3332 bias-pull-up = <2200>; 3333 }; 3334 3335 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3336 /* SDA, SCL */ 3337 pins = "gpio36", "gpio37"; 3338 function = "qup1_se2"; 3339 drive-strength = <2>; 3340 bias-pull-up = <2200>; 3341 }; 3342 3343 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3344 /* SDA, SCL */ 3345 pins = "gpio40", "gpio41"; 3346 function = "qup1_se3"; 3347 drive-strength = <2>; 3348 bias-pull-up = <2200>; 3349 }; 3350 3351 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3352 /* SDA, SCL */ 3353 pins = "gpio44", "gpio45"; 3354 function = "qup1_se4"; 3355 drive-strength = <2>; 3356 bias-pull-up = <2200>; 3357 }; 3358 3359 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3360 /* SDA, SCL */ 3361 pins = "gpio52", "gpio53"; 3362 function = "qup1_se5"; 3363 drive-strength = <2>; 3364 bias-pull-up = <2200>; 3365 }; 3366 3367 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3368 /* SDA, SCL */ 3369 pins = "gpio48", "gpio49"; 3370 function = "qup1_se6"; 3371 drive-strength = <2>; 3372 bias-pull-up = <2200>; 3373 }; 3374 3375 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3376 scl-pins { 3377 pins = "gpio57"; 3378 function = "qup2_se0_l1_mira"; 3379 drive-strength = <2>; 3380 bias-pull-up = <2200>; 3381 }; 3382 3383 sda-pins { 3384 pins = "gpio56"; 3385 function = "qup2_se0_l0_mira"; 3386 drive-strength = <2>; 3387 bias-pull-up = <2200>; 3388 }; 3389 }; 3390 3391 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3392 /* SDA, SCL */ 3393 pins = "gpio60", "gpio61"; 3394 function = "qup2_se1"; 3395 drive-strength = <2>; 3396 bias-pull-up = <2200>; 3397 }; 3398 3399 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3400 /* SDA, SCL */ 3401 pins = "gpio64", "gpio65"; 3402 function = "qup2_se2"; 3403 drive-strength = <2>; 3404 bias-pull-up = <2200>; 3405 }; 3406 3407 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3408 /* SDA, SCL */ 3409 pins = "gpio68", "gpio69"; 3410 function = "qup2_se3"; 3411 drive-strength = <2>; 3412 bias-pull-up = <2200>; 3413 }; 3414 3415 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3416 /* SDA, SCL */ 3417 pins = "gpio2", "gpio3"; 3418 function = "qup2_se4"; 3419 drive-strength = <2>; 3420 bias-pull-up = <2200>; 3421 }; 3422 3423 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3424 /* SDA, SCL */ 3425 pins = "gpio80", "gpio81"; 3426 function = "qup2_se5"; 3427 drive-strength = <2>; 3428 bias-pull-up = <2200>; 3429 }; 3430 3431 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3432 /* SDA, SCL */ 3433 pins = "gpio72", "gpio106"; 3434 function = "qup2_se7"; 3435 drive-strength = <2>; 3436 bias-pull-up = <2200>; 3437 }; 3438 3439 qup_spi0_cs: qup-spi0-cs-state { 3440 pins = "gpio31"; 3441 function = "qup1_se0"; 3442 drive-strength = <6>; 3443 bias-disable; 3444 }; 3445 3446 qup_spi0_data_clk: qup-spi0-data-clk-state { 3447 /* MISO, MOSI, CLK */ 3448 pins = "gpio28", "gpio29", "gpio30"; 3449 function = "qup1_se0"; 3450 drive-strength = <6>; 3451 bias-disable; 3452 }; 3453 3454 qup_spi1_cs: qup-spi1-cs-state { 3455 pins = "gpio35"; 3456 function = "qup1_se1"; 3457 drive-strength = <6>; 3458 bias-disable; 3459 }; 3460 3461 qup_spi1_data_clk: qup-spi1-data-clk-state { 3462 /* MISO, MOSI, CLK */ 3463 pins = "gpio32", "gpio33", "gpio34"; 3464 function = "qup1_se1"; 3465 drive-strength = <6>; 3466 bias-disable; 3467 }; 3468 3469 qup_spi2_cs: qup-spi2-cs-state { 3470 pins = "gpio39"; 3471 function = "qup1_se2"; 3472 drive-strength = <6>; 3473 bias-disable; 3474 }; 3475 3476 qup_spi2_data_clk: qup-spi2-data-clk-state { 3477 /* MISO, MOSI, CLK */ 3478 pins = "gpio36", "gpio37", "gpio38"; 3479 function = "qup1_se2"; 3480 drive-strength = <6>; 3481 bias-disable; 3482 }; 3483 3484 qup_spi3_cs: qup-spi3-cs-state { 3485 pins = "gpio43"; 3486 function = "qup1_se3"; 3487 drive-strength = <6>; 3488 bias-disable; 3489 }; 3490 3491 qup_spi3_data_clk: qup-spi3-data-clk-state { 3492 /* MISO, MOSI, CLK */ 3493 pins = "gpio40", "gpio41", "gpio42"; 3494 function = "qup1_se3"; 3495 drive-strength = <6>; 3496 bias-disable; 3497 }; 3498 3499 qup_spi4_cs: qup-spi4-cs-state { 3500 pins = "gpio47"; 3501 function = "qup1_se4"; 3502 drive-strength = <6>; 3503 bias-disable; 3504 }; 3505 3506 qup_spi4_data_clk: qup-spi4-data-clk-state { 3507 /* MISO, MOSI, CLK */ 3508 pins = "gpio44", "gpio45", "gpio46"; 3509 function = "qup1_se4"; 3510 drive-strength = <6>; 3511 bias-disable; 3512 }; 3513 3514 qup_spi5_cs: qup-spi5-cs-state { 3515 pins = "gpio55"; 3516 function = "qup1_se5"; 3517 drive-strength = <6>; 3518 bias-disable; 3519 }; 3520 3521 qup_spi5_data_clk: qup-spi5-data-clk-state { 3522 /* MISO, MOSI, CLK */ 3523 pins = "gpio52", "gpio53", "gpio54"; 3524 function = "qup1_se5"; 3525 drive-strength = <6>; 3526 bias-disable; 3527 }; 3528 3529 qup_spi6_cs: qup-spi6-cs-state { 3530 pins = "gpio51"; 3531 function = "qup1_se6"; 3532 drive-strength = <6>; 3533 bias-disable; 3534 }; 3535 3536 qup_spi6_data_clk: qup-spi6-data-clk-state { 3537 /* MISO, MOSI, CLK */ 3538 pins = "gpio48", "gpio49", "gpio50"; 3539 function = "qup1_se6"; 3540 drive-strength = <6>; 3541 bias-disable; 3542 }; 3543 3544 qup_spi8_cs: qup-spi8-cs-state { 3545 pins = "gpio59"; 3546 function = "qup2_se0_l3_mira"; 3547 drive-strength = <6>; 3548 bias-disable; 3549 }; 3550 3551 qup_spi8_data_clk: qup-spi8-data-clk-state { 3552 /* MISO, MOSI, CLK */ 3553 pins = "gpio56", "gpio57", "gpio58"; 3554 function = "qup2_se0_l2_mira"; 3555 drive-strength = <6>; 3556 bias-disable; 3557 }; 3558 3559 qup_spi9_cs: qup-spi9-cs-state { 3560 pins = "gpio63"; 3561 function = "qup2_se1"; 3562 drive-strength = <6>; 3563 bias-disable; 3564 }; 3565 3566 qup_spi9_data_clk: qup-spi9-data-clk-state { 3567 /* MISO, MOSI, CLK */ 3568 pins = "gpio60", "gpio61", "gpio62"; 3569 function = "qup2_se1"; 3570 drive-strength = <6>; 3571 bias-disable; 3572 }; 3573 3574 qup_spi10_cs: qup-spi10-cs-state { 3575 pins = "gpio67"; 3576 function = "qup2_se2"; 3577 drive-strength = <6>; 3578 bias-disable; 3579 }; 3580 3581 qup_spi10_data_clk: qup-spi10-data-clk-state { 3582 /* MISO, MOSI, CLK */ 3583 pins = "gpio64", "gpio65", "gpio66"; 3584 function = "qup2_se2"; 3585 drive-strength = <6>; 3586 bias-disable; 3587 }; 3588 3589 qup_spi11_cs: qup-spi11-cs-state { 3590 pins = "gpio71"; 3591 function = "qup2_se3"; 3592 drive-strength = <6>; 3593 bias-disable; 3594 }; 3595 3596 qup_spi11_data_clk: qup-spi11-data-clk-state { 3597 /* MISO, MOSI, CLK */ 3598 pins = "gpio68", "gpio69", "gpio70"; 3599 function = "qup2_se3"; 3600 drive-strength = <6>; 3601 bias-disable; 3602 }; 3603 3604 qup_spi12_cs: qup-spi12-cs-state { 3605 pins = "gpio119"; 3606 function = "qup2_se4"; 3607 drive-strength = <6>; 3608 bias-disable; 3609 }; 3610 3611 qup_spi12_data_clk: qup-spi12-data-clk-state { 3612 /* MISO, MOSI, CLK */ 3613 pins = "gpio2", "gpio3", "gpio118"; 3614 function = "qup2_se4"; 3615 drive-strength = <6>; 3616 bias-disable; 3617 }; 3618 3619 qup_spi13_cs: qup-spi13-cs-state { 3620 pins = "gpio83"; 3621 function = "qup2_se5"; 3622 drive-strength = <6>; 3623 bias-disable; 3624 }; 3625 3626 qup_spi13_data_clk: qup-spi13-data-clk-state { 3627 /* MISO, MOSI, CLK */ 3628 pins = "gpio80", "gpio81", "gpio82"; 3629 function = "qup2_se5"; 3630 drive-strength = <6>; 3631 bias-disable; 3632 }; 3633 3634 qup_spi15_cs: qup-spi15-cs-state { 3635 pins = "gpio75"; 3636 function = "qup2_se7"; 3637 drive-strength = <6>; 3638 bias-disable; 3639 }; 3640 3641 qup_spi15_data_clk: qup-spi15-data-clk-state { 3642 /* MISO, MOSI, CLK */ 3643 pins = "gpio72", "gpio106", "gpio74"; 3644 function = "qup2_se7"; 3645 drive-strength = <6>; 3646 bias-disable; 3647 }; 3648 3649 qup_uart7_default: qup-uart7-default-state { 3650 /* TX, RX */ 3651 pins = "gpio26", "gpio27"; 3652 function = "qup1_se7"; 3653 drive-strength = <2>; 3654 bias-disable; 3655 }; 3656 3657 qup_uart14_default: qup-uart14-default-state { 3658 /* TX, RX */ 3659 pins = "gpio78", "gpio79"; 3660 function = "qup2_se6"; 3661 drive-strength = <2>; 3662 bias-pull-up; 3663 }; 3664 3665 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 3666 /* CTS, RTS */ 3667 pins = "gpio76", "gpio77"; 3668 function = "qup2_se6"; 3669 drive-strength = <2>; 3670 bias-pull-down; 3671 }; 3672 3673 sdc2_sleep: sdc2-sleep-state { 3674 clk-pins { 3675 pins = "sdc2_clk"; 3676 bias-disable; 3677 drive-strength = <2>; 3678 }; 3679 3680 cmd-pins { 3681 pins = "sdc2_cmd"; 3682 bias-pull-up; 3683 drive-strength = <2>; 3684 }; 3685 3686 data-pins { 3687 pins = "sdc2_data"; 3688 bias-pull-up; 3689 drive-strength = <2>; 3690 }; 3691 }; 3692 3693 sdc2_default: sdc2-default-state { 3694 clk-pins { 3695 pins = "sdc2_clk"; 3696 bias-disable; 3697 drive-strength = <16>; 3698 }; 3699 3700 cmd-pins { 3701 pins = "sdc2_cmd"; 3702 bias-pull-up; 3703 drive-strength = <10>; 3704 }; 3705 3706 data-pins { 3707 pins = "sdc2_data"; 3708 bias-pull-up; 3709 drive-strength = <10>; 3710 }; 3711 }; 3712 }; 3713 3714 apps_smmu: iommu@15000000 { 3715 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3716 reg = <0 0x15000000 0 0x100000>; 3717 #iommu-cells = <2>; 3718 #global-interrupts = <1>; 3719 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3721 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3722 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3724 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3727 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3728 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3730 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3731 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3732 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3733 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3734 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3736 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3740 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3741 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3742 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3743 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3744 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3745 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3746 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3747 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3748 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3749 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3750 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3751 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3752 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3753 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3754 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3755 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3799 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3809 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3810 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3811 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3812 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3813 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3814 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3815 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 3816 }; 3817 3818 intc: interrupt-controller@17100000 { 3819 compatible = "arm,gic-v3"; 3820 reg = <0 0x17100000 0 0x10000>, /* GICD */ 3821 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 3822 ranges; 3823 #interrupt-cells = <3>; 3824 interrupt-controller; 3825 #redistributor-regions = <1>; 3826 redistributor-stride = <0 0x40000>; 3827 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3828 #address-cells = <2>; 3829 #size-cells = <2>; 3830 3831 gic_its: msi-controller@17140000 { 3832 compatible = "arm,gic-v3-its"; 3833 reg = <0 0x17140000 0 0x20000>; 3834 msi-controller; 3835 #msi-cells = <1>; 3836 }; 3837 }; 3838 3839 timer@17420000 { 3840 compatible = "arm,armv7-timer-mem"; 3841 reg = <0 0x17420000 0 0x1000>; 3842 ranges = <0 0 0 0x20000000>; 3843 #address-cells = <1>; 3844 #size-cells = <1>; 3845 3846 frame@17421000 { 3847 reg = <0x17421000 0x1000>, 3848 <0x17422000 0x1000>; 3849 frame-number = <0>; 3850 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3852 }; 3853 3854 frame@17423000 { 3855 reg = <0x17423000 0x1000>; 3856 frame-number = <1>; 3857 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3858 status = "disabled"; 3859 }; 3860 3861 frame@17425000 { 3862 reg = <0x17425000 0x1000>; 3863 frame-number = <2>; 3864 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3865 status = "disabled"; 3866 }; 3867 3868 frame@17427000 { 3869 reg = <0x17427000 0x1000>; 3870 frame-number = <3>; 3871 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3872 status = "disabled"; 3873 }; 3874 3875 frame@17429000 { 3876 reg = <0x17429000 0x1000>; 3877 frame-number = <4>; 3878 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3879 status = "disabled"; 3880 }; 3881 3882 frame@1742b000 { 3883 reg = <0x1742b000 0x1000>; 3884 frame-number = <5>; 3885 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3886 status = "disabled"; 3887 }; 3888 3889 frame@1742d000 { 3890 reg = <0x1742d000 0x1000>; 3891 frame-number = <6>; 3892 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3893 status = "disabled"; 3894 }; 3895 }; 3896 3897 apps_rsc: rsc@17a00000 { 3898 label = "apps_rsc"; 3899 compatible = "qcom,rpmh-rsc"; 3900 reg = <0 0x17a00000 0 0x10000>, 3901 <0 0x17a10000 0 0x10000>, 3902 <0 0x17a20000 0 0x10000>, 3903 <0 0x17a30000 0 0x10000>; 3904 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3905 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3906 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3907 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3908 qcom,tcs-offset = <0xd00>; 3909 qcom,drv-id = <2>; 3910 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3911 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3912 power-domains = <&CLUSTER_PD>; 3913 3914 apps_bcm_voter: bcm-voter { 3915 compatible = "qcom,bcm-voter"; 3916 }; 3917 3918 rpmhcc: clock-controller { 3919 compatible = "qcom,sm8550-rpmh-clk"; 3920 #clock-cells = <1>; 3921 clock-names = "xo"; 3922 clocks = <&xo_board>; 3923 }; 3924 3925 rpmhpd: power-controller { 3926 compatible = "qcom,sm8550-rpmhpd"; 3927 #power-domain-cells = <1>; 3928 operating-points-v2 = <&rpmhpd_opp_table>; 3929 3930 rpmhpd_opp_table: opp-table { 3931 compatible = "operating-points-v2"; 3932 3933 rpmhpd_opp_ret: opp-16 { 3934 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3935 }; 3936 3937 rpmhpd_opp_min_svs: opp-48 { 3938 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3939 }; 3940 3941 rpmhpd_opp_low_svs_d2: opp-52 { 3942 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 3943 }; 3944 3945 rpmhpd_opp_low_svs_d1: opp-56 { 3946 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3947 }; 3948 3949 rpmhpd_opp_low_svs_d0: opp-60 { 3950 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 3951 }; 3952 3953 rpmhpd_opp_low_svs: opp-64 { 3954 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3955 }; 3956 3957 rpmhpd_opp_low_svs_l1: opp-80 { 3958 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 3959 }; 3960 3961 rpmhpd_opp_svs: opp-128 { 3962 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3963 }; 3964 3965 rpmhpd_opp_svs_l0: opp-144 { 3966 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 3967 }; 3968 3969 rpmhpd_opp_svs_l1: opp-192 { 3970 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3971 }; 3972 3973 rpmhpd_opp_nom: opp-256 { 3974 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3975 }; 3976 3977 rpmhpd_opp_nom_l1: opp-320 { 3978 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3979 }; 3980 3981 rpmhpd_opp_nom_l2: opp-336 { 3982 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3983 }; 3984 3985 rpmhpd_opp_turbo: opp-384 { 3986 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3987 }; 3988 3989 rpmhpd_opp_turbo_l1: opp-416 { 3990 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3991 }; 3992 }; 3993 }; 3994 }; 3995 3996 cpufreq_hw: cpufreq@17d91000 { 3997 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 3998 reg = <0 0x17d91000 0 0x1000>, 3999 <0 0x17d92000 0 0x1000>, 4000 <0 0x17d93000 0 0x1000>; 4001 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4002 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 4003 clock-names = "xo", "alternate"; 4004 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4005 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4006 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4007 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4008 #freq-domain-cells = <1>; 4009 #clock-cells = <1>; 4010 }; 4011 4012 pmu@24091000 { 4013 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4014 reg = <0 0x24091000 0 0x1000>; 4015 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4016 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 4017 4018 operating-points-v2 = <&llcc_bwmon_opp_table>; 4019 4020 llcc_bwmon_opp_table: opp-table { 4021 compatible = "operating-points-v2"; 4022 4023 opp-0 { 4024 opp-peak-kBps = <2086000>; 4025 }; 4026 4027 opp-1 { 4028 opp-peak-kBps = <2929000>; 4029 }; 4030 4031 opp-2 { 4032 opp-peak-kBps = <5931000>; 4033 }; 4034 4035 opp-3 { 4036 opp-peak-kBps = <6515000>; 4037 }; 4038 4039 opp-4 { 4040 opp-peak-kBps = <7980000>; 4041 }; 4042 4043 opp-5 { 4044 opp-peak-kBps = <10437000>; 4045 }; 4046 4047 opp-6 { 4048 opp-peak-kBps = <12157000>; 4049 }; 4050 4051 opp-7 { 4052 opp-peak-kBps = <14060000>; 4053 }; 4054 4055 opp-8 { 4056 opp-peak-kBps = <16113000>; 4057 }; 4058 }; 4059 }; 4060 4061 pmu@240b6400 { 4062 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 4063 reg = <0 0x240b6400 0 0x600>; 4064 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4065 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 4066 4067 operating-points-v2 = <&cpu_bwmon_opp_table>; 4068 4069 cpu_bwmon_opp_table: opp-table { 4070 compatible = "operating-points-v2"; 4071 4072 opp-0 { 4073 opp-peak-kBps = <4577000>; 4074 }; 4075 4076 opp-1 { 4077 opp-peak-kBps = <7110000>; 4078 }; 4079 4080 opp-2 { 4081 opp-peak-kBps = <9155000>; 4082 }; 4083 4084 opp-3 { 4085 opp-peak-kBps = <12298000>; 4086 }; 4087 4088 opp-4 { 4089 opp-peak-kBps = <14236000>; 4090 }; 4091 4092 opp-5 { 4093 opp-peak-kBps = <16265000>; 4094 }; 4095 }; 4096 }; 4097 4098 gem_noc: interconnect@24100000 { 4099 compatible = "qcom,sm8550-gem-noc"; 4100 reg = <0 0x24100000 0 0xbb800>; 4101 #interconnect-cells = <2>; 4102 qcom,bcm-voters = <&apps_bcm_voter>; 4103 }; 4104 4105 system-cache-controller@25000000 { 4106 compatible = "qcom,sm8550-llcc"; 4107 reg = <0 0x25000000 0 0x200000>, 4108 <0 0x25200000 0 0x200000>, 4109 <0 0x25400000 0 0x200000>, 4110 <0 0x25600000 0 0x200000>, 4111 <0 0x25800000 0 0x200000>; 4112 reg-names = "llcc0_base", 4113 "llcc1_base", 4114 "llcc2_base", 4115 "llcc3_base", 4116 "llcc_broadcast_base"; 4117 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4118 }; 4119 4120 nsp_noc: interconnect@320c0000 { 4121 compatible = "qcom,sm8550-nsp-noc"; 4122 reg = <0 0x320c0000 0 0xe080>; 4123 #interconnect-cells = <2>; 4124 qcom,bcm-voters = <&apps_bcm_voter>; 4125 }; 4126 4127 remoteproc_cdsp: remoteproc@32300000 { 4128 compatible = "qcom,sm8550-cdsp-pas"; 4129 reg = <0x0 0x32300000 0x0 0x10000>; 4130 4131 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4132 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 4133 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 4134 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 4135 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 4136 interrupt-names = "wdog", "fatal", "ready", 4137 "handover", "stop-ack"; 4138 4139 clocks = <&rpmhcc RPMH_CXO_CLK>; 4140 clock-names = "xo"; 4141 4142 power-domains = <&rpmhpd RPMHPD_CX>, 4143 <&rpmhpd RPMHPD_MXC>, 4144 <&rpmhpd RPMHPD_NSP>; 4145 power-domain-names = "cx", "mxc", "nsp"; 4146 4147 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4148 4149 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 4150 4151 qcom,qmp = <&aoss_qmp>; 4152 4153 qcom,smem-states = <&smp2p_cdsp_out 0>; 4154 qcom,smem-state-names = "stop"; 4155 4156 status = "disabled"; 4157 4158 glink-edge { 4159 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4160 IPCC_MPROC_SIGNAL_GLINK_QMP 4161 IRQ_TYPE_EDGE_RISING>; 4162 mboxes = <&ipcc IPCC_CLIENT_CDSP 4163 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4164 4165 label = "cdsp"; 4166 qcom,remote-pid = <5>; 4167 4168 fastrpc { 4169 compatible = "qcom,fastrpc"; 4170 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4171 label = "cdsp"; 4172 qcom,non-secure-domain; 4173 #address-cells = <1>; 4174 #size-cells = <0>; 4175 4176 compute-cb@1 { 4177 compatible = "qcom,fastrpc-compute-cb"; 4178 reg = <1>; 4179 iommus = <&apps_smmu 0x1961 0x0>, 4180 <&apps_smmu 0x0c01 0x20>, 4181 <&apps_smmu 0x19c1 0x10>; 4182 dma-coherent; 4183 }; 4184 4185 compute-cb@2 { 4186 compatible = "qcom,fastrpc-compute-cb"; 4187 reg = <2>; 4188 iommus = <&apps_smmu 0x1962 0x0>, 4189 <&apps_smmu 0x0c02 0x20>, 4190 <&apps_smmu 0x19c2 0x10>; 4191 dma-coherent; 4192 }; 4193 4194 compute-cb@3 { 4195 compatible = "qcom,fastrpc-compute-cb"; 4196 reg = <3>; 4197 iommus = <&apps_smmu 0x1963 0x0>, 4198 <&apps_smmu 0x0c03 0x20>, 4199 <&apps_smmu 0x19c3 0x10>; 4200 dma-coherent; 4201 }; 4202 4203 compute-cb@4 { 4204 compatible = "qcom,fastrpc-compute-cb"; 4205 reg = <4>; 4206 iommus = <&apps_smmu 0x1964 0x0>, 4207 <&apps_smmu 0x0c04 0x20>, 4208 <&apps_smmu 0x19c4 0x10>; 4209 dma-coherent; 4210 }; 4211 4212 compute-cb@5 { 4213 compatible = "qcom,fastrpc-compute-cb"; 4214 reg = <5>; 4215 iommus = <&apps_smmu 0x1965 0x0>, 4216 <&apps_smmu 0x0c05 0x20>, 4217 <&apps_smmu 0x19c5 0x10>; 4218 dma-coherent; 4219 }; 4220 4221 compute-cb@6 { 4222 compatible = "qcom,fastrpc-compute-cb"; 4223 reg = <6>; 4224 iommus = <&apps_smmu 0x1966 0x0>, 4225 <&apps_smmu 0x0c06 0x20>, 4226 <&apps_smmu 0x19c6 0x10>; 4227 dma-coherent; 4228 }; 4229 4230 compute-cb@7 { 4231 compatible = "qcom,fastrpc-compute-cb"; 4232 reg = <7>; 4233 iommus = <&apps_smmu 0x1967 0x0>, 4234 <&apps_smmu 0x0c07 0x20>, 4235 <&apps_smmu 0x19c7 0x10>; 4236 dma-coherent; 4237 }; 4238 4239 compute-cb@8 { 4240 compatible = "qcom,fastrpc-compute-cb"; 4241 reg = <8>; 4242 iommus = <&apps_smmu 0x1968 0x0>, 4243 <&apps_smmu 0x0c08 0x20>, 4244 <&apps_smmu 0x19c8 0x10>; 4245 dma-coherent; 4246 }; 4247 4248 /* note: secure cb9 in downstream */ 4249 }; 4250 }; 4251 }; 4252 }; 4253 4254 thermal-zones { 4255 aoss0-thermal { 4256 polling-delay-passive = <0>; 4257 polling-delay = <0>; 4258 thermal-sensors = <&tsens0 0>; 4259 4260 trips { 4261 thermal-engine-config { 4262 temperature = <125000>; 4263 hysteresis = <1000>; 4264 type = "passive"; 4265 }; 4266 4267 reset-mon-config { 4268 temperature = <115000>; 4269 hysteresis = <5000>; 4270 type = "passive"; 4271 }; 4272 }; 4273 }; 4274 4275 cpuss0-thermal { 4276 polling-delay-passive = <0>; 4277 polling-delay = <0>; 4278 thermal-sensors = <&tsens0 1>; 4279 4280 trips { 4281 thermal-engine-config { 4282 temperature = <125000>; 4283 hysteresis = <1000>; 4284 type = "passive"; 4285 }; 4286 4287 reset-mon-config { 4288 temperature = <115000>; 4289 hysteresis = <5000>; 4290 type = "passive"; 4291 }; 4292 }; 4293 }; 4294 4295 cpuss1-thermal { 4296 polling-delay-passive = <0>; 4297 polling-delay = <0>; 4298 thermal-sensors = <&tsens0 2>; 4299 4300 trips { 4301 thermal-engine-config { 4302 temperature = <125000>; 4303 hysteresis = <1000>; 4304 type = "passive"; 4305 }; 4306 4307 reset-mon-config { 4308 temperature = <115000>; 4309 hysteresis = <5000>; 4310 type = "passive"; 4311 }; 4312 }; 4313 }; 4314 4315 cpuss2-thermal { 4316 polling-delay-passive = <0>; 4317 polling-delay = <0>; 4318 thermal-sensors = <&tsens0 3>; 4319 4320 trips { 4321 thermal-engine-config { 4322 temperature = <125000>; 4323 hysteresis = <1000>; 4324 type = "passive"; 4325 }; 4326 4327 reset-mon-config { 4328 temperature = <115000>; 4329 hysteresis = <5000>; 4330 type = "passive"; 4331 }; 4332 }; 4333 }; 4334 4335 cpuss3-thermal { 4336 polling-delay-passive = <0>; 4337 polling-delay = <0>; 4338 thermal-sensors = <&tsens0 4>; 4339 4340 trips { 4341 thermal-engine-config { 4342 temperature = <125000>; 4343 hysteresis = <1000>; 4344 type = "passive"; 4345 }; 4346 4347 reset-mon-config { 4348 temperature = <115000>; 4349 hysteresis = <5000>; 4350 type = "passive"; 4351 }; 4352 }; 4353 }; 4354 4355 cpu3-top-thermal { 4356 polling-delay-passive = <0>; 4357 polling-delay = <0>; 4358 thermal-sensors = <&tsens0 5>; 4359 4360 trips { 4361 cpu3_top_alert0: trip-point0 { 4362 temperature = <90000>; 4363 hysteresis = <2000>; 4364 type = "passive"; 4365 }; 4366 4367 cpu3_top_alert1: trip-point1 { 4368 temperature = <95000>; 4369 hysteresis = <2000>; 4370 type = "passive"; 4371 }; 4372 4373 cpu3_top_crit: cpu-critical { 4374 temperature = <110000>; 4375 hysteresis = <1000>; 4376 type = "critical"; 4377 }; 4378 }; 4379 }; 4380 4381 cpu3-bottom-thermal { 4382 polling-delay-passive = <0>; 4383 polling-delay = <0>; 4384 thermal-sensors = <&tsens0 6>; 4385 4386 trips { 4387 cpu3_bottom_alert0: trip-point0 { 4388 temperature = <90000>; 4389 hysteresis = <2000>; 4390 type = "passive"; 4391 }; 4392 4393 cpu3_bottom_alert1: trip-point1 { 4394 temperature = <95000>; 4395 hysteresis = <2000>; 4396 type = "passive"; 4397 }; 4398 4399 cpu3_bottom_crit: cpu-critical { 4400 temperature = <110000>; 4401 hysteresis = <1000>; 4402 type = "critical"; 4403 }; 4404 }; 4405 }; 4406 4407 cpu4-top-thermal { 4408 polling-delay-passive = <0>; 4409 polling-delay = <0>; 4410 thermal-sensors = <&tsens0 7>; 4411 4412 trips { 4413 cpu4_top_alert0: trip-point0 { 4414 temperature = <90000>; 4415 hysteresis = <2000>; 4416 type = "passive"; 4417 }; 4418 4419 cpu4_top_alert1: trip-point1 { 4420 temperature = <95000>; 4421 hysteresis = <2000>; 4422 type = "passive"; 4423 }; 4424 4425 cpu4_top_crit: cpu-critical { 4426 temperature = <110000>; 4427 hysteresis = <1000>; 4428 type = "critical"; 4429 }; 4430 }; 4431 }; 4432 4433 cpu4-bottom-thermal { 4434 polling-delay-passive = <0>; 4435 polling-delay = <0>; 4436 thermal-sensors = <&tsens0 8>; 4437 4438 trips { 4439 cpu4_bottom_alert0: trip-point0 { 4440 temperature = <90000>; 4441 hysteresis = <2000>; 4442 type = "passive"; 4443 }; 4444 4445 cpu4_bottom_alert1: trip-point1 { 4446 temperature = <95000>; 4447 hysteresis = <2000>; 4448 type = "passive"; 4449 }; 4450 4451 cpu4_bottom_crit: cpu-critical { 4452 temperature = <110000>; 4453 hysteresis = <1000>; 4454 type = "critical"; 4455 }; 4456 }; 4457 }; 4458 4459 cpu5-top-thermal { 4460 polling-delay-passive = <0>; 4461 polling-delay = <0>; 4462 thermal-sensors = <&tsens0 9>; 4463 4464 trips { 4465 cpu5_top_alert0: trip-point0 { 4466 temperature = <90000>; 4467 hysteresis = <2000>; 4468 type = "passive"; 4469 }; 4470 4471 cpu5_top_alert1: trip-point1 { 4472 temperature = <95000>; 4473 hysteresis = <2000>; 4474 type = "passive"; 4475 }; 4476 4477 cpu5_top_crit: cpu-critical { 4478 temperature = <110000>; 4479 hysteresis = <1000>; 4480 type = "critical"; 4481 }; 4482 }; 4483 }; 4484 4485 cpu5-bottom-thermal { 4486 polling-delay-passive = <0>; 4487 polling-delay = <0>; 4488 thermal-sensors = <&tsens0 10>; 4489 4490 trips { 4491 cpu5_bottom_alert0: trip-point0 { 4492 temperature = <90000>; 4493 hysteresis = <2000>; 4494 type = "passive"; 4495 }; 4496 4497 cpu5_bottom_alert1: trip-point1 { 4498 temperature = <95000>; 4499 hysteresis = <2000>; 4500 type = "passive"; 4501 }; 4502 4503 cpu5_bottom_crit: cpu-critical { 4504 temperature = <110000>; 4505 hysteresis = <1000>; 4506 type = "critical"; 4507 }; 4508 }; 4509 }; 4510 4511 cpu6-top-thermal { 4512 polling-delay-passive = <0>; 4513 polling-delay = <0>; 4514 thermal-sensors = <&tsens0 11>; 4515 4516 trips { 4517 cpu6_top_alert0: trip-point0 { 4518 temperature = <90000>; 4519 hysteresis = <2000>; 4520 type = "passive"; 4521 }; 4522 4523 cpu6_top_alert1: trip-point1 { 4524 temperature = <95000>; 4525 hysteresis = <2000>; 4526 type = "passive"; 4527 }; 4528 4529 cpu6_top_crit: cpu-critical { 4530 temperature = <110000>; 4531 hysteresis = <1000>; 4532 type = "critical"; 4533 }; 4534 }; 4535 }; 4536 4537 cpu6-bottom-thermal { 4538 polling-delay-passive = <0>; 4539 polling-delay = <0>; 4540 thermal-sensors = <&tsens0 12>; 4541 4542 trips { 4543 cpu6_bottom_alert0: trip-point0 { 4544 temperature = <90000>; 4545 hysteresis = <2000>; 4546 type = "passive"; 4547 }; 4548 4549 cpu6_bottom_alert1: trip-point1 { 4550 temperature = <95000>; 4551 hysteresis = <2000>; 4552 type = "passive"; 4553 }; 4554 4555 cpu6_bottom_crit: cpu-critical { 4556 temperature = <110000>; 4557 hysteresis = <1000>; 4558 type = "critical"; 4559 }; 4560 }; 4561 }; 4562 4563 cpu7-top-thermal { 4564 polling-delay-passive = <0>; 4565 polling-delay = <0>; 4566 thermal-sensors = <&tsens0 13>; 4567 4568 trips { 4569 cpu7_top_alert0: trip-point0 { 4570 temperature = <90000>; 4571 hysteresis = <2000>; 4572 type = "passive"; 4573 }; 4574 4575 cpu7_top_alert1: trip-point1 { 4576 temperature = <95000>; 4577 hysteresis = <2000>; 4578 type = "passive"; 4579 }; 4580 4581 cpu7_top_crit: cpu-critical { 4582 temperature = <110000>; 4583 hysteresis = <1000>; 4584 type = "critical"; 4585 }; 4586 }; 4587 }; 4588 4589 cpu7-middle-thermal { 4590 polling-delay-passive = <0>; 4591 polling-delay = <0>; 4592 thermal-sensors = <&tsens0 14>; 4593 4594 trips { 4595 cpu7_middle_alert0: trip-point0 { 4596 temperature = <90000>; 4597 hysteresis = <2000>; 4598 type = "passive"; 4599 }; 4600 4601 cpu7_middle_alert1: trip-point1 { 4602 temperature = <95000>; 4603 hysteresis = <2000>; 4604 type = "passive"; 4605 }; 4606 4607 cpu7_middle_crit: cpu-critical { 4608 temperature = <110000>; 4609 hysteresis = <1000>; 4610 type = "critical"; 4611 }; 4612 }; 4613 }; 4614 4615 cpu7-bottom-thermal { 4616 polling-delay-passive = <0>; 4617 polling-delay = <0>; 4618 thermal-sensors = <&tsens0 15>; 4619 4620 trips { 4621 cpu7_bottom_alert0: trip-point0 { 4622 temperature = <90000>; 4623 hysteresis = <2000>; 4624 type = "passive"; 4625 }; 4626 4627 cpu7_bottom_alert1: trip-point1 { 4628 temperature = <95000>; 4629 hysteresis = <2000>; 4630 type = "passive"; 4631 }; 4632 4633 cpu7_bottom_crit: cpu-critical { 4634 temperature = <110000>; 4635 hysteresis = <1000>; 4636 type = "critical"; 4637 }; 4638 }; 4639 }; 4640 4641 aoss1-thermal { 4642 polling-delay-passive = <0>; 4643 polling-delay = <0>; 4644 thermal-sensors = <&tsens1 0>; 4645 4646 trips { 4647 thermal-engine-config { 4648 temperature = <125000>; 4649 hysteresis = <1000>; 4650 type = "passive"; 4651 }; 4652 4653 reset-mon-config { 4654 temperature = <115000>; 4655 hysteresis = <5000>; 4656 type = "passive"; 4657 }; 4658 }; 4659 }; 4660 4661 cpu0-thermal { 4662 polling-delay-passive = <0>; 4663 polling-delay = <0>; 4664 thermal-sensors = <&tsens1 1>; 4665 4666 trips { 4667 cpu0_alert0: trip-point0 { 4668 temperature = <90000>; 4669 hysteresis = <2000>; 4670 type = "passive"; 4671 }; 4672 4673 cpu0_alert1: trip-point1 { 4674 temperature = <95000>; 4675 hysteresis = <2000>; 4676 type = "passive"; 4677 }; 4678 4679 cpu0_crit: cpu-critical { 4680 temperature = <110000>; 4681 hysteresis = <1000>; 4682 type = "critical"; 4683 }; 4684 }; 4685 }; 4686 4687 cpu1-thermal { 4688 polling-delay-passive = <0>; 4689 polling-delay = <0>; 4690 thermal-sensors = <&tsens1 2>; 4691 4692 trips { 4693 cpu1_alert0: trip-point0 { 4694 temperature = <90000>; 4695 hysteresis = <2000>; 4696 type = "passive"; 4697 }; 4698 4699 cpu1_alert1: trip-point1 { 4700 temperature = <95000>; 4701 hysteresis = <2000>; 4702 type = "passive"; 4703 }; 4704 4705 cpu1_crit: cpu-critical { 4706 temperature = <110000>; 4707 hysteresis = <1000>; 4708 type = "critical"; 4709 }; 4710 }; 4711 }; 4712 4713 cpu2-thermal { 4714 polling-delay-passive = <0>; 4715 polling-delay = <0>; 4716 thermal-sensors = <&tsens1 3>; 4717 4718 trips { 4719 cpu2_alert0: trip-point0 { 4720 temperature = <90000>; 4721 hysteresis = <2000>; 4722 type = "passive"; 4723 }; 4724 4725 cpu2_alert1: trip-point1 { 4726 temperature = <95000>; 4727 hysteresis = <2000>; 4728 type = "passive"; 4729 }; 4730 4731 cpu2_crit: cpu-critical { 4732 temperature = <110000>; 4733 hysteresis = <1000>; 4734 type = "critical"; 4735 }; 4736 }; 4737 }; 4738 4739 cdsp0-thermal { 4740 polling-delay-passive = <10>; 4741 polling-delay = <0>; 4742 thermal-sensors = <&tsens2 4>; 4743 4744 trips { 4745 thermal-engine-config { 4746 temperature = <125000>; 4747 hysteresis = <1000>; 4748 type = "passive"; 4749 }; 4750 4751 thermal-hal-config { 4752 temperature = <125000>; 4753 hysteresis = <1000>; 4754 type = "passive"; 4755 }; 4756 4757 reset-mon-config { 4758 temperature = <115000>; 4759 hysteresis = <5000>; 4760 type = "passive"; 4761 }; 4762 4763 cdsp0_junction_config: junction-config { 4764 temperature = <95000>; 4765 hysteresis = <5000>; 4766 type = "passive"; 4767 }; 4768 }; 4769 }; 4770 4771 cdsp1-thermal { 4772 polling-delay-passive = <10>; 4773 polling-delay = <0>; 4774 thermal-sensors = <&tsens2 5>; 4775 4776 trips { 4777 thermal-engine-config { 4778 temperature = <125000>; 4779 hysteresis = <1000>; 4780 type = "passive"; 4781 }; 4782 4783 thermal-hal-config { 4784 temperature = <125000>; 4785 hysteresis = <1000>; 4786 type = "passive"; 4787 }; 4788 4789 reset-mon-config { 4790 temperature = <115000>; 4791 hysteresis = <5000>; 4792 type = "passive"; 4793 }; 4794 4795 cdsp1_junction_config: junction-config { 4796 temperature = <95000>; 4797 hysteresis = <5000>; 4798 type = "passive"; 4799 }; 4800 }; 4801 }; 4802 4803 cdsp2-thermal { 4804 polling-delay-passive = <10>; 4805 polling-delay = <0>; 4806 thermal-sensors = <&tsens2 6>; 4807 4808 trips { 4809 thermal-engine-config { 4810 temperature = <125000>; 4811 hysteresis = <1000>; 4812 type = "passive"; 4813 }; 4814 4815 thermal-hal-config { 4816 temperature = <125000>; 4817 hysteresis = <1000>; 4818 type = "passive"; 4819 }; 4820 4821 reset-mon-config { 4822 temperature = <115000>; 4823 hysteresis = <5000>; 4824 type = "passive"; 4825 }; 4826 4827 cdsp2_junction_config: junction-config { 4828 temperature = <95000>; 4829 hysteresis = <5000>; 4830 type = "passive"; 4831 }; 4832 }; 4833 }; 4834 4835 cdsp3-thermal { 4836 polling-delay-passive = <10>; 4837 polling-delay = <0>; 4838 thermal-sensors = <&tsens2 7>; 4839 4840 trips { 4841 thermal-engine-config { 4842 temperature = <125000>; 4843 hysteresis = <1000>; 4844 type = "passive"; 4845 }; 4846 4847 thermal-hal-config { 4848 temperature = <125000>; 4849 hysteresis = <1000>; 4850 type = "passive"; 4851 }; 4852 4853 reset-mon-config { 4854 temperature = <115000>; 4855 hysteresis = <5000>; 4856 type = "passive"; 4857 }; 4858 4859 cdsp3_junction_config: junction-config { 4860 temperature = <95000>; 4861 hysteresis = <5000>; 4862 type = "passive"; 4863 }; 4864 }; 4865 }; 4866 4867 video-thermal { 4868 polling-delay-passive = <0>; 4869 polling-delay = <0>; 4870 thermal-sensors = <&tsens1 8>; 4871 4872 trips { 4873 thermal-engine-config { 4874 temperature = <125000>; 4875 hysteresis = <1000>; 4876 type = "passive"; 4877 }; 4878 4879 reset-mon-config { 4880 temperature = <115000>; 4881 hysteresis = <5000>; 4882 type = "passive"; 4883 }; 4884 }; 4885 }; 4886 4887 mem-thermal { 4888 polling-delay-passive = <10>; 4889 polling-delay = <0>; 4890 thermal-sensors = <&tsens1 9>; 4891 4892 trips { 4893 thermal-engine-config { 4894 temperature = <125000>; 4895 hysteresis = <1000>; 4896 type = "passive"; 4897 }; 4898 4899 ddr_config0: ddr0-config { 4900 temperature = <90000>; 4901 hysteresis = <5000>; 4902 type = "passive"; 4903 }; 4904 4905 reset-mon-config { 4906 temperature = <115000>; 4907 hysteresis = <5000>; 4908 type = "passive"; 4909 }; 4910 }; 4911 }; 4912 4913 modem0-thermal { 4914 polling-delay-passive = <0>; 4915 polling-delay = <0>; 4916 thermal-sensors = <&tsens1 10>; 4917 4918 trips { 4919 thermal-engine-config { 4920 temperature = <125000>; 4921 hysteresis = <1000>; 4922 type = "passive"; 4923 }; 4924 4925 mdmss0_config0: mdmss0-config0 { 4926 temperature = <102000>; 4927 hysteresis = <3000>; 4928 type = "passive"; 4929 }; 4930 4931 mdmss0_config1: mdmss0-config1 { 4932 temperature = <105000>; 4933 hysteresis = <3000>; 4934 type = "passive"; 4935 }; 4936 4937 reset-mon-config { 4938 temperature = <115000>; 4939 hysteresis = <5000>; 4940 type = "passive"; 4941 }; 4942 }; 4943 }; 4944 4945 modem1-thermal { 4946 polling-delay-passive = <0>; 4947 polling-delay = <0>; 4948 thermal-sensors = <&tsens1 11>; 4949 4950 trips { 4951 thermal-engine-config { 4952 temperature = <125000>; 4953 hysteresis = <1000>; 4954 type = "passive"; 4955 }; 4956 4957 mdmss1_config0: mdmss1-config0 { 4958 temperature = <102000>; 4959 hysteresis = <3000>; 4960 type = "passive"; 4961 }; 4962 4963 mdmss1_config1: mdmss1-config1 { 4964 temperature = <105000>; 4965 hysteresis = <3000>; 4966 type = "passive"; 4967 }; 4968 4969 reset-mon-config { 4970 temperature = <115000>; 4971 hysteresis = <5000>; 4972 type = "passive"; 4973 }; 4974 }; 4975 }; 4976 4977 modem2-thermal { 4978 polling-delay-passive = <0>; 4979 polling-delay = <0>; 4980 thermal-sensors = <&tsens1 12>; 4981 4982 trips { 4983 thermal-engine-config { 4984 temperature = <125000>; 4985 hysteresis = <1000>; 4986 type = "passive"; 4987 }; 4988 4989 mdmss2_config0: mdmss2-config0 { 4990 temperature = <102000>; 4991 hysteresis = <3000>; 4992 type = "passive"; 4993 }; 4994 4995 mdmss2_config1: mdmss2-config1 { 4996 temperature = <105000>; 4997 hysteresis = <3000>; 4998 type = "passive"; 4999 }; 5000 5001 reset-mon-config { 5002 temperature = <115000>; 5003 hysteresis = <5000>; 5004 type = "passive"; 5005 }; 5006 }; 5007 }; 5008 5009 modem3-thermal { 5010 polling-delay-passive = <0>; 5011 polling-delay = <0>; 5012 thermal-sensors = <&tsens1 13>; 5013 5014 trips { 5015 thermal-engine-config { 5016 temperature = <125000>; 5017 hysteresis = <1000>; 5018 type = "passive"; 5019 }; 5020 5021 mdmss3_config0: mdmss3-config0 { 5022 temperature = <102000>; 5023 hysteresis = <3000>; 5024 type = "passive"; 5025 }; 5026 5027 mdmss3_config1: mdmss3-config1 { 5028 temperature = <105000>; 5029 hysteresis = <3000>; 5030 type = "passive"; 5031 }; 5032 5033 reset-mon-config { 5034 temperature = <115000>; 5035 hysteresis = <5000>; 5036 type = "passive"; 5037 }; 5038 }; 5039 }; 5040 5041 camera0-thermal { 5042 polling-delay-passive = <0>; 5043 polling-delay = <0>; 5044 thermal-sensors = <&tsens1 14>; 5045 5046 trips { 5047 thermal-engine-config { 5048 temperature = <125000>; 5049 hysteresis = <1000>; 5050 type = "passive"; 5051 }; 5052 5053 reset-mon-config { 5054 temperature = <115000>; 5055 hysteresis = <5000>; 5056 type = "passive"; 5057 }; 5058 }; 5059 }; 5060 5061 camera1-thermal { 5062 polling-delay-passive = <0>; 5063 polling-delay = <0>; 5064 thermal-sensors = <&tsens1 15>; 5065 5066 trips { 5067 thermal-engine-config { 5068 temperature = <125000>; 5069 hysteresis = <1000>; 5070 type = "passive"; 5071 }; 5072 5073 reset-mon-config { 5074 temperature = <115000>; 5075 hysteresis = <5000>; 5076 type = "passive"; 5077 }; 5078 }; 5079 }; 5080 5081 aoss2-thermal { 5082 polling-delay-passive = <0>; 5083 polling-delay = <0>; 5084 thermal-sensors = <&tsens2 0>; 5085 5086 trips { 5087 thermal-engine-config { 5088 temperature = <125000>; 5089 hysteresis = <1000>; 5090 type = "passive"; 5091 }; 5092 5093 reset-mon-config { 5094 temperature = <115000>; 5095 hysteresis = <5000>; 5096 type = "passive"; 5097 }; 5098 }; 5099 }; 5100 5101 gpuss-0-thermal { 5102 polling-delay-passive = <10>; 5103 polling-delay = <0>; 5104 thermal-sensors = <&tsens2 1>; 5105 5106 trips { 5107 thermal-engine-config { 5108 temperature = <125000>; 5109 hysteresis = <1000>; 5110 type = "passive"; 5111 }; 5112 5113 thermal-hal-config { 5114 temperature = <125000>; 5115 hysteresis = <1000>; 5116 type = "passive"; 5117 }; 5118 5119 reset-mon-config { 5120 temperature = <115000>; 5121 hysteresis = <5000>; 5122 type = "passive"; 5123 }; 5124 5125 gpu0_junction_config: junction-config { 5126 temperature = <95000>; 5127 hysteresis = <5000>; 5128 type = "passive"; 5129 }; 5130 }; 5131 }; 5132 5133 gpuss-1-thermal { 5134 polling-delay-passive = <10>; 5135 polling-delay = <0>; 5136 thermal-sensors = <&tsens2 2>; 5137 5138 trips { 5139 thermal-engine-config { 5140 temperature = <125000>; 5141 hysteresis = <1000>; 5142 type = "passive"; 5143 }; 5144 5145 thermal-hal-config { 5146 temperature = <125000>; 5147 hysteresis = <1000>; 5148 type = "passive"; 5149 }; 5150 5151 reset-mon-config { 5152 temperature = <115000>; 5153 hysteresis = <5000>; 5154 type = "passive"; 5155 }; 5156 5157 gpu1_junction_config: junction-config { 5158 temperature = <95000>; 5159 hysteresis = <5000>; 5160 type = "passive"; 5161 }; 5162 }; 5163 }; 5164 5165 gpuss-2-thermal { 5166 polling-delay-passive = <10>; 5167 polling-delay = <0>; 5168 thermal-sensors = <&tsens2 3>; 5169 5170 trips { 5171 thermal-engine-config { 5172 temperature = <125000>; 5173 hysteresis = <1000>; 5174 type = "passive"; 5175 }; 5176 5177 thermal-hal-config { 5178 temperature = <125000>; 5179 hysteresis = <1000>; 5180 type = "passive"; 5181 }; 5182 5183 reset-mon-config { 5184 temperature = <115000>; 5185 hysteresis = <5000>; 5186 type = "passive"; 5187 }; 5188 5189 gpu2_junction_config: junction-config { 5190 temperature = <95000>; 5191 hysteresis = <5000>; 5192 type = "passive"; 5193 }; 5194 }; 5195 }; 5196 5197 gpuss-3-thermal { 5198 polling-delay-passive = <10>; 5199 polling-delay = <0>; 5200 thermal-sensors = <&tsens2 4>; 5201 5202 trips { 5203 thermal-engine-config { 5204 temperature = <125000>; 5205 hysteresis = <1000>; 5206 type = "passive"; 5207 }; 5208 5209 thermal-hal-config { 5210 temperature = <125000>; 5211 hysteresis = <1000>; 5212 type = "passive"; 5213 }; 5214 5215 reset-mon-config { 5216 temperature = <115000>; 5217 hysteresis = <5000>; 5218 type = "passive"; 5219 }; 5220 5221 gpu3_junction_config: junction-config { 5222 temperature = <95000>; 5223 hysteresis = <5000>; 5224 type = "passive"; 5225 }; 5226 }; 5227 }; 5228 5229 gpuss-4-thermal { 5230 polling-delay-passive = <10>; 5231 polling-delay = <0>; 5232 thermal-sensors = <&tsens2 5>; 5233 5234 trips { 5235 thermal-engine-config { 5236 temperature = <125000>; 5237 hysteresis = <1000>; 5238 type = "passive"; 5239 }; 5240 5241 thermal-hal-config { 5242 temperature = <125000>; 5243 hysteresis = <1000>; 5244 type = "passive"; 5245 }; 5246 5247 reset-mon-config { 5248 temperature = <115000>; 5249 hysteresis = <5000>; 5250 type = "passive"; 5251 }; 5252 5253 gpu4_junction_config: junction-config { 5254 temperature = <95000>; 5255 hysteresis = <5000>; 5256 type = "passive"; 5257 }; 5258 }; 5259 }; 5260 5261 gpuss-5-thermal { 5262 polling-delay-passive = <10>; 5263 polling-delay = <0>; 5264 thermal-sensors = <&tsens2 6>; 5265 5266 trips { 5267 thermal-engine-config { 5268 temperature = <125000>; 5269 hysteresis = <1000>; 5270 type = "passive"; 5271 }; 5272 5273 thermal-hal-config { 5274 temperature = <125000>; 5275 hysteresis = <1000>; 5276 type = "passive"; 5277 }; 5278 5279 reset-mon-config { 5280 temperature = <115000>; 5281 hysteresis = <5000>; 5282 type = "passive"; 5283 }; 5284 5285 gpu5_junction_config: junction-config { 5286 temperature = <95000>; 5287 hysteresis = <5000>; 5288 type = "passive"; 5289 }; 5290 }; 5291 }; 5292 5293 gpuss-6-thermal { 5294 polling-delay-passive = <10>; 5295 polling-delay = <0>; 5296 thermal-sensors = <&tsens2 7>; 5297 5298 trips { 5299 thermal-engine-config { 5300 temperature = <125000>; 5301 hysteresis = <1000>; 5302 type = "passive"; 5303 }; 5304 5305 thermal-hal-config { 5306 temperature = <125000>; 5307 hysteresis = <1000>; 5308 type = "passive"; 5309 }; 5310 5311 reset-mon-config { 5312 temperature = <115000>; 5313 hysteresis = <5000>; 5314 type = "passive"; 5315 }; 5316 5317 gpu6_junction_config: junction-config { 5318 temperature = <95000>; 5319 hysteresis = <5000>; 5320 type = "passive"; 5321 }; 5322 }; 5323 }; 5324 5325 gpuss-7-thermal { 5326 polling-delay-passive = <10>; 5327 polling-delay = <0>; 5328 thermal-sensors = <&tsens2 8>; 5329 5330 trips { 5331 thermal-engine-config { 5332 temperature = <125000>; 5333 hysteresis = <1000>; 5334 type = "passive"; 5335 }; 5336 5337 thermal-hal-config { 5338 temperature = <125000>; 5339 hysteresis = <1000>; 5340 type = "passive"; 5341 }; 5342 5343 reset-mon-config { 5344 temperature = <115000>; 5345 hysteresis = <5000>; 5346 type = "passive"; 5347 }; 5348 5349 gpu7_junction_config: junction-config { 5350 temperature = <95000>; 5351 hysteresis = <5000>; 5352 type = "passive"; 5353 }; 5354 }; 5355 }; 5356 }; 5357 5358 timer { 5359 compatible = "arm,armv8-timer"; 5360 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5361 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5362 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5363 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5364 }; 5365}; 5366