1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7 8/ { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 cpu0: cpu@0 { 17 compatible = "arm,cortex-a35"; 18 device_type = "cpu"; 19 reg = <0>; 20 enable-method = "psci"; 21 }; 22 }; 23 24 arm-pmu { 25 compatible = "arm,cortex-a35-pmu"; 26 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 27 interrupt-affinity = <&cpu0>; 28 interrupt-parent = <&intc>; 29 }; 30 31 clocks { 32 ck_flexgen_08: ck-flexgen-08 { 33 #clock-cells = <0>; 34 compatible = "fixed-clock"; 35 clock-frequency = <100000000>; 36 }; 37 38 ck_flexgen_51: ck-flexgen-51 { 39 #clock-cells = <0>; 40 compatible = "fixed-clock"; 41 clock-frequency = <200000000>; 42 }; 43 44 ck_icn_ls_mcu: ck-icn-ls-mcu { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <200000000>; 48 }; 49 }; 50 51 firmware { 52 optee { 53 compatible = "linaro,optee-tz"; 54 method = "smc"; 55 }; 56 57 scmi { 58 compatible = "linaro,scmi-optee"; 59 #address-cells = <1>; 60 #size-cells = <0>; 61 linaro,optee-channel-id = <0>; 62 63 scmi_clk: protocol@14 { 64 reg = <0x14>; 65 #clock-cells = <1>; 66 }; 67 68 scmi_reset: protocol@16 { 69 reg = <0x16>; 70 #reset-cells = <1>; 71 }; 72 }; 73 }; 74 75 intc: interrupt-controller@4ac00000 { 76 compatible = "arm,gic-400"; 77 #interrupt-cells = <3>; 78 interrupt-controller; 79 reg = <0x0 0x4ac10000 0x0 0x1000>, 80 <0x0 0x4ac20000 0x0 0x20000>, 81 <0x0 0x4ac40000 0x0 0x20000>, 82 <0x0 0x4ac60000 0x0 0x20000>; 83 }; 84 85 psci { 86 compatible = "arm,psci-1.0"; 87 method = "smc"; 88 }; 89 90 timer { 91 compatible = "arm,armv8-timer"; 92 interrupt-parent = <&intc>; 93 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 94 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 95 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 96 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 97 always-on; 98 }; 99 100 soc@0 { 101 compatible = "simple-bus"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 interrupt-parent = <&intc>; 105 ranges = <0x0 0x0 0x0 0x80000000>; 106 107 rifsc: rifsc-bus@42080000 { 108 compatible = "simple-bus"; 109 reg = <0x42080000 0x1000>; 110 #address-cells = <1>; 111 #size-cells = <1>; 112 ranges; 113 114 usart2: serial@400e0000 { 115 compatible = "st,stm32h7-uart"; 116 reg = <0x400e0000 0x400>; 117 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 118 clocks = <&ck_flexgen_08>; 119 status = "disabled"; 120 }; 121 }; 122 123 syscfg: syscon@44230000 { 124 compatible = "st,stm32mp25-syscfg", "syscon"; 125 reg = <0x44230000 0x10000>; 126 }; 127 128 pinctrl: pinctrl@44240000 { 129 #address-cells = <1>; 130 #size-cells = <1>; 131 compatible = "st,stm32mp257-pinctrl"; 132 ranges = <0 0x44240000 0xa0400>; 133 pins-are-numbered; 134 135 gpioa: gpio@44240000 { 136 gpio-controller; 137 #gpio-cells = <2>; 138 interrupt-controller; 139 #interrupt-cells = <2>; 140 reg = <0x0 0x400>; 141 clocks = <&ck_icn_ls_mcu>; 142 st,bank-name = "GPIOA"; 143 status = "disabled"; 144 }; 145 146 gpiob: gpio@44250000 { 147 gpio-controller; 148 #gpio-cells = <2>; 149 interrupt-controller; 150 #interrupt-cells = <2>; 151 reg = <0x10000 0x400>; 152 clocks = <&ck_icn_ls_mcu>; 153 st,bank-name = "GPIOB"; 154 status = "disabled"; 155 }; 156 157 gpioc: gpio@44260000 { 158 gpio-controller; 159 #gpio-cells = <2>; 160 interrupt-controller; 161 #interrupt-cells = <2>; 162 reg = <0x20000 0x400>; 163 clocks = <&ck_icn_ls_mcu>; 164 st,bank-name = "GPIOC"; 165 status = "disabled"; 166 }; 167 168 gpiod: gpio@44270000 { 169 gpio-controller; 170 #gpio-cells = <2>; 171 interrupt-controller; 172 #interrupt-cells = <2>; 173 reg = <0x30000 0x400>; 174 clocks = <&ck_icn_ls_mcu>; 175 st,bank-name = "GPIOD"; 176 status = "disabled"; 177 }; 178 179 gpioe: gpio@44280000 { 180 gpio-controller; 181 #gpio-cells = <2>; 182 interrupt-controller; 183 #interrupt-cells = <2>; 184 reg = <0x40000 0x400>; 185 clocks = <&ck_icn_ls_mcu>; 186 st,bank-name = "GPIOE"; 187 status = "disabled"; 188 }; 189 190 gpiof: gpio@44290000 { 191 gpio-controller; 192 #gpio-cells = <2>; 193 interrupt-controller; 194 #interrupt-cells = <2>; 195 reg = <0x50000 0x400>; 196 clocks = <&ck_icn_ls_mcu>; 197 st,bank-name = "GPIOF"; 198 status = "disabled"; 199 }; 200 201 gpiog: gpio@442a0000 { 202 gpio-controller; 203 #gpio-cells = <2>; 204 interrupt-controller; 205 #interrupt-cells = <2>; 206 reg = <0x60000 0x400>; 207 clocks = <&ck_icn_ls_mcu>; 208 st,bank-name = "GPIOG"; 209 status = "disabled"; 210 }; 211 212 gpioh: gpio@442b0000 { 213 gpio-controller; 214 #gpio-cells = <2>; 215 interrupt-controller; 216 #interrupt-cells = <2>; 217 reg = <0x70000 0x400>; 218 clocks = <&ck_icn_ls_mcu>; 219 st,bank-name = "GPIOH"; 220 status = "disabled"; 221 }; 222 223 gpioi: gpio@442c0000 { 224 gpio-controller; 225 #gpio-cells = <2>; 226 interrupt-controller; 227 #interrupt-cells = <2>; 228 reg = <0x80000 0x400>; 229 clocks = <&ck_icn_ls_mcu>; 230 st,bank-name = "GPIOI"; 231 status = "disabled"; 232 }; 233 234 gpioj: gpio@442d0000 { 235 gpio-controller; 236 #gpio-cells = <2>; 237 interrupt-controller; 238 #interrupt-cells = <2>; 239 reg = <0x90000 0x400>; 240 clocks = <&ck_icn_ls_mcu>; 241 st,bank-name = "GPIOJ"; 242 status = "disabled"; 243 }; 244 245 gpiok: gpio@442e0000 { 246 gpio-controller; 247 #gpio-cells = <2>; 248 interrupt-controller; 249 #interrupt-cells = <2>; 250 reg = <0xa0000 0x400>; 251 clocks = <&ck_icn_ls_mcu>; 252 st,bank-name = "GPIOK"; 253 status = "disabled"; 254 }; 255 }; 256 257 pinctrl_z: pinctrl@46200000 { 258 #address-cells = <1>; 259 #size-cells = <1>; 260 compatible = "st,stm32mp257-z-pinctrl"; 261 ranges = <0 0x46200000 0x400>; 262 pins-are-numbered; 263 264 gpioz: gpio@46200000 { 265 gpio-controller; 266 #gpio-cells = <2>; 267 interrupt-controller; 268 #interrupt-cells = <2>; 269 reg = <0 0x400>; 270 clocks = <&ck_icn_ls_mcu>; 271 st,bank-name = "GPIOZ"; 272 st,bank-ioport = <11>; 273 status = "disabled"; 274 }; 275 276 }; 277 }; 278}; 279