1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Clock specification for Xilinx ZynqMP 4 * 5 * (C) Copyright 2017 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 7 * 8 * Michal Simek <michal.simek@amd.com> 9 */ 10 11#include <dt-bindings/clock/xlnx-zynqmp-clk.h> 12/ { 13 pss_ref_clk: pss-ref-clk { 14 bootph-all; 15 compatible = "fixed-clock"; 16 #clock-cells = <0>; 17 clock-frequency = <33333333>; 18 clock-output-names = "pss_ref_clk"; 19 }; 20 21 video_clk: video-clk { 22 bootph-all; 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <27000000>; 26 clock-output-names = "video_clk"; 27 }; 28 29 pss_alt_ref_clk: pss-alt-ref-clk { 30 bootph-all; 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 clock-output-names = "pss_alt_ref_clk"; 35 }; 36 37 gt_crx_ref_clk: gt-crx-ref-clk { 38 bootph-all; 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <108000000>; 42 clock-output-names = "gt_crx_ref_clk"; 43 }; 44 45 aux_ref_clk: aux-ref-clk { 46 bootph-all; 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <27000000>; 50 clock-output-names = "aux_ref_clk"; 51 }; 52}; 53 54&zynqmp_firmware { 55 zynqmp_clk: clock-controller { 56 bootph-all; 57 #clock-cells = <1>; 58 compatible = "xlnx,zynqmp-clk"; 59 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, 60 <&aux_ref_clk>, <>_crx_ref_clk>; 61 clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", 62 "aux_ref_clk", "gt_crx_ref_clk"; 63 }; 64}; 65 66&can0 { 67 clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; 68}; 69 70&can1 { 71 clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; 72}; 73 74&cpu0 { 75 clocks = <&zynqmp_clk ACPU>; 76}; 77 78&fpd_dma_chan1 { 79 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 80}; 81 82&fpd_dma_chan2 { 83 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 84}; 85 86&fpd_dma_chan3 { 87 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 88}; 89 90&fpd_dma_chan4 { 91 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 92}; 93 94&fpd_dma_chan5 { 95 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 96}; 97 98&fpd_dma_chan6 { 99 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 100}; 101 102&fpd_dma_chan7 { 103 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 104}; 105 106&fpd_dma_chan8 { 107 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 108}; 109 110&gpu { 111 clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>; 112}; 113 114&lpd_dma_chan1 { 115 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 116}; 117 118&lpd_dma_chan2 { 119 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 120}; 121 122&lpd_dma_chan3 { 123 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 124}; 125 126&lpd_dma_chan4 { 127 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 128}; 129 130&lpd_dma_chan5 { 131 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 132}; 133 134&lpd_dma_chan6 { 135 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 136}; 137 138&lpd_dma_chan7 { 139 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 140}; 141 142&lpd_dma_chan8 { 143 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; 144}; 145 146&nand0 { 147 clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; 148}; 149 150&gem0 { 151 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, 152 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, 153 <&zynqmp_clk GEM_TSU>; 154 assigned-clocks = <&zynqmp_clk GEM_TSU>; 155}; 156 157&gem1 { 158 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, 159 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, 160 <&zynqmp_clk GEM_TSU>; 161 assigned-clocks = <&zynqmp_clk GEM_TSU>; 162}; 163 164&gem2 { 165 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, 166 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, 167 <&zynqmp_clk GEM_TSU>; 168 assigned-clocks = <&zynqmp_clk GEM_TSU>; 169}; 170 171&gem3 { 172 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, 173 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, 174 <&zynqmp_clk GEM_TSU>; 175 assigned-clocks = <&zynqmp_clk GEM_TSU>; 176}; 177 178&gpio { 179 clocks = <&zynqmp_clk LPD_LSBUS>; 180}; 181 182&i2c0 { 183 clocks = <&zynqmp_clk I2C0_REF>; 184}; 185 186&i2c1 { 187 clocks = <&zynqmp_clk I2C1_REF>; 188}; 189 190&pcie { 191 clocks = <&zynqmp_clk PCIE_REF>; 192}; 193 194&qspi { 195 clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; 196}; 197 198&sata { 199 clocks = <&zynqmp_clk SATA_REF>; 200}; 201 202&sdhci0 { 203 clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; 204 assigned-clocks = <&zynqmp_clk SDIO0_REF>; 205}; 206 207&sdhci1 { 208 clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; 209 assigned-clocks = <&zynqmp_clk SDIO1_REF>; 210}; 211 212&spi0 { 213 clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; 214}; 215 216&spi1 { 217 clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; 218}; 219 220&ttc0 { 221 clocks = <&zynqmp_clk LPD_LSBUS>; 222}; 223 224&ttc1 { 225 clocks = <&zynqmp_clk LPD_LSBUS>; 226}; 227 228&ttc2 { 229 clocks = <&zynqmp_clk LPD_LSBUS>; 230}; 231 232&ttc3 { 233 clocks = <&zynqmp_clk LPD_LSBUS>; 234}; 235 236&uart0 { 237 clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; 238}; 239 240&uart1 { 241 clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; 242}; 243 244&dwc3_0 { 245 clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; 246}; 247 248&dwc3_1 { 249 clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; 250}; 251 252&watchdog0 { 253 clocks = <&zynqmp_clk WDT>; 254}; 255 256&lpd_watchdog { 257 clocks = <&zynqmp_clk LPD_WDT>; 258}; 259 260&xilinx_ams { 261 clocks = <&zynqmp_clk AMS_REF>; 262}; 263 264&zynqmp_dpdma { 265 clocks = <&zynqmp_clk DPDMA_REF>; 266 assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ 267}; 268 269&zynqmp_dpsub { 270 clocks = <&zynqmp_clk TOPSW_LSBUS>, 271 <&zynqmp_clk DP_AUDIO_REF>, 272 <&zynqmp_clk DP_VIDEO_REF>; 273 assigned-clocks = <&zynqmp_clk DP_STC_REF>, 274 <&zynqmp_clk DP_AUDIO_REF>, 275 <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ 276}; 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