1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "amdgpu_atombios.h"
25 #include "hdp_v4_0.h"
26 #include "amdgpu_ras.h"
27
28 #include "hdp/hdp_4_0_offset.h"
29 #include "hdp/hdp_4_0_sh_mask.h"
30 #include <uapi/linux/kfd_ioctl.h>
31
32 /* for Vega20 register name change */
33 #define mmHDP_MEM_POWER_CTRL 0x00d4
34 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
35 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
36 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
37 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
38 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
39
hdp_v4_0_flush_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)40 static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
41 struct amdgpu_ring *ring)
42 {
43 if (!ring || !ring->funcs->emit_wreg) {
44 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
45 /* We just need to read back a register to post the write.
46 * Reading back the remapped register causes problems on
47 * some platforms so just read back the memory size register.
48 */
49 if (adev->nbio.funcs->get_memsize)
50 adev->nbio.funcs->get_memsize(adev);
51 } else {
52 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
53 }
54 }
55
hdp_v4_0_invalidate_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)56 static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
57 struct amdgpu_ring *ring)
58 {
59 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0) ||
60 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 2))
61 return;
62
63 if (!ring || !ring->funcs->emit_wreg) {
64 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
65 RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE);
66 } else {
67 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
68 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
69 }
70 }
71
hdp_v4_0_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)72 static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,
73 void *ras_error_status)
74 {
75 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
76
77 err_data->ue_count = 0;
78 err_data->ce_count = 0;
79
80 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
81 return;
82
83 /* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */
84 err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
85 };
86
hdp_v4_0_reset_ras_error_count(struct amdgpu_device * adev)87 static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
88 {
89 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
90 return;
91
92 if (adev->ip_versions[HDP_HWIP][0] >= IP_VERSION(4, 4, 0))
93 WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
94 else
95 /*read back hdp ras counter to reset it to 0 */
96 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
97 }
98
hdp_v4_0_update_clock_gating(struct amdgpu_device * adev,bool enable)99 static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
100 bool enable)
101 {
102 uint32_t def, data;
103
104 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 0) ||
105 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 1) ||
106 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 1) ||
107 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 0)) {
108 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
109
110 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
111 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
112 else
113 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
114
115 if (def != data)
116 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
117 } else {
118 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
119
120 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
121 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
122 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
123 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
124 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
125 else
126 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
127 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
128 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
129 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
130
131 if (def != data)
132 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
133 }
134 }
135
hdp_v4_0_get_clockgating_state(struct amdgpu_device * adev,u64 * flags)136 static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
137 u64 *flags)
138 {
139 int data;
140
141 /* AMD_CG_SUPPORT_HDP_LS */
142 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
143 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
144 *flags |= AMD_CG_SUPPORT_HDP_LS;
145 }
146
hdp_v4_0_init_registers(struct amdgpu_device * adev)147 static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
148 {
149 switch (adev->ip_versions[HDP_HWIP][0]) {
150 case IP_VERSION(4, 2, 1):
151 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
152 break;
153 default:
154 break;
155 }
156
157 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
158
159 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0))
160 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);
161
162 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
163 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
164 }
165
166 struct amdgpu_ras_block_hw_ops hdp_v4_0_ras_hw_ops = {
167 .query_ras_error_count = hdp_v4_0_query_ras_error_count,
168 .reset_ras_error_count = hdp_v4_0_reset_ras_error_count,
169 };
170
171 struct amdgpu_hdp_ras hdp_v4_0_ras = {
172 .ras_block = {
173 .hw_ops = &hdp_v4_0_ras_hw_ops,
174 },
175 };
176
177 const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
178 .flush_hdp = hdp_v4_0_flush_hdp,
179 .invalidate_hdp = hdp_v4_0_invalidate_hdp,
180 .update_clock_gating = hdp_v4_0_update_clock_gating,
181 .get_clock_gating_state = hdp_v4_0_get_clockgating_state,
182 .init_registers = hdp_v4_0_init_registers,
183 };
184