1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2015-2018 Broadcom */
3
4 #include <linux/delay.h>
5 #include <linux/mutex.h>
6 #include <linux/spinlock_types.h>
7 #include <linux/workqueue.h>
8
9 #include <drm/drm_encoder.h>
10 #include <drm/drm_gem.h>
11 #include <drm/drm_gem_shmem_helper.h>
12 #include <drm/gpu_scheduler.h>
13
14 #include "uapi/drm/v3d_drm.h"
15
16 struct clk;
17 struct platform_device;
18 struct reset_control;
19
20 #define GMP_GRANULARITY (128 * 1024)
21
22 #define V3D_MAX_QUEUES (V3D_CACHE_CLEAN + 1)
23
24 struct v3d_queue_state {
25 struct drm_gpu_scheduler sched;
26
27 u64 fence_context;
28 u64 emit_seqno;
29 };
30
31 /* Performance monitor object. The perform lifetime is controlled by userspace
32 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
33 * request, and when this is the case, HW perf counters will be activated just
34 * before the submit_cl is submitted to the GPU and disabled when the job is
35 * done. This way, only events related to a specific job will be counted.
36 */
37 struct v3d_perfmon {
38 /* Tracks the number of users of the perfmon, when this counter reaches
39 * zero the perfmon is destroyed.
40 */
41 refcount_t refcnt;
42
43 /* Protects perfmon stop, as it can be invoked from multiple places. */
44 struct mutex lock;
45
46 /* Number of counters activated in this perfmon instance
47 * (should be less than DRM_V3D_MAX_PERF_COUNTERS).
48 */
49 u8 ncounters;
50
51 /* Events counted by the HW perf counters. */
52 u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
53
54 /* Storage for counter values. Counters are incremented by the
55 * HW perf counter values every time the perfmon is attached
56 * to a GPU job. This way, perfmon users don't have to
57 * retrieve the results after each job if they want to track
58 * events covering several submissions. Note that counter
59 * values can't be reset, but you can fake a reset by
60 * destroying the perfmon and creating a new one.
61 */
62 u64 values[];
63 };
64
65 enum v3d_irq {
66 V3D_CORE_IRQ,
67 V3D_HUB_IRQ,
68 V3D_MAX_IRQS,
69 };
70
71 struct v3d_dev {
72 struct drm_device drm;
73
74 /* Short representation (e.g. 33, 41) of the V3D tech version
75 * and revision.
76 */
77 int ver;
78 bool single_irq_line;
79
80 int irq[V3D_MAX_IRQS];
81
82 void __iomem *hub_regs;
83 void __iomem *core_regs[3];
84 void __iomem *bridge_regs;
85 void __iomem *gca_regs;
86 struct clk *clk;
87 struct reset_control *reset;
88
89 /* Virtual and DMA addresses of the single shared page table. */
90 volatile u32 *pt;
91 dma_addr_t pt_paddr;
92
93 /* Virtual and DMA addresses of the MMU's scratch page. When
94 * a read or write is invalid in the MMU, it will be
95 * redirected here.
96 */
97 void *mmu_scratch;
98 dma_addr_t mmu_scratch_paddr;
99 /* virtual address bits from V3D to the MMU. */
100 int va_width;
101
102 /* Number of V3D cores. */
103 u32 cores;
104
105 /* Allocator managing the address space. All units are in
106 * number of pages.
107 */
108 struct drm_mm mm;
109 spinlock_t mm_lock;
110
111 struct work_struct overflow_mem_work;
112
113 struct v3d_bin_job *bin_job;
114 struct v3d_render_job *render_job;
115 struct v3d_tfu_job *tfu_job;
116 struct v3d_csd_job *csd_job;
117
118 struct v3d_queue_state queue[V3D_MAX_QUEUES];
119
120 /* Spinlock used to synchronize the overflow memory
121 * management against bin job submission.
122 */
123 spinlock_t job_lock;
124
125 /* Used to track the active perfmon if any. */
126 struct v3d_perfmon *active_perfmon;
127
128 /* Protects bo_stats */
129 struct mutex bo_lock;
130
131 /* Lock taken when resetting the GPU, to keep multiple
132 * processes from trying to park the scheduler threads and
133 * reset at once.
134 */
135 struct mutex reset_lock;
136
137 /* Lock taken when creating and pushing the GPU scheduler
138 * jobs, to keep the sched-fence seqnos in order.
139 */
140 struct mutex sched_lock;
141
142 /* Lock taken during a cache clean and when initiating an L2
143 * flush, to keep L2 flushes from interfering with the
144 * synchronous L2 cleans.
145 */
146 struct mutex cache_clean_lock;
147
148 struct {
149 u32 num_allocated;
150 u32 pages_allocated;
151 } bo_stats;
152 };
153
154 static inline struct v3d_dev *
to_v3d_dev(struct drm_device * dev)155 to_v3d_dev(struct drm_device *dev)
156 {
157 return container_of(dev, struct v3d_dev, drm);
158 }
159
160 static inline bool
v3d_has_csd(struct v3d_dev * v3d)161 v3d_has_csd(struct v3d_dev *v3d)
162 {
163 return v3d->ver >= 41;
164 }
165
166 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev)
167
168 /* The per-fd struct, which tracks the MMU mappings. */
169 struct v3d_file_priv {
170 struct v3d_dev *v3d;
171
172 struct {
173 struct idr idr;
174 struct mutex lock;
175 } perfmon;
176
177 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES];
178 };
179
180 struct v3d_bo {
181 struct drm_gem_shmem_object base;
182
183 struct drm_mm_node node;
184
185 /* List entry for the BO's position in
186 * v3d_render_job->unref_list
187 */
188 struct list_head unref_head;
189 };
190
191 static inline struct v3d_bo *
to_v3d_bo(struct drm_gem_object * bo)192 to_v3d_bo(struct drm_gem_object *bo)
193 {
194 return (struct v3d_bo *)bo;
195 }
196
197 struct v3d_fence {
198 struct dma_fence base;
199 struct drm_device *dev;
200 /* v3d seqno for signaled() test */
201 u64 seqno;
202 enum v3d_queue queue;
203 };
204
205 static inline struct v3d_fence *
to_v3d_fence(struct dma_fence * fence)206 to_v3d_fence(struct dma_fence *fence)
207 {
208 return (struct v3d_fence *)fence;
209 }
210
211 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
212 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
213
214 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
215 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
216
217 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
218 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
219
220 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
221 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
222
223 struct v3d_job {
224 struct drm_sched_job base;
225
226 struct kref refcount;
227
228 struct v3d_dev *v3d;
229
230 /* This is the array of BOs that were looked up at the start
231 * of submission.
232 */
233 struct drm_gem_object **bo;
234 u32 bo_count;
235
236 /* v3d fence to be signaled by IRQ handler when the job is complete. */
237 struct dma_fence *irq_fence;
238
239 /* scheduler fence for when the job is considered complete and
240 * the BO reservations can be released.
241 */
242 struct dma_fence *done_fence;
243
244 /* Pointer to a performance monitor object if the user requested it,
245 * NULL otherwise.
246 */
247 struct v3d_perfmon *perfmon;
248
249 /* Callback for the freeing of the job on refcount going to 0. */
250 void (*free)(struct kref *ref);
251 };
252
253 struct v3d_bin_job {
254 struct v3d_job base;
255
256 /* GPU virtual addresses of the start/end of the CL job. */
257 u32 start, end;
258
259 u32 timedout_ctca, timedout_ctra;
260
261 /* Corresponding render job, for attaching our overflow memory. */
262 struct v3d_render_job *render;
263
264 /* Submitted tile memory allocation start/size, tile state. */
265 u32 qma, qms, qts;
266 };
267
268 struct v3d_render_job {
269 struct v3d_job base;
270
271 /* GPU virtual addresses of the start/end of the CL job. */
272 u32 start, end;
273
274 u32 timedout_ctca, timedout_ctra;
275
276 /* List of overflow BOs used in the job that need to be
277 * released once the job is complete.
278 */
279 struct list_head unref_list;
280 };
281
282 struct v3d_tfu_job {
283 struct v3d_job base;
284
285 struct drm_v3d_submit_tfu args;
286 };
287
288 struct v3d_csd_job {
289 struct v3d_job base;
290
291 u32 timedout_batches;
292
293 struct drm_v3d_submit_csd args;
294 };
295
296 struct v3d_submit_outsync {
297 struct drm_syncobj *syncobj;
298 };
299
300 struct v3d_submit_ext {
301 u32 flags;
302 u32 wait_stage;
303
304 u32 in_sync_count;
305 u64 in_syncs;
306
307 u32 out_sync_count;
308 struct v3d_submit_outsync *out_syncs;
309 };
310
311 /**
312 * __wait_for - magic wait macro
313 *
314 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
315 * important that we check the condition again after having timed out, since the
316 * timeout could be due to preemption or similar and we've never had a chance to
317 * check the condition before the timeout.
318 */
319 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
320 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
321 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
322 int ret__; \
323 might_sleep(); \
324 for (;;) { \
325 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
326 OP; \
327 /* Guarantee COND check prior to timeout */ \
328 barrier(); \
329 if (COND) { \
330 ret__ = 0; \
331 break; \
332 } \
333 if (expired__) { \
334 ret__ = -ETIMEDOUT; \
335 break; \
336 } \
337 usleep_range(wait__, wait__ * 2); \
338 if (wait__ < (Wmax)) \
339 wait__ <<= 1; \
340 } \
341 ret__; \
342 })
343
344 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
345 (Wmax))
346 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
347
nsecs_to_jiffies_timeout(const u64 n)348 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
349 {
350 /* nsecs_to_jiffies64() does not guard against overflow */
351 if ((NSEC_PER_SEC % HZ) != 0 &&
352 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
353 return MAX_JIFFY_OFFSET;
354
355 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
356 }
357
358 /* v3d_bo.c */
359 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size);
360 void v3d_free_object(struct drm_gem_object *gem_obj);
361 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv,
362 size_t size);
363 int v3d_create_bo_ioctl(struct drm_device *dev, void *data,
364 struct drm_file *file_priv);
365 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data,
366 struct drm_file *file_priv);
367 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data,
368 struct drm_file *file_priv);
369 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev,
370 struct dma_buf_attachment *attach,
371 struct sg_table *sgt);
372
373 /* v3d_debugfs.c */
374 void v3d_debugfs_init(struct drm_minor *minor);
375
376 /* v3d_fence.c */
377 extern const struct dma_fence_ops v3d_fence_ops;
378 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
379
380 /* v3d_gem.c */
381 int v3d_gem_init(struct drm_device *dev);
382 void v3d_gem_destroy(struct drm_device *dev);
383 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
384 struct drm_file *file_priv);
385 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data,
386 struct drm_file *file_priv);
387 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data,
388 struct drm_file *file_priv);
389 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
390 struct drm_file *file_priv);
391 void v3d_job_cleanup(struct v3d_job *job);
392 void v3d_job_put(struct v3d_job *job);
393 void v3d_reset(struct v3d_dev *v3d);
394 void v3d_invalidate_caches(struct v3d_dev *v3d);
395 void v3d_clean_caches(struct v3d_dev *v3d);
396
397 /* v3d_irq.c */
398 int v3d_irq_init(struct v3d_dev *v3d);
399 void v3d_irq_enable(struct v3d_dev *v3d);
400 void v3d_irq_disable(struct v3d_dev *v3d);
401 void v3d_irq_reset(struct v3d_dev *v3d);
402
403 /* v3d_mmu.c */
404 int v3d_mmu_get_offset(struct drm_file *file_priv, struct v3d_bo *bo,
405 u32 *offset);
406 int v3d_mmu_set_page_table(struct v3d_dev *v3d);
407 void v3d_mmu_insert_ptes(struct v3d_bo *bo);
408 void v3d_mmu_remove_ptes(struct v3d_bo *bo);
409
410 /* v3d_sched.c */
411 int v3d_sched_init(struct v3d_dev *v3d);
412 void v3d_sched_fini(struct v3d_dev *v3d);
413
414 /* v3d_perfmon.c */
415 void v3d_perfmon_get(struct v3d_perfmon *perfmon);
416 void v3d_perfmon_put(struct v3d_perfmon *perfmon);
417 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon);
418 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon,
419 bool capture);
420 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id);
421 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv);
422 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv);
423 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data,
424 struct drm_file *file_priv);
425 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
426 struct drm_file *file_priv);
427 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
428 struct drm_file *file_priv);
429