1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <dt-bindings/interconnect/qcom,sc7280.h> 14 15 #include "bcm-voter.h" 16 #include "icc-rpmh.h" 17 #include "sc7280.h" 18 19 static struct qcom_icc_node qhm_qspi = { 20 .name = "qhm_qspi", 21 .id = SC7280_MASTER_QSPI_0, 22 .channels = 1, 23 .buswidth = 4, 24 .num_links = 1, 25 .links = { SC7280_SLAVE_A1NOC_SNOC }, 26 }; 27 28 static struct qcom_icc_node qhm_qup0 = { 29 .name = "qhm_qup0", 30 .id = SC7280_MASTER_QUP_0, 31 .channels = 1, 32 .buswidth = 4, 33 .num_links = 1, 34 .links = { SC7280_SLAVE_A1NOC_SNOC }, 35 }; 36 37 static struct qcom_icc_node qhm_qup1 = { 38 .name = "qhm_qup1", 39 .id = SC7280_MASTER_QUP_1, 40 .channels = 1, 41 .buswidth = 4, 42 .num_links = 1, 43 .links = { SC7280_SLAVE_A1NOC_SNOC }, 44 }; 45 46 static struct qcom_icc_node qnm_a1noc_cfg = { 47 .name = "qnm_a1noc_cfg", 48 .id = SC7280_MASTER_A1NOC_CFG, 49 .channels = 1, 50 .buswidth = 4, 51 .num_links = 1, 52 .links = { SC7280_SLAVE_SERVICE_A1NOC }, 53 }; 54 55 static struct qcom_icc_node xm_sdc1 = { 56 .name = "xm_sdc1", 57 .id = SC7280_MASTER_SDCC_1, 58 .channels = 1, 59 .buswidth = 8, 60 .num_links = 1, 61 .links = { SC7280_SLAVE_A1NOC_SNOC }, 62 }; 63 64 static struct qcom_icc_node xm_sdc2 = { 65 .name = "xm_sdc2", 66 .id = SC7280_MASTER_SDCC_2, 67 .channels = 1, 68 .buswidth = 8, 69 .num_links = 1, 70 .links = { SC7280_SLAVE_A1NOC_SNOC }, 71 }; 72 73 static struct qcom_icc_node xm_sdc4 = { 74 .name = "xm_sdc4", 75 .id = SC7280_MASTER_SDCC_4, 76 .channels = 1, 77 .buswidth = 8, 78 .num_links = 1, 79 .links = { SC7280_SLAVE_A1NOC_SNOC }, 80 }; 81 82 static struct qcom_icc_node xm_ufs_mem = { 83 .name = "xm_ufs_mem", 84 .id = SC7280_MASTER_UFS_MEM, 85 .channels = 1, 86 .buswidth = 8, 87 .num_links = 1, 88 .links = { SC7280_SLAVE_A1NOC_SNOC }, 89 }; 90 91 static struct qcom_icc_node xm_usb2 = { 92 .name = "xm_usb2", 93 .id = SC7280_MASTER_USB2, 94 .channels = 1, 95 .buswidth = 8, 96 .num_links = 1, 97 .links = { SC7280_SLAVE_A1NOC_SNOC }, 98 }; 99 100 static struct qcom_icc_node xm_usb3_0 = { 101 .name = "xm_usb3_0", 102 .id = SC7280_MASTER_USB3_0, 103 .channels = 1, 104 .buswidth = 8, 105 .num_links = 1, 106 .links = { SC7280_SLAVE_A1NOC_SNOC }, 107 }; 108 109 static struct qcom_icc_node qhm_qdss_bam = { 110 .name = "qhm_qdss_bam", 111 .id = SC7280_MASTER_QDSS_BAM, 112 .channels = 1, 113 .buswidth = 4, 114 .num_links = 1, 115 .links = { SC7280_SLAVE_A2NOC_SNOC }, 116 }; 117 118 static struct qcom_icc_node qnm_a2noc_cfg = { 119 .name = "qnm_a2noc_cfg", 120 .id = SC7280_MASTER_A2NOC_CFG, 121 .channels = 1, 122 .buswidth = 4, 123 .num_links = 1, 124 .links = { SC7280_SLAVE_SERVICE_A2NOC }, 125 }; 126 127 static struct qcom_icc_node qnm_cnoc_datapath = { 128 .name = "qnm_cnoc_datapath", 129 .id = SC7280_MASTER_CNOC_A2NOC, 130 .channels = 1, 131 .buswidth = 8, 132 .num_links = 1, 133 .links = { SC7280_SLAVE_A2NOC_SNOC }, 134 }; 135 136 static struct qcom_icc_node qxm_crypto = { 137 .name = "qxm_crypto", 138 .id = SC7280_MASTER_CRYPTO, 139 .channels = 1, 140 .buswidth = 8, 141 .num_links = 1, 142 .links = { SC7280_SLAVE_A2NOC_SNOC }, 143 }; 144 145 static struct qcom_icc_node qxm_ipa = { 146 .name = "qxm_ipa", 147 .id = SC7280_MASTER_IPA, 148 .channels = 1, 149 .buswidth = 8, 150 .num_links = 1, 151 .links = { SC7280_SLAVE_A2NOC_SNOC }, 152 }; 153 154 static struct qcom_icc_node xm_pcie3_0 = { 155 .name = "xm_pcie3_0", 156 .id = SC7280_MASTER_PCIE_0, 157 .channels = 1, 158 .buswidth = 8, 159 .num_links = 1, 160 .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC }, 161 }; 162 163 static struct qcom_icc_node xm_pcie3_1 = { 164 .name = "xm_pcie3_1", 165 .id = SC7280_MASTER_PCIE_1, 166 .channels = 1, 167 .buswidth = 8, 168 .num_links = 1, 169 .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC }, 170 }; 171 172 static struct qcom_icc_node xm_qdss_etr = { 173 .name = "xm_qdss_etr", 174 .id = SC7280_MASTER_QDSS_ETR, 175 .channels = 1, 176 .buswidth = 8, 177 .num_links = 1, 178 .links = { SC7280_SLAVE_A2NOC_SNOC }, 179 }; 180 181 static struct qcom_icc_node qup0_core_master = { 182 .name = "qup0_core_master", 183 .id = SC7280_MASTER_QUP_CORE_0, 184 .channels = 1, 185 .buswidth = 4, 186 .num_links = 1, 187 .links = { SC7280_SLAVE_QUP_CORE_0 }, 188 }; 189 190 static struct qcom_icc_node qup1_core_master = { 191 .name = "qup1_core_master", 192 .id = SC7280_MASTER_QUP_CORE_1, 193 .channels = 1, 194 .buswidth = 4, 195 .num_links = 1, 196 .links = { SC7280_SLAVE_QUP_CORE_1 }, 197 }; 198 199 static struct qcom_icc_node qnm_cnoc3_cnoc2 = { 200 .name = "qnm_cnoc3_cnoc2", 201 .id = SC7280_MASTER_CNOC3_CNOC2, 202 .channels = 1, 203 .buswidth = 8, 204 .num_links = 44, 205 .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH, 206 SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL, 207 SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG, 208 SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG, 209 SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG, 210 SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG, 211 SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG, 212 SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG, 213 SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS, 214 SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG, 215 SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM, 216 SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG, 217 SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG, 218 SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0, 219 SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1, 220 SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4, 221 SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR, 222 SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG, 223 SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0, 224 SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG, 225 SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG, 226 SC7280_SLAVE_CNOC_MNOC_CFG, SC7280_SLAVE_SNOC_CFG }, 227 }; 228 229 static struct qcom_icc_node xm_qdss_dap = { 230 .name = "xm_qdss_dap", 231 .id = SC7280_MASTER_QDSS_DAP, 232 .channels = 1, 233 .buswidth = 8, 234 .num_links = 45, 235 .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH, 236 SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL, 237 SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG, 238 SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG, 239 SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG, 240 SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG, 241 SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG, 242 SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG, 243 SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS, 244 SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG, 245 SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM, 246 SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG, 247 SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG, 248 SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0, 249 SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1, 250 SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4, 251 SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR, 252 SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG, 253 SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0, 254 SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG, 255 SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG, 256 SC7280_SLAVE_CNOC2_CNOC3, SC7280_SLAVE_CNOC_MNOC_CFG, 257 SC7280_SLAVE_SNOC_CFG }, 258 }; 259 260 static struct qcom_icc_node qnm_cnoc2_cnoc3 = { 261 .name = "qnm_cnoc2_cnoc3", 262 .id = SC7280_MASTER_CNOC2_CNOC3, 263 .channels = 1, 264 .buswidth = 8, 265 .num_links = 9, 266 .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS, 267 SC7280_SLAVE_CNOC_A2NOC, SC7280_SLAVE_DDRSS_CFG, 268 SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM, 269 SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM, 270 SC7280_SLAVE_TCU }, 271 }; 272 273 static struct qcom_icc_node qnm_gemnoc_cnoc = { 274 .name = "qnm_gemnoc_cnoc", 275 .id = SC7280_MASTER_GEM_NOC_CNOC, 276 .channels = 1, 277 .buswidth = 16, 278 .num_links = 9, 279 .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS, 280 SC7280_SLAVE_CNOC3_CNOC2, SC7280_SLAVE_DDRSS_CFG, 281 SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM, 282 SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM, 283 SC7280_SLAVE_TCU }, 284 }; 285 286 static struct qcom_icc_node qnm_gemnoc_pcie = { 287 .name = "qnm_gemnoc_pcie", 288 .id = SC7280_MASTER_GEM_NOC_PCIE_SNOC, 289 .channels = 1, 290 .buswidth = 8, 291 .num_links = 2, 292 .links = { SC7280_SLAVE_PCIE_0, SC7280_SLAVE_PCIE_1 }, 293 }; 294 295 static struct qcom_icc_node qnm_cnoc_dc_noc = { 296 .name = "qnm_cnoc_dc_noc", 297 .id = SC7280_MASTER_CNOC_DC_NOC, 298 .channels = 1, 299 .buswidth = 4, 300 .num_links = 2, 301 .links = { SC7280_SLAVE_LLCC_CFG, SC7280_SLAVE_GEM_NOC_CFG }, 302 }; 303 304 static struct qcom_icc_node alm_gpu_tcu = { 305 .name = "alm_gpu_tcu", 306 .id = SC7280_MASTER_GPU_TCU, 307 .channels = 1, 308 .buswidth = 8, 309 .num_links = 2, 310 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, 311 }; 312 313 static struct qcom_icc_node alm_sys_tcu = { 314 .name = "alm_sys_tcu", 315 .id = SC7280_MASTER_SYS_TCU, 316 .channels = 1, 317 .buswidth = 8, 318 .num_links = 2, 319 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, 320 }; 321 322 static struct qcom_icc_node chm_apps = { 323 .name = "chm_apps", 324 .id = SC7280_MASTER_APPSS_PROC, 325 .channels = 1, 326 .buswidth = 32, 327 .num_links = 3, 328 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC, 329 SC7280_SLAVE_MEM_NOC_PCIE_SNOC }, 330 }; 331 332 static struct qcom_icc_node qnm_cmpnoc = { 333 .name = "qnm_cmpnoc", 334 .id = SC7280_MASTER_COMPUTE_NOC, 335 .channels = 2, 336 .buswidth = 32, 337 .num_links = 2, 338 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, 339 }; 340 341 static struct qcom_icc_node qnm_gemnoc_cfg = { 342 .name = "qnm_gemnoc_cfg", 343 .id = SC7280_MASTER_GEM_NOC_CFG, 344 .channels = 1, 345 .buswidth = 4, 346 .num_links = 5, 347 .links = { SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, SC7280_SLAVE_MCDMA_MS_MPU_CFG, 348 SC7280_SLAVE_SERVICE_GEM_NOC_1, SC7280_SLAVE_SERVICE_GEM_NOC_2, 349 SC7280_SLAVE_SERVICE_GEM_NOC }, 350 }; 351 352 static struct qcom_icc_node qnm_gpu = { 353 .name = "qnm_gpu", 354 .id = SC7280_MASTER_GFX3D, 355 .channels = 2, 356 .buswidth = 32, 357 .num_links = 2, 358 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, 359 }; 360 361 static struct qcom_icc_node qnm_mnoc_hf = { 362 .name = "qnm_mnoc_hf", 363 .id = SC7280_MASTER_MNOC_HF_MEM_NOC, 364 .channels = 2, 365 .buswidth = 32, 366 .num_links = 1, 367 .links = { SC7280_SLAVE_LLCC }, 368 }; 369 370 static struct qcom_icc_node qnm_mnoc_sf = { 371 .name = "qnm_mnoc_sf", 372 .id = SC7280_MASTER_MNOC_SF_MEM_NOC, 373 .channels = 1, 374 .buswidth = 32, 375 .num_links = 2, 376 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, 377 }; 378 379 static struct qcom_icc_node qnm_pcie = { 380 .name = "qnm_pcie", 381 .id = SC7280_MASTER_ANOC_PCIE_GEM_NOC, 382 .channels = 1, 383 .buswidth = 16, 384 .num_links = 2, 385 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, 386 }; 387 388 static struct qcom_icc_node qnm_snoc_gc = { 389 .name = "qnm_snoc_gc", 390 .id = SC7280_MASTER_SNOC_GC_MEM_NOC, 391 .channels = 1, 392 .buswidth = 8, 393 .num_links = 1, 394 .links = { SC7280_SLAVE_LLCC }, 395 }; 396 397 static struct qcom_icc_node qnm_snoc_sf = { 398 .name = "qnm_snoc_sf", 399 .id = SC7280_MASTER_SNOC_SF_MEM_NOC, 400 .channels = 1, 401 .buswidth = 16, 402 .num_links = 3, 403 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC, 404 SC7280_SLAVE_MEM_NOC_PCIE_SNOC }, 405 }; 406 407 static struct qcom_icc_node qhm_config_noc = { 408 .name = "qhm_config_noc", 409 .id = SC7280_MASTER_CNOC_LPASS_AG_NOC, 410 .channels = 1, 411 .buswidth = 4, 412 .num_links = 6, 413 .links = { SC7280_SLAVE_LPASS_CORE_CFG, SC7280_SLAVE_LPASS_LPI_CFG, 414 SC7280_SLAVE_LPASS_MPU_CFG, SC7280_SLAVE_LPASS_TOP_CFG, 415 SC7280_SLAVE_SERVICES_LPASS_AML_NOC, SC7280_SLAVE_SERVICE_LPASS_AG_NOC }, 416 }; 417 418 static struct qcom_icc_node llcc_mc = { 419 .name = "llcc_mc", 420 .id = SC7280_MASTER_LLCC, 421 .channels = 2, 422 .buswidth = 4, 423 .num_links = 1, 424 .links = { SC7280_SLAVE_EBI1 }, 425 }; 426 427 static struct qcom_icc_node qnm_mnoc_cfg = { 428 .name = "qnm_mnoc_cfg", 429 .id = SC7280_MASTER_CNOC_MNOC_CFG, 430 .channels = 1, 431 .buswidth = 4, 432 .num_links = 1, 433 .links = { SC7280_SLAVE_SERVICE_MNOC }, 434 }; 435 436 static struct qcom_icc_node qnm_video0 = { 437 .name = "qnm_video0", 438 .id = SC7280_MASTER_VIDEO_P0, 439 .channels = 1, 440 .buswidth = 32, 441 .num_links = 1, 442 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, 443 }; 444 445 static struct qcom_icc_node qnm_video_cpu = { 446 .name = "qnm_video_cpu", 447 .id = SC7280_MASTER_VIDEO_PROC, 448 .channels = 1, 449 .buswidth = 8, 450 .num_links = 1, 451 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, 452 }; 453 454 static struct qcom_icc_node qxm_camnoc_hf = { 455 .name = "qxm_camnoc_hf", 456 .id = SC7280_MASTER_CAMNOC_HF, 457 .channels = 2, 458 .buswidth = 32, 459 .num_links = 1, 460 .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC }, 461 }; 462 463 static struct qcom_icc_node qxm_camnoc_icp = { 464 .name = "qxm_camnoc_icp", 465 .id = SC7280_MASTER_CAMNOC_ICP, 466 .channels = 1, 467 .buswidth = 8, 468 .num_links = 1, 469 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, 470 }; 471 472 static struct qcom_icc_node qxm_camnoc_sf = { 473 .name = "qxm_camnoc_sf", 474 .id = SC7280_MASTER_CAMNOC_SF, 475 .channels = 1, 476 .buswidth = 32, 477 .num_links = 1, 478 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, 479 }; 480 481 static struct qcom_icc_node qxm_mdp0 = { 482 .name = "qxm_mdp0", 483 .id = SC7280_MASTER_MDP0, 484 .channels = 1, 485 .buswidth = 32, 486 .num_links = 1, 487 .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC }, 488 }; 489 490 static struct qcom_icc_node qhm_nsp_noc_config = { 491 .name = "qhm_nsp_noc_config", 492 .id = SC7280_MASTER_CDSP_NOC_CFG, 493 .channels = 1, 494 .buswidth = 4, 495 .num_links = 1, 496 .links = { SC7280_SLAVE_SERVICE_NSP_NOC }, 497 }; 498 499 static struct qcom_icc_node qxm_nsp = { 500 .name = "qxm_nsp", 501 .id = SC7280_MASTER_CDSP_PROC, 502 .channels = 2, 503 .buswidth = 32, 504 .num_links = 1, 505 .links = { SC7280_SLAVE_CDSP_MEM_NOC }, 506 }; 507 508 static struct qcom_icc_node qnm_aggre1_noc = { 509 .name = "qnm_aggre1_noc", 510 .id = SC7280_MASTER_A1NOC_SNOC, 511 .channels = 1, 512 .buswidth = 16, 513 .num_links = 1, 514 .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF }, 515 }; 516 517 static struct qcom_icc_node qnm_aggre2_noc = { 518 .name = "qnm_aggre2_noc", 519 .id = SC7280_MASTER_A2NOC_SNOC, 520 .channels = 1, 521 .buswidth = 16, 522 .num_links = 1, 523 .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF }, 524 }; 525 526 static struct qcom_icc_node qnm_snoc_cfg = { 527 .name = "qnm_snoc_cfg", 528 .id = SC7280_MASTER_SNOC_CFG, 529 .channels = 1, 530 .buswidth = 4, 531 .num_links = 1, 532 .links = { SC7280_SLAVE_SERVICE_SNOC }, 533 }; 534 535 static struct qcom_icc_node qxm_pimem = { 536 .name = "qxm_pimem", 537 .id = SC7280_MASTER_PIMEM, 538 .channels = 1, 539 .buswidth = 8, 540 .num_links = 1, 541 .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC }, 542 }; 543 544 static struct qcom_icc_node xm_gic = { 545 .name = "xm_gic", 546 .id = SC7280_MASTER_GIC, 547 .channels = 1, 548 .buswidth = 8, 549 .num_links = 1, 550 .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC }, 551 }; 552 553 static struct qcom_icc_node qns_a1noc_snoc = { 554 .name = "qns_a1noc_snoc", 555 .id = SC7280_SLAVE_A1NOC_SNOC, 556 .channels = 1, 557 .buswidth = 16, 558 .num_links = 1, 559 .links = { SC7280_MASTER_A1NOC_SNOC }, 560 }; 561 562 static struct qcom_icc_node srvc_aggre1_noc = { 563 .name = "srvc_aggre1_noc", 564 .id = SC7280_SLAVE_SERVICE_A1NOC, 565 .channels = 1, 566 .buswidth = 4, 567 .num_links = 0, 568 }; 569 570 static struct qcom_icc_node qns_a2noc_snoc = { 571 .name = "qns_a2noc_snoc", 572 .id = SC7280_SLAVE_A2NOC_SNOC, 573 .channels = 1, 574 .buswidth = 16, 575 .num_links = 1, 576 .links = { SC7280_MASTER_A2NOC_SNOC }, 577 }; 578 579 static struct qcom_icc_node qns_pcie_mem_noc = { 580 .name = "qns_pcie_mem_noc", 581 .id = SC7280_SLAVE_ANOC_PCIE_GEM_NOC, 582 .channels = 1, 583 .buswidth = 16, 584 .num_links = 1, 585 .links = { SC7280_MASTER_ANOC_PCIE_GEM_NOC }, 586 }; 587 588 static struct qcom_icc_node srvc_aggre2_noc = { 589 .name = "srvc_aggre2_noc", 590 .id = SC7280_SLAVE_SERVICE_A2NOC, 591 .channels = 1, 592 .buswidth = 4, 593 .num_links = 0, 594 }; 595 596 static struct qcom_icc_node qup0_core_slave = { 597 .name = "qup0_core_slave", 598 .id = SC7280_SLAVE_QUP_CORE_0, 599 .channels = 1, 600 .buswidth = 4, 601 .num_links = 0, 602 }; 603 604 static struct qcom_icc_node qup1_core_slave = { 605 .name = "qup1_core_slave", 606 .id = SC7280_SLAVE_QUP_CORE_1, 607 .channels = 1, 608 .buswidth = 4, 609 .num_links = 0, 610 }; 611 612 static struct qcom_icc_node qhs_ahb2phy0 = { 613 .name = "qhs_ahb2phy0", 614 .id = SC7280_SLAVE_AHB2PHY_SOUTH, 615 .channels = 1, 616 .buswidth = 4, 617 .num_links = 0, 618 }; 619 620 static struct qcom_icc_node qhs_ahb2phy1 = { 621 .name = "qhs_ahb2phy1", 622 .id = SC7280_SLAVE_AHB2PHY_NORTH, 623 .channels = 1, 624 .buswidth = 4, 625 .num_links = 0, 626 }; 627 628 static struct qcom_icc_node qhs_camera_cfg = { 629 .name = "qhs_camera_cfg", 630 .id = SC7280_SLAVE_CAMERA_CFG, 631 .channels = 1, 632 .buswidth = 4, 633 .num_links = 0, 634 }; 635 636 static struct qcom_icc_node qhs_clk_ctl = { 637 .name = "qhs_clk_ctl", 638 .id = SC7280_SLAVE_CLK_CTL, 639 .channels = 1, 640 .buswidth = 4, 641 .num_links = 0, 642 }; 643 644 static struct qcom_icc_node qhs_compute_cfg = { 645 .name = "qhs_compute_cfg", 646 .id = SC7280_SLAVE_CDSP_CFG, 647 .channels = 1, 648 .buswidth = 4, 649 .num_links = 1, 650 .links = { SC7280_MASTER_CDSP_NOC_CFG }, 651 }; 652 653 static struct qcom_icc_node qhs_cpr_cx = { 654 .name = "qhs_cpr_cx", 655 .id = SC7280_SLAVE_RBCPR_CX_CFG, 656 .channels = 1, 657 .buswidth = 4, 658 .num_links = 0, 659 }; 660 661 static struct qcom_icc_node qhs_cpr_mx = { 662 .name = "qhs_cpr_mx", 663 .id = SC7280_SLAVE_RBCPR_MX_CFG, 664 .channels = 1, 665 .buswidth = 4, 666 .num_links = 0, 667 }; 668 669 static struct qcom_icc_node qhs_crypto0_cfg = { 670 .name = "qhs_crypto0_cfg", 671 .id = SC7280_SLAVE_CRYPTO_0_CFG, 672 .channels = 1, 673 .buswidth = 4, 674 .num_links = 0, 675 }; 676 677 static struct qcom_icc_node qhs_cx_rdpm = { 678 .name = "qhs_cx_rdpm", 679 .id = SC7280_SLAVE_CX_RDPM, 680 .channels = 1, 681 .buswidth = 4, 682 .num_links = 0, 683 }; 684 685 static struct qcom_icc_node qhs_dcc_cfg = { 686 .name = "qhs_dcc_cfg", 687 .id = SC7280_SLAVE_DCC_CFG, 688 .channels = 1, 689 .buswidth = 4, 690 .num_links = 0, 691 }; 692 693 static struct qcom_icc_node qhs_display_cfg = { 694 .name = "qhs_display_cfg", 695 .id = SC7280_SLAVE_DISPLAY_CFG, 696 .channels = 1, 697 .buswidth = 4, 698 .num_links = 0, 699 }; 700 701 static struct qcom_icc_node qhs_gpuss_cfg = { 702 .name = "qhs_gpuss_cfg", 703 .id = SC7280_SLAVE_GFX3D_CFG, 704 .channels = 1, 705 .buswidth = 8, 706 .num_links = 0, 707 }; 708 709 static struct qcom_icc_node qhs_hwkm = { 710 .name = "qhs_hwkm", 711 .id = SC7280_SLAVE_HWKM, 712 .channels = 1, 713 .buswidth = 4, 714 .num_links = 0, 715 }; 716 717 static struct qcom_icc_node qhs_imem_cfg = { 718 .name = "qhs_imem_cfg", 719 .id = SC7280_SLAVE_IMEM_CFG, 720 .channels = 1, 721 .buswidth = 4, 722 .num_links = 0, 723 }; 724 725 static struct qcom_icc_node qhs_ipa = { 726 .name = "qhs_ipa", 727 .id = SC7280_SLAVE_IPA_CFG, 728 .channels = 1, 729 .buswidth = 4, 730 .num_links = 0, 731 }; 732 733 static struct qcom_icc_node qhs_ipc_router = { 734 .name = "qhs_ipc_router", 735 .id = SC7280_SLAVE_IPC_ROUTER_CFG, 736 .channels = 1, 737 .buswidth = 4, 738 .num_links = 0, 739 }; 740 741 static struct qcom_icc_node qhs_lpass_cfg = { 742 .name = "qhs_lpass_cfg", 743 .id = SC7280_SLAVE_LPASS, 744 .channels = 1, 745 .buswidth = 4, 746 .num_links = 1, 747 .links = { SC7280_MASTER_CNOC_LPASS_AG_NOC }, 748 }; 749 750 static struct qcom_icc_node qhs_mss_cfg = { 751 .name = "qhs_mss_cfg", 752 .id = SC7280_SLAVE_CNOC_MSS, 753 .channels = 1, 754 .buswidth = 4, 755 .num_links = 0, 756 }; 757 758 static struct qcom_icc_node qhs_mx_rdpm = { 759 .name = "qhs_mx_rdpm", 760 .id = SC7280_SLAVE_MX_RDPM, 761 .channels = 1, 762 .buswidth = 4, 763 .num_links = 0, 764 }; 765 766 static struct qcom_icc_node qhs_pcie0_cfg = { 767 .name = "qhs_pcie0_cfg", 768 .id = SC7280_SLAVE_PCIE_0_CFG, 769 .channels = 1, 770 .buswidth = 4, 771 .num_links = 0, 772 }; 773 774 static struct qcom_icc_node qhs_pcie1_cfg = { 775 .name = "qhs_pcie1_cfg", 776 .id = SC7280_SLAVE_PCIE_1_CFG, 777 .channels = 1, 778 .buswidth = 4, 779 .num_links = 0, 780 }; 781 782 static struct qcom_icc_node qhs_pdm = { 783 .name = "qhs_pdm", 784 .id = SC7280_SLAVE_PDM, 785 .channels = 1, 786 .buswidth = 4, 787 .num_links = 0, 788 }; 789 790 static struct qcom_icc_node qhs_pimem_cfg = { 791 .name = "qhs_pimem_cfg", 792 .id = SC7280_SLAVE_PIMEM_CFG, 793 .channels = 1, 794 .buswidth = 4, 795 .num_links = 0, 796 }; 797 798 static struct qcom_icc_node qhs_pka_wrapper_cfg = { 799 .name = "qhs_pka_wrapper_cfg", 800 .id = SC7280_SLAVE_PKA_WRAPPER_CFG, 801 .channels = 1, 802 .buswidth = 4, 803 .num_links = 0, 804 }; 805 806 static struct qcom_icc_node qhs_pmu_wrapper_cfg = { 807 .name = "qhs_pmu_wrapper_cfg", 808 .id = SC7280_SLAVE_PMU_WRAPPER_CFG, 809 .channels = 1, 810 .buswidth = 4, 811 .num_links = 0, 812 }; 813 814 static struct qcom_icc_node qhs_qdss_cfg = { 815 .name = "qhs_qdss_cfg", 816 .id = SC7280_SLAVE_QDSS_CFG, 817 .channels = 1, 818 .buswidth = 4, 819 .num_links = 0, 820 }; 821 822 static struct qcom_icc_node qhs_qspi = { 823 .name = "qhs_qspi", 824 .id = SC7280_SLAVE_QSPI_0, 825 .channels = 1, 826 .buswidth = 4, 827 .num_links = 0, 828 }; 829 830 static struct qcom_icc_node qhs_qup0 = { 831 .name = "qhs_qup0", 832 .id = SC7280_SLAVE_QUP_0, 833 .channels = 1, 834 .buswidth = 4, 835 .num_links = 0, 836 }; 837 838 static struct qcom_icc_node qhs_qup1 = { 839 .name = "qhs_qup1", 840 .id = SC7280_SLAVE_QUP_1, 841 .channels = 1, 842 .buswidth = 4, 843 .num_links = 0, 844 }; 845 846 static struct qcom_icc_node qhs_sdc1 = { 847 .name = "qhs_sdc1", 848 .id = SC7280_SLAVE_SDCC_1, 849 .channels = 1, 850 .buswidth = 4, 851 .num_links = 0, 852 }; 853 854 static struct qcom_icc_node qhs_sdc2 = { 855 .name = "qhs_sdc2", 856 .id = SC7280_SLAVE_SDCC_2, 857 .channels = 1, 858 .buswidth = 4, 859 .num_links = 0, 860 }; 861 862 static struct qcom_icc_node qhs_sdc4 = { 863 .name = "qhs_sdc4", 864 .id = SC7280_SLAVE_SDCC_4, 865 .channels = 1, 866 .buswidth = 4, 867 .num_links = 0, 868 }; 869 870 static struct qcom_icc_node qhs_security = { 871 .name = "qhs_security", 872 .id = SC7280_SLAVE_SECURITY, 873 .channels = 1, 874 .buswidth = 4, 875 .num_links = 0, 876 }; 877 878 static struct qcom_icc_node qhs_tcsr = { 879 .name = "qhs_tcsr", 880 .id = SC7280_SLAVE_TCSR, 881 .channels = 1, 882 .buswidth = 4, 883 .num_links = 0, 884 }; 885 886 static struct qcom_icc_node qhs_tlmm = { 887 .name = "qhs_tlmm", 888 .id = SC7280_SLAVE_TLMM, 889 .channels = 1, 890 .buswidth = 4, 891 .num_links = 0, 892 }; 893 894 static struct qcom_icc_node qhs_ufs_mem_cfg = { 895 .name = "qhs_ufs_mem_cfg", 896 .id = SC7280_SLAVE_UFS_MEM_CFG, 897 .channels = 1, 898 .buswidth = 4, 899 .num_links = 0, 900 }; 901 902 static struct qcom_icc_node qhs_usb2 = { 903 .name = "qhs_usb2", 904 .id = SC7280_SLAVE_USB2, 905 .channels = 1, 906 .buswidth = 4, 907 .num_links = 0, 908 }; 909 910 static struct qcom_icc_node qhs_usb3_0 = { 911 .name = "qhs_usb3_0", 912 .id = SC7280_SLAVE_USB3_0, 913 .channels = 1, 914 .buswidth = 4, 915 .num_links = 0, 916 }; 917 918 static struct qcom_icc_node qhs_venus_cfg = { 919 .name = "qhs_venus_cfg", 920 .id = SC7280_SLAVE_VENUS_CFG, 921 .channels = 1, 922 .buswidth = 4, 923 .num_links = 0, 924 }; 925 926 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 927 .name = "qhs_vsense_ctrl_cfg", 928 .id = SC7280_SLAVE_VSENSE_CTRL_CFG, 929 .channels = 1, 930 .buswidth = 4, 931 .num_links = 0, 932 }; 933 934 static struct qcom_icc_node qns_a1_noc_cfg = { 935 .name = "qns_a1_noc_cfg", 936 .id = SC7280_SLAVE_A1NOC_CFG, 937 .channels = 1, 938 .buswidth = 4, 939 .num_links = 1, 940 .links = { SC7280_MASTER_A1NOC_CFG }, 941 }; 942 943 static struct qcom_icc_node qns_a2_noc_cfg = { 944 .name = "qns_a2_noc_cfg", 945 .id = SC7280_SLAVE_A2NOC_CFG, 946 .channels = 1, 947 .buswidth = 4, 948 .num_links = 1, 949 .links = { SC7280_MASTER_A2NOC_CFG }, 950 }; 951 952 static struct qcom_icc_node qns_cnoc2_cnoc3 = { 953 .name = "qns_cnoc2_cnoc3", 954 .id = SC7280_SLAVE_CNOC2_CNOC3, 955 .channels = 1, 956 .buswidth = 8, 957 .num_links = 1, 958 .links = { SC7280_MASTER_CNOC2_CNOC3 }, 959 }; 960 961 static struct qcom_icc_node qns_mnoc_cfg = { 962 .name = "qns_mnoc_cfg", 963 .id = SC7280_SLAVE_CNOC_MNOC_CFG, 964 .channels = 1, 965 .buswidth = 4, 966 .num_links = 1, 967 .links = { SC7280_MASTER_CNOC_MNOC_CFG }, 968 }; 969 970 static struct qcom_icc_node qns_snoc_cfg = { 971 .name = "qns_snoc_cfg", 972 .id = SC7280_SLAVE_SNOC_CFG, 973 .channels = 1, 974 .buswidth = 4, 975 .num_links = 1, 976 .links = { SC7280_MASTER_SNOC_CFG }, 977 }; 978 979 static struct qcom_icc_node qhs_aoss = { 980 .name = "qhs_aoss", 981 .id = SC7280_SLAVE_AOSS, 982 .channels = 1, 983 .buswidth = 4, 984 .num_links = 0, 985 }; 986 987 static struct qcom_icc_node qhs_apss = { 988 .name = "qhs_apss", 989 .id = SC7280_SLAVE_APPSS, 990 .channels = 1, 991 .buswidth = 8, 992 .num_links = 0, 993 }; 994 995 static struct qcom_icc_node qns_cnoc3_cnoc2 = { 996 .name = "qns_cnoc3_cnoc2", 997 .id = SC7280_SLAVE_CNOC3_CNOC2, 998 .channels = 1, 999 .buswidth = 8, 1000 .num_links = 1, 1001 .links = { SC7280_MASTER_CNOC3_CNOC2 }, 1002 }; 1003 1004 static struct qcom_icc_node qns_cnoc_a2noc = { 1005 .name = "qns_cnoc_a2noc", 1006 .id = SC7280_SLAVE_CNOC_A2NOC, 1007 .channels = 1, 1008 .buswidth = 8, 1009 .num_links = 1, 1010 .links = { SC7280_MASTER_CNOC_A2NOC }, 1011 }; 1012 1013 static struct qcom_icc_node qns_ddrss_cfg = { 1014 .name = "qns_ddrss_cfg", 1015 .id = SC7280_SLAVE_DDRSS_CFG, 1016 .channels = 1, 1017 .buswidth = 4, 1018 .num_links = 1, 1019 .links = { SC7280_MASTER_CNOC_DC_NOC }, 1020 }; 1021 1022 static struct qcom_icc_node qxs_boot_imem = { 1023 .name = "qxs_boot_imem", 1024 .id = SC7280_SLAVE_BOOT_IMEM, 1025 .channels = 1, 1026 .buswidth = 8, 1027 .num_links = 0, 1028 }; 1029 1030 static struct qcom_icc_node qxs_imem = { 1031 .name = "qxs_imem", 1032 .id = SC7280_SLAVE_IMEM, 1033 .channels = 1, 1034 .buswidth = 8, 1035 .num_links = 0, 1036 }; 1037 1038 static struct qcom_icc_node qxs_pimem = { 1039 .name = "qxs_pimem", 1040 .id = SC7280_SLAVE_PIMEM, 1041 .channels = 1, 1042 .buswidth = 8, 1043 .num_links = 0, 1044 }; 1045 1046 static struct qcom_icc_node xs_pcie_0 = { 1047 .name = "xs_pcie_0", 1048 .id = SC7280_SLAVE_PCIE_0, 1049 .channels = 1, 1050 .buswidth = 8, 1051 .num_links = 0, 1052 }; 1053 1054 static struct qcom_icc_node xs_pcie_1 = { 1055 .name = "xs_pcie_1", 1056 .id = SC7280_SLAVE_PCIE_1, 1057 .channels = 1, 1058 .buswidth = 8, 1059 .num_links = 0, 1060 }; 1061 1062 static struct qcom_icc_node xs_qdss_stm = { 1063 .name = "xs_qdss_stm", 1064 .id = SC7280_SLAVE_QDSS_STM, 1065 .channels = 1, 1066 .buswidth = 4, 1067 .num_links = 0, 1068 }; 1069 1070 static struct qcom_icc_node xs_sys_tcu_cfg = { 1071 .name = "xs_sys_tcu_cfg", 1072 .id = SC7280_SLAVE_TCU, 1073 .channels = 1, 1074 .buswidth = 8, 1075 .num_links = 0, 1076 }; 1077 1078 static struct qcom_icc_node qhs_llcc = { 1079 .name = "qhs_llcc", 1080 .id = SC7280_SLAVE_LLCC_CFG, 1081 .channels = 1, 1082 .buswidth = 4, 1083 .num_links = 0, 1084 }; 1085 1086 static struct qcom_icc_node qns_gemnoc = { 1087 .name = "qns_gemnoc", 1088 .id = SC7280_SLAVE_GEM_NOC_CFG, 1089 .channels = 1, 1090 .buswidth = 4, 1091 .num_links = 1, 1092 .links = { SC7280_MASTER_GEM_NOC_CFG }, 1093 }; 1094 1095 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1096 .name = "qhs_mdsp_ms_mpu_cfg", 1097 .id = SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, 1098 .channels = 1, 1099 .buswidth = 4, 1100 .num_links = 0, 1101 }; 1102 1103 static struct qcom_icc_node qhs_modem_ms_mpu_cfg = { 1104 .name = "qhs_modem_ms_mpu_cfg", 1105 .id = SC7280_SLAVE_MCDMA_MS_MPU_CFG, 1106 .channels = 1, 1107 .buswidth = 4, 1108 .num_links = 0, 1109 }; 1110 1111 static struct qcom_icc_node qns_gem_noc_cnoc = { 1112 .name = "qns_gem_noc_cnoc", 1113 .id = SC7280_SLAVE_GEM_NOC_CNOC, 1114 .channels = 1, 1115 .buswidth = 16, 1116 .num_links = 1, 1117 .links = { SC7280_MASTER_GEM_NOC_CNOC }, 1118 }; 1119 1120 static struct qcom_icc_node qns_llcc = { 1121 .name = "qns_llcc", 1122 .id = SC7280_SLAVE_LLCC, 1123 .channels = 2, 1124 .buswidth = 16, 1125 .num_links = 1, 1126 .links = { SC7280_MASTER_LLCC }, 1127 }; 1128 1129 static struct qcom_icc_node qns_pcie = { 1130 .name = "qns_pcie", 1131 .id = SC7280_SLAVE_MEM_NOC_PCIE_SNOC, 1132 .channels = 1, 1133 .buswidth = 8, 1134 .num_links = 1, 1135 .links = { SC7280_MASTER_GEM_NOC_PCIE_SNOC }, 1136 }; 1137 1138 static struct qcom_icc_node srvc_even_gemnoc = { 1139 .name = "srvc_even_gemnoc", 1140 .id = SC7280_SLAVE_SERVICE_GEM_NOC_1, 1141 .channels = 1, 1142 .buswidth = 4, 1143 .num_links = 0, 1144 }; 1145 1146 static struct qcom_icc_node srvc_odd_gemnoc = { 1147 .name = "srvc_odd_gemnoc", 1148 .id = SC7280_SLAVE_SERVICE_GEM_NOC_2, 1149 .channels = 1, 1150 .buswidth = 4, 1151 .num_links = 0, 1152 }; 1153 1154 static struct qcom_icc_node srvc_sys_gemnoc = { 1155 .name = "srvc_sys_gemnoc", 1156 .id = SC7280_SLAVE_SERVICE_GEM_NOC, 1157 .channels = 1, 1158 .buswidth = 4, 1159 .num_links = 0, 1160 }; 1161 1162 static struct qcom_icc_node qhs_lpass_core = { 1163 .name = "qhs_lpass_core", 1164 .id = SC7280_SLAVE_LPASS_CORE_CFG, 1165 .channels = 1, 1166 .buswidth = 4, 1167 .num_links = 0, 1168 }; 1169 1170 static struct qcom_icc_node qhs_lpass_lpi = { 1171 .name = "qhs_lpass_lpi", 1172 .id = SC7280_SLAVE_LPASS_LPI_CFG, 1173 .channels = 1, 1174 .buswidth = 4, 1175 .num_links = 0, 1176 }; 1177 1178 static struct qcom_icc_node qhs_lpass_mpu = { 1179 .name = "qhs_lpass_mpu", 1180 .id = SC7280_SLAVE_LPASS_MPU_CFG, 1181 .channels = 1, 1182 .buswidth = 4, 1183 .num_links = 0, 1184 }; 1185 1186 static struct qcom_icc_node qhs_lpass_top = { 1187 .name = "qhs_lpass_top", 1188 .id = SC7280_SLAVE_LPASS_TOP_CFG, 1189 .channels = 1, 1190 .buswidth = 4, 1191 .num_links = 0, 1192 }; 1193 1194 static struct qcom_icc_node srvc_niu_aml_noc = { 1195 .name = "srvc_niu_aml_noc", 1196 .id = SC7280_SLAVE_SERVICES_LPASS_AML_NOC, 1197 .channels = 1, 1198 .buswidth = 4, 1199 .num_links = 0, 1200 }; 1201 1202 static struct qcom_icc_node srvc_niu_lpass_agnoc = { 1203 .name = "srvc_niu_lpass_agnoc", 1204 .id = SC7280_SLAVE_SERVICE_LPASS_AG_NOC, 1205 .channels = 1, 1206 .buswidth = 4, 1207 .num_links = 0, 1208 }; 1209 1210 static struct qcom_icc_node ebi = { 1211 .name = "ebi", 1212 .id = SC7280_SLAVE_EBI1, 1213 .channels = 2, 1214 .buswidth = 4, 1215 .num_links = 0, 1216 }; 1217 1218 static struct qcom_icc_node qns_mem_noc_hf = { 1219 .name = "qns_mem_noc_hf", 1220 .id = SC7280_SLAVE_MNOC_HF_MEM_NOC, 1221 .channels = 2, 1222 .buswidth = 32, 1223 .num_links = 1, 1224 .links = { SC7280_MASTER_MNOC_HF_MEM_NOC }, 1225 }; 1226 1227 static struct qcom_icc_node qns_mem_noc_sf = { 1228 .name = "qns_mem_noc_sf", 1229 .id = SC7280_SLAVE_MNOC_SF_MEM_NOC, 1230 .channels = 1, 1231 .buswidth = 32, 1232 .num_links = 1, 1233 .links = { SC7280_MASTER_MNOC_SF_MEM_NOC }, 1234 }; 1235 1236 static struct qcom_icc_node srvc_mnoc = { 1237 .name = "srvc_mnoc", 1238 .id = SC7280_SLAVE_SERVICE_MNOC, 1239 .channels = 1, 1240 .buswidth = 4, 1241 .num_links = 0, 1242 }; 1243 1244 static struct qcom_icc_node qns_nsp_gemnoc = { 1245 .name = "qns_nsp_gemnoc", 1246 .id = SC7280_SLAVE_CDSP_MEM_NOC, 1247 .channels = 2, 1248 .buswidth = 32, 1249 .num_links = 1, 1250 .links = { SC7280_MASTER_COMPUTE_NOC }, 1251 }; 1252 1253 static struct qcom_icc_node service_nsp_noc = { 1254 .name = "service_nsp_noc", 1255 .id = SC7280_SLAVE_SERVICE_NSP_NOC, 1256 .channels = 1, 1257 .buswidth = 4, 1258 .num_links = 0, 1259 }; 1260 1261 static struct qcom_icc_node qns_gemnoc_gc = { 1262 .name = "qns_gemnoc_gc", 1263 .id = SC7280_SLAVE_SNOC_GEM_NOC_GC, 1264 .channels = 1, 1265 .buswidth = 8, 1266 .num_links = 1, 1267 .links = { SC7280_MASTER_SNOC_GC_MEM_NOC }, 1268 }; 1269 1270 static struct qcom_icc_node qns_gemnoc_sf = { 1271 .name = "qns_gemnoc_sf", 1272 .id = SC7280_SLAVE_SNOC_GEM_NOC_SF, 1273 .channels = 1, 1274 .buswidth = 16, 1275 .num_links = 1, 1276 .links = { SC7280_MASTER_SNOC_SF_MEM_NOC }, 1277 }; 1278 1279 static struct qcom_icc_node srvc_snoc = { 1280 .name = "srvc_snoc", 1281 .id = SC7280_SLAVE_SERVICE_SNOC, 1282 .channels = 1, 1283 .buswidth = 4, 1284 .num_links = 0, 1285 }; 1286 1287 static struct qcom_icc_bcm bcm_acv = { 1288 .name = "ACV", 1289 .enable_mask = BIT(3), 1290 .num_nodes = 1, 1291 .nodes = { &ebi }, 1292 }; 1293 1294 static struct qcom_icc_bcm bcm_ce0 = { 1295 .name = "CE0", 1296 .num_nodes = 1, 1297 .nodes = { &qxm_crypto }, 1298 }; 1299 1300 static struct qcom_icc_bcm bcm_cn0 = { 1301 .name = "CN0", 1302 .keepalive = true, 1303 .num_nodes = 2, 1304 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, 1305 }; 1306 1307 static struct qcom_icc_bcm bcm_cn1 = { 1308 .name = "CN1", 1309 .num_nodes = 47, 1310 .nodes = { &qnm_cnoc3_cnoc2, &xm_qdss_dap, 1311 &qhs_ahb2phy0, &qhs_ahb2phy1, 1312 &qhs_camera_cfg, &qhs_clk_ctl, 1313 &qhs_compute_cfg, &qhs_cpr_cx, 1314 &qhs_cpr_mx, &qhs_crypto0_cfg, 1315 &qhs_cx_rdpm, &qhs_dcc_cfg, 1316 &qhs_display_cfg, &qhs_gpuss_cfg, 1317 &qhs_hwkm, &qhs_imem_cfg, 1318 &qhs_ipa, &qhs_ipc_router, 1319 &qhs_mss_cfg, &qhs_mx_rdpm, 1320 &qhs_pcie0_cfg, &qhs_pcie1_cfg, 1321 &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, 1322 &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, 1323 &qhs_qup0, &qhs_qup1, 1324 &qhs_security, &qhs_tcsr, 1325 &qhs_tlmm, &qhs_ufs_mem_cfg, &qhs_usb2, 1326 &qhs_usb3_0, &qhs_venus_cfg, 1327 &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, 1328 &qns_a2_noc_cfg, &qns_cnoc2_cnoc3, 1329 &qns_mnoc_cfg, &qns_snoc_cfg, 1330 &qnm_cnoc2_cnoc3, &qhs_aoss, 1331 &qhs_apss, &qns_cnoc3_cnoc2, 1332 &qns_cnoc_a2noc, &qns_ddrss_cfg }, 1333 }; 1334 1335 static struct qcom_icc_bcm bcm_cn2 = { 1336 .name = "CN2", 1337 .num_nodes = 6, 1338 .nodes = { &qhs_lpass_cfg, &qhs_pdm, 1339 &qhs_qspi, &qhs_sdc1, 1340 &qhs_sdc2, &qhs_sdc4 }, 1341 }; 1342 1343 static struct qcom_icc_bcm bcm_co0 = { 1344 .name = "CO0", 1345 .num_nodes = 1, 1346 .nodes = { &qns_nsp_gemnoc }, 1347 }; 1348 1349 static struct qcom_icc_bcm bcm_co3 = { 1350 .name = "CO3", 1351 .num_nodes = 1, 1352 .nodes = { &qxm_nsp }, 1353 }; 1354 1355 static struct qcom_icc_bcm bcm_mc0 = { 1356 .name = "MC0", 1357 .keepalive = true, 1358 .num_nodes = 1, 1359 .nodes = { &ebi }, 1360 }; 1361 1362 static struct qcom_icc_bcm bcm_mm0 = { 1363 .name = "MM0", 1364 .keepalive = true, 1365 .num_nodes = 1, 1366 .nodes = { &qns_mem_noc_hf }, 1367 }; 1368 1369 static struct qcom_icc_bcm bcm_mm1 = { 1370 .name = "MM1", 1371 .num_nodes = 2, 1372 .nodes = { &qxm_camnoc_hf, &qxm_mdp0 }, 1373 }; 1374 1375 static struct qcom_icc_bcm bcm_mm4 = { 1376 .name = "MM4", 1377 .num_nodes = 1, 1378 .nodes = { &qns_mem_noc_sf }, 1379 }; 1380 1381 static struct qcom_icc_bcm bcm_mm5 = { 1382 .name = "MM5", 1383 .num_nodes = 3, 1384 .nodes = { &qnm_video0, &qxm_camnoc_icp, 1385 &qxm_camnoc_sf }, 1386 }; 1387 1388 static struct qcom_icc_bcm bcm_qup0 = { 1389 .name = "QUP0", 1390 .vote_scale = 1, 1391 .num_nodes = 1, 1392 .nodes = { &qup0_core_slave }, 1393 }; 1394 1395 static struct qcom_icc_bcm bcm_qup1 = { 1396 .name = "QUP1", 1397 .vote_scale = 1, 1398 .num_nodes = 1, 1399 .nodes = { &qup1_core_slave }, 1400 }; 1401 1402 static struct qcom_icc_bcm bcm_sh0 = { 1403 .name = "SH0", 1404 .keepalive = true, 1405 .num_nodes = 1, 1406 .nodes = { &qns_llcc }, 1407 }; 1408 1409 static struct qcom_icc_bcm bcm_sh2 = { 1410 .name = "SH2", 1411 .num_nodes = 2, 1412 .nodes = { &alm_gpu_tcu, &alm_sys_tcu }, 1413 }; 1414 1415 static struct qcom_icc_bcm bcm_sh3 = { 1416 .name = "SH3", 1417 .num_nodes = 1, 1418 .nodes = { &qnm_cmpnoc }, 1419 }; 1420 1421 static struct qcom_icc_bcm bcm_sh4 = { 1422 .name = "SH4", 1423 .num_nodes = 1, 1424 .nodes = { &chm_apps }, 1425 }; 1426 1427 static struct qcom_icc_bcm bcm_sn0 = { 1428 .name = "SN0", 1429 .keepalive = true, 1430 .num_nodes = 1, 1431 .nodes = { &qns_gemnoc_sf }, 1432 }; 1433 1434 static struct qcom_icc_bcm bcm_sn2 = { 1435 .name = "SN2", 1436 .num_nodes = 1, 1437 .nodes = { &qns_gemnoc_gc }, 1438 }; 1439 1440 static struct qcom_icc_bcm bcm_sn3 = { 1441 .name = "SN3", 1442 .num_nodes = 1, 1443 .nodes = { &qxs_pimem }, 1444 }; 1445 1446 static struct qcom_icc_bcm bcm_sn4 = { 1447 .name = "SN4", 1448 .num_nodes = 1, 1449 .nodes = { &xs_qdss_stm }, 1450 }; 1451 1452 static struct qcom_icc_bcm bcm_sn5 = { 1453 .name = "SN5", 1454 .num_nodes = 1, 1455 .nodes = { &xm_pcie3_0 }, 1456 }; 1457 1458 static struct qcom_icc_bcm bcm_sn6 = { 1459 .name = "SN6", 1460 .num_nodes = 1, 1461 .nodes = { &xm_pcie3_1 }, 1462 }; 1463 1464 static struct qcom_icc_bcm bcm_sn7 = { 1465 .name = "SN7", 1466 .num_nodes = 1, 1467 .nodes = { &qnm_aggre1_noc }, 1468 }; 1469 1470 static struct qcom_icc_bcm bcm_sn8 = { 1471 .name = "SN8", 1472 .num_nodes = 1, 1473 .nodes = { &qnm_aggre2_noc }, 1474 }; 1475 1476 static struct qcom_icc_bcm bcm_sn14 = { 1477 .name = "SN14", 1478 .num_nodes = 1, 1479 .nodes = { &qns_pcie_mem_noc }, 1480 }; 1481 1482 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1483 &bcm_sn5, 1484 &bcm_sn6, 1485 &bcm_sn14, 1486 }; 1487 1488 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1489 [MASTER_QSPI_0] = &qhm_qspi, 1490 [MASTER_QUP_0] = &qhm_qup0, 1491 [MASTER_QUP_1] = &qhm_qup1, 1492 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, 1493 [MASTER_PCIE_0] = &xm_pcie3_0, 1494 [MASTER_PCIE_1] = &xm_pcie3_1, 1495 [MASTER_SDCC_1] = &xm_sdc1, 1496 [MASTER_SDCC_2] = &xm_sdc2, 1497 [MASTER_SDCC_4] = &xm_sdc4, 1498 [MASTER_UFS_MEM] = &xm_ufs_mem, 1499 [MASTER_USB2] = &xm_usb2, 1500 [MASTER_USB3_0] = &xm_usb3_0, 1501 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1502 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1503 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1504 }; 1505 1506 static const struct qcom_icc_desc sc7280_aggre1_noc = { 1507 .nodes = aggre1_noc_nodes, 1508 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1509 .bcms = aggre1_noc_bcms, 1510 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1511 }; 1512 1513 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1514 &bcm_ce0, 1515 }; 1516 1517 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1518 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1519 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, 1520 [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath, 1521 [MASTER_CRYPTO] = &qxm_crypto, 1522 [MASTER_IPA] = &qxm_ipa, 1523 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1524 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1525 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1526 }; 1527 1528 static const struct qcom_icc_desc sc7280_aggre2_noc = { 1529 .nodes = aggre2_noc_nodes, 1530 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1531 .bcms = aggre2_noc_bcms, 1532 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1533 }; 1534 1535 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1536 &bcm_qup0, 1537 &bcm_qup1, 1538 }; 1539 1540 static struct qcom_icc_node * const clk_virt_nodes[] = { 1541 [MASTER_QUP_CORE_0] = &qup0_core_master, 1542 [MASTER_QUP_CORE_1] = &qup1_core_master, 1543 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1544 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1545 }; 1546 1547 static const struct qcom_icc_desc sc7280_clk_virt = { 1548 .nodes = clk_virt_nodes, 1549 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1550 .bcms = clk_virt_bcms, 1551 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1552 }; 1553 1554 static struct qcom_icc_bcm * const cnoc2_bcms[] = { 1555 &bcm_cn1, 1556 &bcm_cn2, 1557 }; 1558 1559 static struct qcom_icc_node * const cnoc2_nodes[] = { 1560 [MASTER_CNOC3_CNOC2] = &qnm_cnoc3_cnoc2, 1561 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1562 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1563 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1564 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1565 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1566 [SLAVE_CDSP_CFG] = &qhs_compute_cfg, 1567 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1568 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1569 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1570 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 1571 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1572 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1573 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1574 [SLAVE_HWKM] = &qhs_hwkm, 1575 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1576 [SLAVE_IPA_CFG] = &qhs_ipa, 1577 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1578 [SLAVE_LPASS] = &qhs_lpass_cfg, 1579 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1580 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 1581 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1582 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1583 [SLAVE_PDM] = &qhs_pdm, 1584 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1585 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg, 1586 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg, 1587 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1588 [SLAVE_QSPI_0] = &qhs_qspi, 1589 [SLAVE_QUP_0] = &qhs_qup0, 1590 [SLAVE_QUP_1] = &qhs_qup1, 1591 [SLAVE_SDCC_1] = &qhs_sdc1, 1592 [SLAVE_SDCC_2] = &qhs_sdc2, 1593 [SLAVE_SDCC_4] = &qhs_sdc4, 1594 [SLAVE_SECURITY] = &qhs_security, 1595 [SLAVE_TCSR] = &qhs_tcsr, 1596 [SLAVE_TLMM] = &qhs_tlmm, 1597 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1598 [SLAVE_USB2] = &qhs_usb2, 1599 [SLAVE_USB3_0] = &qhs_usb3_0, 1600 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1601 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1602 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, 1603 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, 1604 [SLAVE_CNOC2_CNOC3] = &qns_cnoc2_cnoc3, 1605 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, 1606 [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 1607 }; 1608 1609 static const struct qcom_icc_desc sc7280_cnoc2 = { 1610 .nodes = cnoc2_nodes, 1611 .num_nodes = ARRAY_SIZE(cnoc2_nodes), 1612 .bcms = cnoc2_bcms, 1613 .num_bcms = ARRAY_SIZE(cnoc2_bcms), 1614 }; 1615 1616 static struct qcom_icc_bcm * const cnoc3_bcms[] = { 1617 &bcm_cn0, 1618 &bcm_cn1, 1619 &bcm_sn3, 1620 &bcm_sn4, 1621 }; 1622 1623 static struct qcom_icc_node * const cnoc3_nodes[] = { 1624 [MASTER_CNOC2_CNOC3] = &qnm_cnoc2_cnoc3, 1625 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1626 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1627 [SLAVE_AOSS] = &qhs_aoss, 1628 [SLAVE_APPSS] = &qhs_apss, 1629 [SLAVE_CNOC3_CNOC2] = &qns_cnoc3_cnoc2, 1630 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1631 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 1632 [SLAVE_BOOT_IMEM] = &qxs_boot_imem, 1633 [SLAVE_IMEM] = &qxs_imem, 1634 [SLAVE_PIMEM] = &qxs_pimem, 1635 [SLAVE_PCIE_0] = &xs_pcie_0, 1636 [SLAVE_PCIE_1] = &xs_pcie_1, 1637 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1638 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1639 }; 1640 1641 static const struct qcom_icc_desc sc7280_cnoc3 = { 1642 .nodes = cnoc3_nodes, 1643 .num_nodes = ARRAY_SIZE(cnoc3_nodes), 1644 .bcms = cnoc3_bcms, 1645 .num_bcms = ARRAY_SIZE(cnoc3_bcms), 1646 }; 1647 1648 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1649 }; 1650 1651 static struct qcom_icc_node * const dc_noc_nodes[] = { 1652 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, 1653 [SLAVE_LLCC_CFG] = &qhs_llcc, 1654 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, 1655 }; 1656 1657 static const struct qcom_icc_desc sc7280_dc_noc = { 1658 .nodes = dc_noc_nodes, 1659 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1660 .bcms = dc_noc_bcms, 1661 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1662 }; 1663 1664 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1665 &bcm_sh0, 1666 &bcm_sh2, 1667 &bcm_sh3, 1668 &bcm_sh4, 1669 }; 1670 1671 static struct qcom_icc_node * const gem_noc_nodes[] = { 1672 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1673 [MASTER_SYS_TCU] = &alm_sys_tcu, 1674 [MASTER_APPSS_PROC] = &chm_apps, 1675 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1676 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, 1677 [MASTER_GFX3D] = &qnm_gpu, 1678 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1679 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1680 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1681 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1682 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1683 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1684 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg, 1685 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1686 [SLAVE_LLCC] = &qns_llcc, 1687 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1688 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, 1689 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, 1690 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, 1691 }; 1692 1693 static const struct qcom_icc_desc sc7280_gem_noc = { 1694 .nodes = gem_noc_nodes, 1695 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1696 .bcms = gem_noc_bcms, 1697 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1698 }; 1699 1700 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { 1701 }; 1702 1703 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 1704 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 1705 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 1706 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 1707 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 1708 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 1709 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 1710 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 1711 }; 1712 1713 static const struct qcom_icc_desc sc7280_lpass_ag_noc = { 1714 .nodes = lpass_ag_noc_nodes, 1715 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 1716 .bcms = lpass_ag_noc_bcms, 1717 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 1718 }; 1719 1720 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1721 &bcm_acv, 1722 &bcm_mc0, 1723 }; 1724 1725 static struct qcom_icc_node * const mc_virt_nodes[] = { 1726 [MASTER_LLCC] = &llcc_mc, 1727 [SLAVE_EBI1] = &ebi, 1728 }; 1729 1730 static const struct qcom_icc_desc sc7280_mc_virt = { 1731 .nodes = mc_virt_nodes, 1732 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1733 .bcms = mc_virt_bcms, 1734 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1735 }; 1736 1737 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1738 &bcm_mm0, 1739 &bcm_mm1, 1740 &bcm_mm4, 1741 &bcm_mm5, 1742 }; 1743 1744 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1745 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, 1746 [MASTER_VIDEO_P0] = &qnm_video0, 1747 [MASTER_VIDEO_PROC] = &qnm_video_cpu, 1748 [MASTER_CAMNOC_HF] = &qxm_camnoc_hf, 1749 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp, 1750 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1751 [MASTER_MDP0] = &qxm_mdp0, 1752 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1753 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1754 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1755 }; 1756 1757 static const struct qcom_icc_desc sc7280_mmss_noc = { 1758 .nodes = mmss_noc_nodes, 1759 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1760 .bcms = mmss_noc_bcms, 1761 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1762 }; 1763 1764 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 1765 &bcm_co0, 1766 &bcm_co3, 1767 }; 1768 1769 static struct qcom_icc_node * const nsp_noc_nodes[] = { 1770 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 1771 [MASTER_CDSP_PROC] = &qxm_nsp, 1772 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 1773 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 1774 }; 1775 1776 static const struct qcom_icc_desc sc7280_nsp_noc = { 1777 .nodes = nsp_noc_nodes, 1778 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 1779 .bcms = nsp_noc_bcms, 1780 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 1781 }; 1782 1783 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1784 &bcm_sn0, 1785 &bcm_sn2, 1786 &bcm_sn7, 1787 &bcm_sn8, 1788 }; 1789 1790 static struct qcom_icc_node * const system_noc_nodes[] = { 1791 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1792 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1793 [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 1794 [MASTER_PIMEM] = &qxm_pimem, 1795 [MASTER_GIC] = &xm_gic, 1796 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1797 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1798 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1799 }; 1800 1801 static const struct qcom_icc_desc sc7280_system_noc = { 1802 .nodes = system_noc_nodes, 1803 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1804 .bcms = system_noc_bcms, 1805 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1806 }; 1807 1808 static const struct of_device_id qnoc_of_match[] = { 1809 { .compatible = "qcom,sc7280-aggre1-noc", 1810 .data = &sc7280_aggre1_noc}, 1811 { .compatible = "qcom,sc7280-aggre2-noc", 1812 .data = &sc7280_aggre2_noc}, 1813 { .compatible = "qcom,sc7280-clk-virt", 1814 .data = &sc7280_clk_virt}, 1815 { .compatible = "qcom,sc7280-cnoc2", 1816 .data = &sc7280_cnoc2}, 1817 { .compatible = "qcom,sc7280-cnoc3", 1818 .data = &sc7280_cnoc3}, 1819 { .compatible = "qcom,sc7280-dc-noc", 1820 .data = &sc7280_dc_noc}, 1821 { .compatible = "qcom,sc7280-gem-noc", 1822 .data = &sc7280_gem_noc}, 1823 { .compatible = "qcom,sc7280-lpass-ag-noc", 1824 .data = &sc7280_lpass_ag_noc}, 1825 { .compatible = "qcom,sc7280-mc-virt", 1826 .data = &sc7280_mc_virt}, 1827 { .compatible = "qcom,sc7280-mmss-noc", 1828 .data = &sc7280_mmss_noc}, 1829 { .compatible = "qcom,sc7280-nsp-noc", 1830 .data = &sc7280_nsp_noc}, 1831 { .compatible = "qcom,sc7280-system-noc", 1832 .data = &sc7280_system_noc}, 1833 { } 1834 }; 1835 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1836 1837 static struct platform_driver qnoc_driver = { 1838 .probe = qcom_icc_rpmh_probe, 1839 .remove = qcom_icc_rpmh_remove, 1840 .driver = { 1841 .name = "qnoc-sc7280", 1842 .of_match_table = qnoc_of_match, 1843 .sync_state = icc_sync_state, 1844 }, 1845 }; 1846 module_platform_driver(qnoc_driver); 1847 1848 MODULE_DESCRIPTION("SC7280 NoC driver"); 1849 MODULE_LICENSE("GPL v2"); 1850