1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R-Car PWM Timer driver
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 *
7 * Limitations:
8 * - The hardware cannot generate a 0% duty cycle.
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/clk.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/log2.h>
16 #include <linux/math64.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/pwm.h>
22 #include <linux/slab.h>
23
24 #define RCAR_PWM_MAX_DIVISION 24
25 #define RCAR_PWM_MAX_CYCLE 1023
26
27 #define RCAR_PWMCR 0x00
28 #define RCAR_PWMCR_CC0_MASK 0x000f0000
29 #define RCAR_PWMCR_CC0_SHIFT 16
30 #define RCAR_PWMCR_CCMD BIT(15)
31 #define RCAR_PWMCR_SYNC BIT(11)
32 #define RCAR_PWMCR_SS0 BIT(4)
33 #define RCAR_PWMCR_EN0 BIT(0)
34
35 #define RCAR_PWMCNT 0x04
36 #define RCAR_PWMCNT_CYC0_MASK 0x03ff0000
37 #define RCAR_PWMCNT_CYC0_SHIFT 16
38 #define RCAR_PWMCNT_PH0_MASK 0x000003ff
39 #define RCAR_PWMCNT_PH0_SHIFT 0
40
41 struct rcar_pwm_chip {
42 struct pwm_chip chip;
43 void __iomem *base;
44 struct clk *clk;
45 };
46
to_rcar_pwm_chip(struct pwm_chip * chip)47 static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
48 {
49 return container_of(chip, struct rcar_pwm_chip, chip);
50 }
51
rcar_pwm_write(struct rcar_pwm_chip * rp,u32 data,unsigned int offset)52 static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
53 unsigned int offset)
54 {
55 writel(data, rp->base + offset);
56 }
57
rcar_pwm_read(struct rcar_pwm_chip * rp,unsigned int offset)58 static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
59 {
60 return readl(rp->base + offset);
61 }
62
rcar_pwm_update(struct rcar_pwm_chip * rp,u32 mask,u32 data,unsigned int offset)63 static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
64 unsigned int offset)
65 {
66 u32 value;
67
68 value = rcar_pwm_read(rp, offset);
69 value &= ~mask;
70 value |= data & mask;
71 rcar_pwm_write(rp, value, offset);
72 }
73
rcar_pwm_get_clock_division(struct rcar_pwm_chip * rp,int period_ns)74 static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
75 {
76 unsigned long clk_rate = clk_get_rate(rp->clk);
77 u64 div, tmp;
78
79 if (clk_rate == 0)
80 return -EINVAL;
81
82 div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE;
83 tmp = (u64)period_ns * clk_rate + div - 1;
84 tmp = div64_u64(tmp, div);
85 div = ilog2(tmp - 1) + 1;
86
87 return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
88 }
89
rcar_pwm_set_clock_control(struct rcar_pwm_chip * rp,unsigned int div)90 static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
91 unsigned int div)
92 {
93 u32 value;
94
95 value = rcar_pwm_read(rp, RCAR_PWMCR);
96 value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK);
97
98 if (div & 1)
99 value |= RCAR_PWMCR_CCMD;
100
101 div >>= 1;
102
103 value |= div << RCAR_PWMCR_CC0_SHIFT;
104 rcar_pwm_write(rp, value, RCAR_PWMCR);
105 }
106
rcar_pwm_set_counter(struct rcar_pwm_chip * rp,int div,u64 duty_ns,u64 period_ns)107 static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, u64 duty_ns,
108 u64 period_ns)
109 {
110 unsigned long long tmp;
111 unsigned long clk_rate = clk_get_rate(rp->clk);
112 u32 cyc, ph;
113
114 /* div <= 24 == RCAR_PWM_MAX_DIVISION, so the shift doesn't overflow. */
115 tmp = mul_u64_u64_div_u64(period_ns, clk_rate, (u64)NSEC_PER_SEC << div);
116 if (tmp > FIELD_MAX(RCAR_PWMCNT_CYC0_MASK))
117 tmp = FIELD_MAX(RCAR_PWMCNT_CYC0_MASK);
118
119 cyc = FIELD_PREP(RCAR_PWMCNT_CYC0_MASK, tmp);
120
121 tmp = mul_u64_u64_div_u64(duty_ns, clk_rate, (u64)NSEC_PER_SEC << div);
122 if (tmp > FIELD_MAX(RCAR_PWMCNT_PH0_MASK))
123 tmp = FIELD_MAX(RCAR_PWMCNT_PH0_MASK);
124 ph = FIELD_PREP(RCAR_PWMCNT_PH0_MASK, tmp);
125
126 /* Avoid prohibited setting */
127 if (cyc == 0 || ph == 0)
128 return -EINVAL;
129
130 rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);
131
132 return 0;
133 }
134
rcar_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)135 static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
136 {
137 return pm_runtime_get_sync(chip->dev);
138 }
139
rcar_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)140 static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
141 {
142 pm_runtime_put(chip->dev);
143 }
144
rcar_pwm_enable(struct rcar_pwm_chip * rp)145 static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
146 {
147 u32 value;
148
149 /* Don't enable the PWM device if CYC0 or PH0 is 0 */
150 value = rcar_pwm_read(rp, RCAR_PWMCNT);
151 if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 ||
152 (value & RCAR_PWMCNT_PH0_MASK) == 0)
153 return -EINVAL;
154
155 rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
156
157 return 0;
158 }
159
rcar_pwm_disable(struct rcar_pwm_chip * rp)160 static void rcar_pwm_disable(struct rcar_pwm_chip *rp)
161 {
162 rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
163 }
164
rcar_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)165 static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
166 const struct pwm_state *state)
167 {
168 struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
169 int div, ret;
170
171 /* This HW/driver only supports normal polarity */
172 if (state->polarity != PWM_POLARITY_NORMAL)
173 return -EINVAL;
174
175 if (!state->enabled) {
176 rcar_pwm_disable(rp);
177 return 0;
178 }
179
180 div = rcar_pwm_get_clock_division(rp, state->period);
181 if (div < 0)
182 return div;
183
184 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
185
186 ret = rcar_pwm_set_counter(rp, div, state->duty_cycle, state->period);
187 if (!ret)
188 rcar_pwm_set_clock_control(rp, div);
189
190 /* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
191 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);
192
193 if (!ret)
194 ret = rcar_pwm_enable(rp);
195
196 return ret;
197 }
198
199 static const struct pwm_ops rcar_pwm_ops = {
200 .request = rcar_pwm_request,
201 .free = rcar_pwm_free,
202 .apply = rcar_pwm_apply,
203 .owner = THIS_MODULE,
204 };
205
rcar_pwm_probe(struct platform_device * pdev)206 static int rcar_pwm_probe(struct platform_device *pdev)
207 {
208 struct rcar_pwm_chip *rcar_pwm;
209 int ret;
210
211 rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL);
212 if (rcar_pwm == NULL)
213 return -ENOMEM;
214
215 rcar_pwm->base = devm_platform_ioremap_resource(pdev, 0);
216 if (IS_ERR(rcar_pwm->base))
217 return PTR_ERR(rcar_pwm->base);
218
219 rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL);
220 if (IS_ERR(rcar_pwm->clk)) {
221 dev_err(&pdev->dev, "cannot get clock\n");
222 return PTR_ERR(rcar_pwm->clk);
223 }
224
225 platform_set_drvdata(pdev, rcar_pwm);
226
227 rcar_pwm->chip.dev = &pdev->dev;
228 rcar_pwm->chip.ops = &rcar_pwm_ops;
229 rcar_pwm->chip.npwm = 1;
230
231 pm_runtime_enable(&pdev->dev);
232
233 ret = pwmchip_add(&rcar_pwm->chip);
234 if (ret < 0) {
235 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
236 pm_runtime_disable(&pdev->dev);
237 return ret;
238 }
239
240 return 0;
241 }
242
rcar_pwm_remove(struct platform_device * pdev)243 static void rcar_pwm_remove(struct platform_device *pdev)
244 {
245 struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
246
247 pwmchip_remove(&rcar_pwm->chip);
248
249 pm_runtime_disable(&pdev->dev);
250 }
251
252 static const struct of_device_id rcar_pwm_of_table[] = {
253 { .compatible = "renesas,pwm-rcar", },
254 { },
255 };
256 MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
257
258 static struct platform_driver rcar_pwm_driver = {
259 .probe = rcar_pwm_probe,
260 .remove_new = rcar_pwm_remove,
261 .driver = {
262 .name = "pwm-rcar",
263 .of_match_table = rcar_pwm_of_table,
264 }
265 };
266 module_platform_driver(rcar_pwm_driver);
267
268 MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
269 MODULE_DESCRIPTION("Renesas PWM Timer Driver");
270 MODULE_LICENSE("GPL v2");
271 MODULE_ALIAS("platform:pwm-rcar");
272