1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2016 IBM Corporation
4 *
5 * Joel Stanley <joel@jms.id.au>
6 */
7
8 #include <linux/bits.h>
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/kstrtox.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_irq.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
20 #include <linux/watchdog.h>
21
22 static bool nowayout = WATCHDOG_NOWAYOUT;
23 module_param(nowayout, bool, 0);
24 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
25 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
26 struct aspeed_wdt_scu {
27 const char *compatible;
28 u32 reset_status_reg;
29 u32 wdt_reset_mask;
30 u32 wdt_reset_mask_shift;
31 };
32
33 struct aspeed_wdt_config {
34 u32 ext_pulse_width_mask;
35 u32 irq_shift;
36 u32 irq_mask;
37 struct aspeed_wdt_scu scu;
38 };
39
40 struct aspeed_wdt {
41 struct watchdog_device wdd;
42 void __iomem *base;
43 u32 ctrl;
44 const struct aspeed_wdt_config *cfg;
45 };
46
47 static const struct aspeed_wdt_config ast2400_config = {
48 .ext_pulse_width_mask = 0xff,
49 .irq_shift = 0,
50 .irq_mask = 0,
51 .scu = {
52 .compatible = "aspeed,ast2400-scu",
53 .reset_status_reg = 0x3c,
54 .wdt_reset_mask = 0x1,
55 .wdt_reset_mask_shift = 1,
56 },
57 };
58
59 static const struct aspeed_wdt_config ast2500_config = {
60 .ext_pulse_width_mask = 0xfffff,
61 .irq_shift = 12,
62 .irq_mask = GENMASK(31, 12),
63 .scu = {
64 .compatible = "aspeed,ast2500-scu",
65 .reset_status_reg = 0x3c,
66 .wdt_reset_mask = 0x1,
67 .wdt_reset_mask_shift = 2,
68 },
69 };
70
71 static const struct aspeed_wdt_config ast2600_config = {
72 .ext_pulse_width_mask = 0xfffff,
73 .irq_shift = 0,
74 .irq_mask = GENMASK(31, 10),
75 .scu = {
76 .compatible = "aspeed,ast2600-scu",
77 .reset_status_reg = 0x74,
78 .wdt_reset_mask = 0xf,
79 .wdt_reset_mask_shift = 16,
80 },
81 };
82
83 static const struct of_device_id aspeed_wdt_of_table[] = {
84 { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
85 { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
86 { .compatible = "aspeed,ast2600-wdt", .data = &ast2600_config },
87 { },
88 };
89 MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
90
91 #define WDT_STATUS 0x00
92 #define WDT_RELOAD_VALUE 0x04
93 #define WDT_RESTART 0x08
94 #define WDT_CTRL 0x0C
95 #define WDT_CTRL_BOOT_SECONDARY BIT(7)
96 #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
97 #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
98 #define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5)
99 #define WDT_CTRL_1MHZ_CLK BIT(4)
100 #define WDT_CTRL_WDT_EXT BIT(3)
101 #define WDT_CTRL_WDT_INTR BIT(2)
102 #define WDT_CTRL_RESET_SYSTEM BIT(1)
103 #define WDT_CTRL_ENABLE BIT(0)
104 #define WDT_TIMEOUT_STATUS 0x10
105 #define WDT_TIMEOUT_STATUS_IRQ BIT(2)
106 #define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
107 #define WDT_CLEAR_TIMEOUT_STATUS 0x14
108 #define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
109
110 /*
111 * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
112 * enabled), specifically:
113 *
114 * * Pulse duration
115 * * Drive mode: push-pull vs open-drain
116 * * Polarity: Active high or active low
117 *
118 * Pulse duration configuration is available on both the AST2400 and AST2500,
119 * though the field changes between SoCs:
120 *
121 * AST2400: Bits 7:0
122 * AST2500: Bits 19:0
123 *
124 * This difference is captured in struct aspeed_wdt_config.
125 *
126 * The AST2500 exposes the drive mode and polarity options, but not in a
127 * regular fashion. For read purposes, bit 31 represents active high or low,
128 * and bit 30 represents push-pull or open-drain. With respect to write, magic
129 * values need to be written to the top byte to change the state of the drive
130 * mode and polarity bits. Any other value written to the top byte has no
131 * effect on the state of the drive mode or polarity bits. However, the pulse
132 * width value must be preserved (as desired) if written.
133 */
134 #define WDT_RESET_WIDTH 0x18
135 #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31)
136 #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)
137 #define WDT_ACTIVE_LOW_MAGIC (0x5A << 24)
138 #define WDT_RESET_WIDTH_PUSH_PULL BIT(30)
139 #define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
140 #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
141
142 #define WDT_RESTART_MAGIC 0x4755
143
144 /* 32 bits at 1MHz, in milliseconds */
145 #define WDT_MAX_TIMEOUT_MS 4294967
146 #define WDT_DEFAULT_TIMEOUT 30
147 #define WDT_RATE_1MHZ 1000000
148
to_aspeed_wdt(struct watchdog_device * wdd)149 static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd)
150 {
151 return container_of(wdd, struct aspeed_wdt, wdd);
152 }
153
aspeed_wdt_enable(struct aspeed_wdt * wdt,int count)154 static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
155 {
156 wdt->ctrl |= WDT_CTRL_ENABLE;
157
158 writel(0, wdt->base + WDT_CTRL);
159 writel(count, wdt->base + WDT_RELOAD_VALUE);
160 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
161 writel(wdt->ctrl, wdt->base + WDT_CTRL);
162 }
163
aspeed_wdt_start(struct watchdog_device * wdd)164 static int aspeed_wdt_start(struct watchdog_device *wdd)
165 {
166 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
167
168 aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ);
169
170 return 0;
171 }
172
aspeed_wdt_stop(struct watchdog_device * wdd)173 static int aspeed_wdt_stop(struct watchdog_device *wdd)
174 {
175 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
176
177 wdt->ctrl &= ~WDT_CTRL_ENABLE;
178 writel(wdt->ctrl, wdt->base + WDT_CTRL);
179
180 return 0;
181 }
182
aspeed_wdt_ping(struct watchdog_device * wdd)183 static int aspeed_wdt_ping(struct watchdog_device *wdd)
184 {
185 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
186
187 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
188
189 return 0;
190 }
191
aspeed_wdt_set_timeout(struct watchdog_device * wdd,unsigned int timeout)192 static int aspeed_wdt_set_timeout(struct watchdog_device *wdd,
193 unsigned int timeout)
194 {
195 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
196 u32 actual;
197
198 wdd->timeout = timeout;
199
200 actual = min(timeout, wdd->max_hw_heartbeat_ms / 1000);
201
202 writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
203 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
204
205 return 0;
206 }
207
aspeed_wdt_set_pretimeout(struct watchdog_device * wdd,unsigned int pretimeout)208 static int aspeed_wdt_set_pretimeout(struct watchdog_device *wdd,
209 unsigned int pretimeout)
210 {
211 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
212 u32 actual = pretimeout * WDT_RATE_1MHZ;
213 u32 s = wdt->cfg->irq_shift;
214 u32 m = wdt->cfg->irq_mask;
215
216 wdd->pretimeout = pretimeout;
217 wdt->ctrl &= ~m;
218 if (pretimeout)
219 wdt->ctrl |= ((actual << s) & m) | WDT_CTRL_WDT_INTR;
220 else
221 wdt->ctrl &= ~WDT_CTRL_WDT_INTR;
222
223 writel(wdt->ctrl, wdt->base + WDT_CTRL);
224
225 return 0;
226 }
227
aspeed_wdt_restart(struct watchdog_device * wdd,unsigned long action,void * data)228 static int aspeed_wdt_restart(struct watchdog_device *wdd,
229 unsigned long action, void *data)
230 {
231 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
232
233 wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;
234 aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);
235
236 mdelay(1000);
237
238 return 0;
239 }
240
aspeed_wdt_update_bootstatus(struct platform_device * pdev,struct aspeed_wdt * wdt)241 static void aspeed_wdt_update_bootstatus(struct platform_device *pdev,
242 struct aspeed_wdt *wdt)
243 {
244 const struct resource *res;
245 struct aspeed_wdt_scu scu = wdt->cfg->scu;
246 struct regmap *scu_base;
247 u32 reset_mask_width;
248 u32 reset_mask_shift;
249 u32 idx = 0;
250 u32 status;
251 int ret;
252
253 if (!of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2400-wdt")) {
254 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
255 idx = ((intptr_t)wdt->base & 0x00000fff) / (uintptr_t)resource_size(res);
256 }
257
258 scu_base = syscon_regmap_lookup_by_compatible(scu.compatible);
259 if (IS_ERR(scu_base)) {
260 wdt->wdd.bootstatus = WDIOS_UNKNOWN;
261 return;
262 }
263
264 ret = regmap_read(scu_base, scu.reset_status_reg, &status);
265 if (ret) {
266 wdt->wdd.bootstatus = WDIOS_UNKNOWN;
267 return;
268 }
269
270 reset_mask_width = hweight32(scu.wdt_reset_mask);
271 reset_mask_shift = scu.wdt_reset_mask_shift +
272 reset_mask_width * idx;
273
274 if (status & (scu.wdt_reset_mask << reset_mask_shift))
275 wdt->wdd.bootstatus = WDIOF_CARDRESET;
276
277 /* clear wdt reset event flag */
278 if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2400-wdt") ||
279 of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-wdt")) {
280 ret = regmap_read(scu_base, scu.reset_status_reg, &status);
281 if (!ret) {
282 status &= ~(scu.wdt_reset_mask << reset_mask_shift);
283 regmap_write(scu_base, scu.reset_status_reg, status);
284 }
285 } else {
286 regmap_write(scu_base, scu.reset_status_reg,
287 scu.wdt_reset_mask << reset_mask_shift);
288 }
289 }
290
291 /* access_cs0 shows if cs0 is accessible, hence the reverted bit */
access_cs0_show(struct device * dev,struct device_attribute * attr,char * buf)292 static ssize_t access_cs0_show(struct device *dev,
293 struct device_attribute *attr, char *buf)
294 {
295 struct aspeed_wdt *wdt = dev_get_drvdata(dev);
296 u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
297
298 return sysfs_emit(buf, "%u\n",
299 !(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY));
300 }
301
access_cs0_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)302 static ssize_t access_cs0_store(struct device *dev,
303 struct device_attribute *attr, const char *buf,
304 size_t size)
305 {
306 struct aspeed_wdt *wdt = dev_get_drvdata(dev);
307 unsigned long val;
308
309 if (kstrtoul(buf, 10, &val))
310 return -EINVAL;
311
312 if (val)
313 writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
314 wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
315
316 return size;
317 }
318
319 /*
320 * This attribute exists only if the system has booted from the alternate
321 * flash with 'alt-boot' option.
322 *
323 * At alternate flash the 'access_cs0' sysfs node provides:
324 * ast2400: a way to get access to the primary SPI flash chip at CS0
325 * after booting from the alternate chip at CS1.
326 * ast2500: a way to restore the normal address mapping from
327 * (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
328 *
329 * Clearing the boot code selection and timeout counter also resets to the
330 * initial state the chip select line mapping. When the SoC is in normal
331 * mapping state (i.e. booted from CS0), clearing those bits does nothing for
332 * both versions of the SoC. For alternate boot mode (booted from CS1 due to
333 * wdt2 expiration) the behavior differs as described above.
334 *
335 * This option can be used with wdt2 (watchdog1) only.
336 */
337 static DEVICE_ATTR_RW(access_cs0);
338
339 static struct attribute *bswitch_attrs[] = {
340 &dev_attr_access_cs0.attr,
341 NULL
342 };
343 ATTRIBUTE_GROUPS(bswitch);
344
345 static const struct watchdog_ops aspeed_wdt_ops = {
346 .start = aspeed_wdt_start,
347 .stop = aspeed_wdt_stop,
348 .ping = aspeed_wdt_ping,
349 .set_timeout = aspeed_wdt_set_timeout,
350 .set_pretimeout = aspeed_wdt_set_pretimeout,
351 .restart = aspeed_wdt_restart,
352 .owner = THIS_MODULE,
353 };
354
355 static const struct watchdog_info aspeed_wdt_info = {
356 .options = WDIOF_KEEPALIVEPING
357 | WDIOF_MAGICCLOSE
358 | WDIOF_SETTIMEOUT,
359 .identity = KBUILD_MODNAME,
360 };
361
362 static const struct watchdog_info aspeed_wdt_pretimeout_info = {
363 .options = WDIOF_KEEPALIVEPING
364 | WDIOF_PRETIMEOUT
365 | WDIOF_MAGICCLOSE
366 | WDIOF_SETTIMEOUT,
367 .identity = KBUILD_MODNAME,
368 };
369
aspeed_wdt_irq(int irq,void * arg)370 static irqreturn_t aspeed_wdt_irq(int irq, void *arg)
371 {
372 struct watchdog_device *wdd = arg;
373 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
374 u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
375
376 if (status & WDT_TIMEOUT_STATUS_IRQ)
377 watchdog_notify_pretimeout(wdd);
378
379 return IRQ_HANDLED;
380 }
381
aspeed_wdt_probe(struct platform_device * pdev)382 static int aspeed_wdt_probe(struct platform_device *pdev)
383 {
384 struct device *dev = &pdev->dev;
385 const struct of_device_id *ofdid;
386 struct aspeed_wdt *wdt;
387 struct device_node *np;
388 const char *reset_type;
389 u32 duration;
390 u32 status;
391 int ret;
392
393 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
394 if (!wdt)
395 return -ENOMEM;
396
397 np = dev->of_node;
398
399 ofdid = of_match_node(aspeed_wdt_of_table, np);
400 if (!ofdid)
401 return -EINVAL;
402 wdt->cfg = ofdid->data;
403
404 wdt->base = devm_platform_ioremap_resource(pdev, 0);
405 if (IS_ERR(wdt->base))
406 return PTR_ERR(wdt->base);
407
408 wdt->wdd.info = &aspeed_wdt_info;
409
410 if (wdt->cfg->irq_mask) {
411 int irq = platform_get_irq_optional(pdev, 0);
412
413 if (irq > 0) {
414 ret = devm_request_irq(dev, irq, aspeed_wdt_irq,
415 IRQF_SHARED, dev_name(dev),
416 wdt);
417 if (ret)
418 return ret;
419
420 wdt->wdd.info = &aspeed_wdt_pretimeout_info;
421 }
422 }
423
424 wdt->wdd.ops = &aspeed_wdt_ops;
425 wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
426 wdt->wdd.parent = dev;
427
428 wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
429 watchdog_init_timeout(&wdt->wdd, 0, dev);
430
431 watchdog_set_nowayout(&wdt->wdd, nowayout);
432
433 /*
434 * On clock rates:
435 * - ast2400 wdt can run at PCLK, or 1MHz
436 * - ast2500 only runs at 1MHz, hard coding bit 4 to 1
437 * - ast2600 always runs at 1MHz
438 *
439 * Set the ast2400 to run at 1MHz as it simplifies the driver.
440 */
441 if (of_device_is_compatible(np, "aspeed,ast2400-wdt"))
442 wdt->ctrl = WDT_CTRL_1MHZ_CLK;
443
444 /*
445 * Control reset on a per-device basis to ensure the
446 * host is not affected by a BMC reboot
447 */
448 ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
449 if (ret) {
450 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
451 } else {
452 if (!strcmp(reset_type, "cpu"))
453 wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
454 WDT_CTRL_RESET_SYSTEM;
455 else if (!strcmp(reset_type, "soc"))
456 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
457 WDT_CTRL_RESET_SYSTEM;
458 else if (!strcmp(reset_type, "system"))
459 wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
460 WDT_CTRL_RESET_SYSTEM;
461 else if (strcmp(reset_type, "none"))
462 return -EINVAL;
463 }
464 if (of_property_read_bool(np, "aspeed,external-signal"))
465 wdt->ctrl |= WDT_CTRL_WDT_EXT;
466 if (of_property_read_bool(np, "aspeed,alt-boot"))
467 wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY;
468
469 if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) {
470 /*
471 * The watchdog is running, but invoke aspeed_wdt_start() to
472 * write wdt->ctrl to WDT_CTRL to ensure the watchdog's
473 * configuration conforms to the driver's expectations.
474 * Primarily, ensure we're using the 1MHz clock source.
475 */
476 aspeed_wdt_start(&wdt->wdd);
477 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
478 }
479
480 if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
481 (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
482 u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
483
484 reg &= wdt->cfg->ext_pulse_width_mask;
485 if (of_property_read_bool(np, "aspeed,ext-active-high"))
486 reg |= WDT_ACTIVE_HIGH_MAGIC;
487 else
488 reg |= WDT_ACTIVE_LOW_MAGIC;
489
490 writel(reg, wdt->base + WDT_RESET_WIDTH);
491
492 reg &= wdt->cfg->ext_pulse_width_mask;
493 if (of_property_read_bool(np, "aspeed,ext-push-pull"))
494 reg |= WDT_PUSH_PULL_MAGIC;
495 else
496 reg |= WDT_OPEN_DRAIN_MAGIC;
497
498 writel(reg, wdt->base + WDT_RESET_WIDTH);
499 }
500
501 if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {
502 u32 max_duration = wdt->cfg->ext_pulse_width_mask + 1;
503
504 if (duration == 0 || duration > max_duration) {
505 dev_err(dev, "Invalid pulse duration: %uus\n",
506 duration);
507 duration = max(1U, min(max_duration, duration));
508 dev_info(dev, "Pulse duration set to %uus\n",
509 duration);
510 }
511
512 /*
513 * The watchdog is always configured with a 1MHz source, so
514 * there is no need to scale the microsecond value. However we
515 * need to offset it - from the datasheet:
516 *
517 * "This register decides the asserting duration of wdt_ext and
518 * wdt_rstarm signal. The default value is 0xFF. It means the
519 * default asserting duration of wdt_ext and wdt_rstarm is
520 * 256us."
521 *
522 * This implies a value of 0 gives a 1us pulse.
523 */
524 writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
525 }
526
527 aspeed_wdt_update_bootstatus(pdev, wdt);
528
529 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
530 if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
531 if (of_device_is_compatible(np, "aspeed,ast2400-wdt") ||
532 of_device_is_compatible(np, "aspeed,ast2500-wdt"))
533 wdt->wdd.groups = bswitch_groups;
534 }
535
536 dev_set_drvdata(dev, wdt);
537
538 return devm_watchdog_register_device(dev, &wdt->wdd);
539 }
540
541 static struct platform_driver aspeed_watchdog_driver = {
542 .probe = aspeed_wdt_probe,
543 .driver = {
544 .name = KBUILD_MODNAME,
545 .of_match_table = aspeed_wdt_of_table,
546 },
547 };
548
aspeed_wdt_init(void)549 static int __init aspeed_wdt_init(void)
550 {
551 return platform_driver_register(&aspeed_watchdog_driver);
552 }
553 arch_initcall(aspeed_wdt_init);
554
aspeed_wdt_exit(void)555 static void __exit aspeed_wdt_exit(void)
556 {
557 platform_driver_unregister(&aspeed_watchdog_driver);
558 }
559 module_exit(aspeed_wdt_exit);
560
561 MODULE_DESCRIPTION("Aspeed Watchdog Driver");
562 MODULE_LICENSE("GPL");
563