1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPIVFIO_H 20 #define _UAPIVFIO_H 21 #include <linux/types.h> 22 #include <linux/ioctl.h> 23 #define VFIO_API_VERSION 0 24 #define VFIO_TYPE1_IOMMU 1 25 #define VFIO_SPAPR_TCE_IOMMU 2 26 #define VFIO_TYPE1v2_IOMMU 3 27 #define VFIO_DMA_CC_IOMMU 4 28 #define VFIO_EEH 5 29 #define VFIO_TYPE1_NESTING_IOMMU 6 30 #define VFIO_SPAPR_TCE_v2_IOMMU 7 31 #define VFIO_NOIOMMU_IOMMU 8 32 #define VFIO_TYPE (';') 33 #define VFIO_BASE 100 34 struct vfio_info_cap_header { 35 __u16 id; 36 __u16 version; 37 __u32 next; 38 }; 39 #define VFIO_GET_API_VERSION _IO(VFIO_TYPE, VFIO_BASE + 0) 40 #define VFIO_CHECK_EXTENSION _IO(VFIO_TYPE, VFIO_BASE + 1) 41 #define VFIO_SET_IOMMU _IO(VFIO_TYPE, VFIO_BASE + 2) 42 struct vfio_group_status { 43 __u32 argsz; 44 __u32 flags; 45 #define VFIO_GROUP_FLAGS_VIABLE (1 << 0) 46 #define VFIO_GROUP_FLAGS_CONTAINER_SET (1 << 1) 47 }; 48 #define VFIO_GROUP_GET_STATUS _IO(VFIO_TYPE, VFIO_BASE + 3) 49 #define VFIO_GROUP_SET_CONTAINER _IO(VFIO_TYPE, VFIO_BASE + 4) 50 #define VFIO_GROUP_UNSET_CONTAINER _IO(VFIO_TYPE, VFIO_BASE + 5) 51 #define VFIO_GROUP_GET_DEVICE_FD _IO(VFIO_TYPE, VFIO_BASE + 6) 52 struct vfio_device_info { 53 __u32 argsz; 54 __u32 flags; 55 #define VFIO_DEVICE_FLAGS_RESET (1 << 0) 56 #define VFIO_DEVICE_FLAGS_PCI (1 << 1) 57 #define VFIO_DEVICE_FLAGS_PLATFORM (1 << 2) 58 #define VFIO_DEVICE_FLAGS_AMBA (1 << 3) 59 #define VFIO_DEVICE_FLAGS_CCW (1 << 4) 60 #define VFIO_DEVICE_FLAGS_AP (1 << 5) 61 #define VFIO_DEVICE_FLAGS_FSL_MC (1 << 6) 62 #define VFIO_DEVICE_FLAGS_CAPS (1 << 7) 63 __u32 num_regions; 64 __u32 num_irqs; 65 __u32 cap_offset; 66 }; 67 #define VFIO_DEVICE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 7) 68 #define VFIO_DEVICE_API_PCI_STRING "vfio-pci" 69 #define VFIO_DEVICE_API_PLATFORM_STRING "vfio-platform" 70 #define VFIO_DEVICE_API_AMBA_STRING "vfio-amba" 71 #define VFIO_DEVICE_API_CCW_STRING "vfio-ccw" 72 #define VFIO_DEVICE_API_AP_STRING "vfio-ap" 73 #define VFIO_DEVICE_INFO_CAP_ZPCI_BASE 1 74 #define VFIO_DEVICE_INFO_CAP_ZPCI_GROUP 2 75 #define VFIO_DEVICE_INFO_CAP_ZPCI_UTIL 3 76 #define VFIO_DEVICE_INFO_CAP_ZPCI_PFIP 4 77 struct vfio_region_info { 78 __u32 argsz; 79 __u32 flags; 80 #define VFIO_REGION_INFO_FLAG_READ (1 << 0) 81 #define VFIO_REGION_INFO_FLAG_WRITE (1 << 1) 82 #define VFIO_REGION_INFO_FLAG_MMAP (1 << 2) 83 #define VFIO_REGION_INFO_FLAG_CAPS (1 << 3) 84 __u32 index; 85 __u32 cap_offset; 86 __u64 size; 87 __u64 offset; 88 }; 89 #define VFIO_DEVICE_GET_REGION_INFO _IO(VFIO_TYPE, VFIO_BASE + 8) 90 #define VFIO_REGION_INFO_CAP_SPARSE_MMAP 1 91 struct vfio_region_sparse_mmap_area { 92 __u64 offset; 93 __u64 size; 94 }; 95 struct vfio_region_info_cap_sparse_mmap { 96 struct vfio_info_cap_header header; 97 __u32 nr_areas; 98 __u32 reserved; 99 struct vfio_region_sparse_mmap_area areas[]; 100 }; 101 #define VFIO_REGION_INFO_CAP_TYPE 2 102 struct vfio_region_info_cap_type { 103 struct vfio_info_cap_header header; 104 __u32 type; 105 __u32 subtype; 106 }; 107 #define VFIO_REGION_TYPE_PCI_VENDOR_TYPE (1 << 31) 108 #define VFIO_REGION_TYPE_PCI_VENDOR_MASK (0xffff) 109 #define VFIO_REGION_TYPE_GFX (1) 110 #define VFIO_REGION_TYPE_CCW (2) 111 #define VFIO_REGION_TYPE_MIGRATION (3) 112 #define VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION (1) 113 #define VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG (2) 114 #define VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG (3) 115 #define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM (1) 116 #define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1) 117 #define VFIO_REGION_SUBTYPE_GFX_EDID (1) 118 struct vfio_region_gfx_edid { 119 __u32 edid_offset; 120 __u32 edid_max_size; 121 __u32 edid_size; 122 __u32 max_xres; 123 __u32 max_yres; 124 __u32 link_state; 125 #define VFIO_DEVICE_GFX_LINK_STATE_UP 1 126 #define VFIO_DEVICE_GFX_LINK_STATE_DOWN 2 127 }; 128 #define VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD (1) 129 #define VFIO_REGION_SUBTYPE_CCW_SCHIB (2) 130 #define VFIO_REGION_SUBTYPE_CCW_CRW (3) 131 #define VFIO_REGION_SUBTYPE_MIGRATION (1) 132 struct vfio_device_migration_info { 133 __u32 device_state; 134 #define VFIO_DEVICE_STATE_STOP (0) 135 #define VFIO_DEVICE_STATE_RUNNING (1 << 0) 136 #define VFIO_DEVICE_STATE_SAVING (1 << 1) 137 #define VFIO_DEVICE_STATE_RESUMING (1 << 2) 138 #define VFIO_DEVICE_STATE_MASK (VFIO_DEVICE_STATE_RUNNING | VFIO_DEVICE_STATE_SAVING | VFIO_DEVICE_STATE_RESUMING) 139 #define VFIO_DEVICE_STATE_VALID(state) (state & VFIO_DEVICE_STATE_RESUMING ? (state & VFIO_DEVICE_STATE_MASK) == VFIO_DEVICE_STATE_RESUMING : 1) 140 #define VFIO_DEVICE_STATE_IS_ERROR(state) ((state & VFIO_DEVICE_STATE_MASK) == (VFIO_DEVICE_STATE_SAVING | VFIO_DEVICE_STATE_RESUMING)) 141 #define VFIO_DEVICE_STATE_SET_ERROR(state) ((state & ~VFIO_DEVICE_STATE_MASK) | VFIO_DEVICE_SATE_SAVING | VFIO_DEVICE_STATE_RESUMING) 142 __u32 reserved; 143 __u64 pending_bytes; 144 __u64 data_offset; 145 __u64 data_size; 146 }; 147 #define VFIO_REGION_INFO_CAP_MSIX_MAPPABLE 3 148 #define VFIO_REGION_INFO_CAP_NVLINK2_SSATGT 4 149 struct vfio_region_info_cap_nvlink2_ssatgt { 150 struct vfio_info_cap_header header; 151 __u64 tgt; 152 }; 153 #define VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD 5 154 struct vfio_region_info_cap_nvlink2_lnkspd { 155 struct vfio_info_cap_header header; 156 __u32 link_speed; 157 __u32 __pad; 158 }; 159 struct vfio_irq_info { 160 __u32 argsz; 161 __u32 flags; 162 #define VFIO_IRQ_INFO_EVENTFD (1 << 0) 163 #define VFIO_IRQ_INFO_MASKABLE (1 << 1) 164 #define VFIO_IRQ_INFO_AUTOMASKED (1 << 2) 165 #define VFIO_IRQ_INFO_NORESIZE (1 << 3) 166 __u32 index; 167 __u32 count; 168 }; 169 #define VFIO_DEVICE_GET_IRQ_INFO _IO(VFIO_TYPE, VFIO_BASE + 9) 170 struct vfio_irq_set { 171 __u32 argsz; 172 __u32 flags; 173 #define VFIO_IRQ_SET_DATA_NONE (1 << 0) 174 #define VFIO_IRQ_SET_DATA_BOOL (1 << 1) 175 #define VFIO_IRQ_SET_DATA_EVENTFD (1 << 2) 176 #define VFIO_IRQ_SET_ACTION_MASK (1 << 3) 177 #define VFIO_IRQ_SET_ACTION_UNMASK (1 << 4) 178 #define VFIO_IRQ_SET_ACTION_TRIGGER (1 << 5) 179 __u32 index; 180 __u32 start; 181 __u32 count; 182 __u8 data[]; 183 }; 184 #define VFIO_DEVICE_SET_IRQS _IO(VFIO_TYPE, VFIO_BASE + 10) 185 #define VFIO_IRQ_SET_DATA_TYPE_MASK (VFIO_IRQ_SET_DATA_NONE | VFIO_IRQ_SET_DATA_BOOL | VFIO_IRQ_SET_DATA_EVENTFD) 186 #define VFIO_IRQ_SET_ACTION_TYPE_MASK (VFIO_IRQ_SET_ACTION_MASK | VFIO_IRQ_SET_ACTION_UNMASK | VFIO_IRQ_SET_ACTION_TRIGGER) 187 #define VFIO_DEVICE_RESET _IO(VFIO_TYPE, VFIO_BASE + 11) 188 enum { 189 VFIO_PCI_BAR0_REGION_INDEX, 190 VFIO_PCI_BAR1_REGION_INDEX, 191 VFIO_PCI_BAR2_REGION_INDEX, 192 VFIO_PCI_BAR3_REGION_INDEX, 193 VFIO_PCI_BAR4_REGION_INDEX, 194 VFIO_PCI_BAR5_REGION_INDEX, 195 VFIO_PCI_ROM_REGION_INDEX, 196 VFIO_PCI_CONFIG_REGION_INDEX, 197 VFIO_PCI_VGA_REGION_INDEX, 198 VFIO_PCI_NUM_REGIONS = 9 199 }; 200 enum { 201 VFIO_PCI_INTX_IRQ_INDEX, 202 VFIO_PCI_MSI_IRQ_INDEX, 203 VFIO_PCI_MSIX_IRQ_INDEX, 204 VFIO_PCI_ERR_IRQ_INDEX, 205 VFIO_PCI_REQ_IRQ_INDEX, 206 VFIO_PCI_NUM_IRQS 207 }; 208 enum { 209 VFIO_CCW_CONFIG_REGION_INDEX, 210 VFIO_CCW_NUM_REGIONS 211 }; 212 enum { 213 VFIO_CCW_IO_IRQ_INDEX, 214 VFIO_CCW_CRW_IRQ_INDEX, 215 VFIO_CCW_NUM_IRQS 216 }; 217 struct vfio_pci_dependent_device { 218 __u32 group_id; 219 __u16 segment; 220 __u8 bus; 221 __u8 devfn; 222 }; 223 struct vfio_pci_hot_reset_info { 224 __u32 argsz; 225 __u32 flags; 226 __u32 count; 227 struct vfio_pci_dependent_device devices[]; 228 }; 229 #define VFIO_DEVICE_GET_PCI_HOT_RESET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) 230 struct vfio_pci_hot_reset { 231 __u32 argsz; 232 __u32 flags; 233 __u32 count; 234 __s32 group_fds[]; 235 }; 236 #define VFIO_DEVICE_PCI_HOT_RESET _IO(VFIO_TYPE, VFIO_BASE + 13) 237 struct vfio_device_gfx_plane_info { 238 __u32 argsz; 239 __u32 flags; 240 #define VFIO_GFX_PLANE_TYPE_PROBE (1 << 0) 241 #define VFIO_GFX_PLANE_TYPE_DMABUF (1 << 1) 242 #define VFIO_GFX_PLANE_TYPE_REGION (1 << 2) 243 __u32 drm_plane_type; 244 __u32 drm_format; 245 __u64 drm_format_mod; 246 __u32 width; 247 __u32 height; 248 __u32 stride; 249 __u32 size; 250 __u32 x_pos; 251 __u32 y_pos; 252 __u32 x_hot; 253 __u32 y_hot; 254 union { 255 __u32 region_index; 256 __u32 dmabuf_id; 257 }; 258 }; 259 #define VFIO_DEVICE_QUERY_GFX_PLANE _IO(VFIO_TYPE, VFIO_BASE + 14) 260 #define VFIO_DEVICE_GET_GFX_DMABUF _IO(VFIO_TYPE, VFIO_BASE + 15) 261 struct vfio_device_ioeventfd { 262 __u32 argsz; 263 __u32 flags; 264 #define VFIO_DEVICE_IOEVENTFD_8 (1 << 0) 265 #define VFIO_DEVICE_IOEVENTFD_16 (1 << 1) 266 #define VFIO_DEVICE_IOEVENTFD_32 (1 << 2) 267 #define VFIO_DEVICE_IOEVENTFD_64 (1 << 3) 268 #define VFIO_DEVICE_IOEVENTFD_SIZE_MASK (0xf) 269 __u64 offset; 270 __u64 data; 271 __s32 fd; 272 }; 273 #define VFIO_DEVICE_IOEVENTFD _IO(VFIO_TYPE, VFIO_BASE + 16) 274 struct vfio_device_feature { 275 __u32 argsz; 276 __u32 flags; 277 #define VFIO_DEVICE_FEATURE_MASK (0xffff) 278 #define VFIO_DEVICE_FEATURE_GET (1 << 16) 279 #define VFIO_DEVICE_FEATURE_SET (1 << 17) 280 #define VFIO_DEVICE_FEATURE_PROBE (1 << 18) 281 __u8 data[]; 282 }; 283 #define VFIO_DEVICE_FEATURE _IO(VFIO_TYPE, VFIO_BASE + 17) 284 #define VFIO_DEVICE_FEATURE_PCI_VF_TOKEN (0) 285 struct vfio_iommu_type1_info { 286 __u32 argsz; 287 __u32 flags; 288 #define VFIO_IOMMU_INFO_PGSIZES (1 << 0) 289 #define VFIO_IOMMU_INFO_CAPS (1 << 1) 290 __u64 iova_pgsizes; 291 __u32 cap_offset; 292 }; 293 #define VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE 1 294 struct vfio_iova_range { 295 __u64 start; 296 __u64 end; 297 }; 298 struct vfio_iommu_type1_info_cap_iova_range { 299 struct vfio_info_cap_header header; 300 __u32 nr_iovas; 301 __u32 reserved; 302 struct vfio_iova_range iova_ranges[]; 303 }; 304 #define VFIO_IOMMU_TYPE1_INFO_CAP_MIGRATION 2 305 struct vfio_iommu_type1_info_cap_migration { 306 struct vfio_info_cap_header header; 307 __u32 flags; 308 __u64 pgsize_bitmap; 309 __u64 max_dirty_bitmap_size; 310 }; 311 #define VFIO_IOMMU_TYPE1_INFO_DMA_AVAIL 3 312 struct vfio_iommu_type1_info_dma_avail { 313 struct vfio_info_cap_header header; 314 __u32 avail; 315 }; 316 #define VFIO_IOMMU_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) 317 struct vfio_iommu_type1_dma_map { 318 __u32 argsz; 319 __u32 flags; 320 #define VFIO_DMA_MAP_FLAG_READ (1 << 0) 321 #define VFIO_DMA_MAP_FLAG_WRITE (1 << 1) 322 __u64 vaddr; 323 __u64 iova; 324 __u64 size; 325 }; 326 #define VFIO_IOMMU_MAP_DMA _IO(VFIO_TYPE, VFIO_BASE + 13) 327 struct vfio_bitmap { 328 __u64 pgsize; 329 __u64 size; 330 __u64 __user * data; 331 }; 332 struct vfio_iommu_type1_dma_unmap { 333 __u32 argsz; 334 __u32 flags; 335 #define VFIO_DMA_UNMAP_FLAG_GET_DIRTY_BITMAP (1 << 0) 336 __u64 iova; 337 __u64 size; 338 __u8 data[]; 339 }; 340 #define VFIO_IOMMU_UNMAP_DMA _IO(VFIO_TYPE, VFIO_BASE + 14) 341 #define VFIO_IOMMU_ENABLE _IO(VFIO_TYPE, VFIO_BASE + 15) 342 #define VFIO_IOMMU_DISABLE _IO(VFIO_TYPE, VFIO_BASE + 16) 343 struct vfio_iommu_type1_dirty_bitmap { 344 __u32 argsz; 345 __u32 flags; 346 #define VFIO_IOMMU_DIRTY_PAGES_FLAG_START (1 << 0) 347 #define VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP (1 << 1) 348 #define VFIO_IOMMU_DIRTY_PAGES_FLAG_GET_BITMAP (1 << 2) 349 __u8 data[]; 350 }; 351 struct vfio_iommu_type1_dirty_bitmap_get { 352 __u64 iova; 353 __u64 size; 354 struct vfio_bitmap bitmap; 355 }; 356 #define VFIO_IOMMU_DIRTY_PAGES _IO(VFIO_TYPE, VFIO_BASE + 17) 357 struct vfio_iommu_spapr_tce_ddw_info { 358 __u64 pgsizes; 359 __u32 max_dynamic_windows_supported; 360 __u32 levels; 361 }; 362 struct vfio_iommu_spapr_tce_info { 363 __u32 argsz; 364 __u32 flags; 365 #define VFIO_IOMMU_SPAPR_INFO_DDW (1 << 0) 366 __u32 dma32_window_start; 367 __u32 dma32_window_size; 368 struct vfio_iommu_spapr_tce_ddw_info ddw; 369 }; 370 #define VFIO_IOMMU_SPAPR_TCE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) 371 struct vfio_eeh_pe_err { 372 __u32 type; 373 __u32 func; 374 __u64 addr; 375 __u64 mask; 376 }; 377 struct vfio_eeh_pe_op { 378 __u32 argsz; 379 __u32 flags; 380 __u32 op; 381 union { 382 struct vfio_eeh_pe_err err; 383 }; 384 }; 385 #define VFIO_EEH_PE_DISABLE 0 386 #define VFIO_EEH_PE_ENABLE 1 387 #define VFIO_EEH_PE_UNFREEZE_IO 2 388 #define VFIO_EEH_PE_UNFREEZE_DMA 3 389 #define VFIO_EEH_PE_GET_STATE 4 390 #define VFIO_EEH_PE_STATE_NORMAL 0 391 #define VFIO_EEH_PE_STATE_RESET 1 392 #define VFIO_EEH_PE_STATE_STOPPED 2 393 #define VFIO_EEH_PE_STATE_STOPPED_DMA 4 394 #define VFIO_EEH_PE_STATE_UNAVAIL 5 395 #define VFIO_EEH_PE_RESET_DEACTIVATE 5 396 #define VFIO_EEH_PE_RESET_HOT 6 397 #define VFIO_EEH_PE_RESET_FUNDAMENTAL 7 398 #define VFIO_EEH_PE_CONFIGURE 8 399 #define VFIO_EEH_PE_INJECT_ERR 9 400 #define VFIO_EEH_PE_OP _IO(VFIO_TYPE, VFIO_BASE + 21) 401 struct vfio_iommu_spapr_register_memory { 402 __u32 argsz; 403 __u32 flags; 404 __u64 vaddr; 405 __u64 size; 406 }; 407 #define VFIO_IOMMU_SPAPR_REGISTER_MEMORY _IO(VFIO_TYPE, VFIO_BASE + 17) 408 #define VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY _IO(VFIO_TYPE, VFIO_BASE + 18) 409 struct vfio_iommu_spapr_tce_create { 410 __u32 argsz; 411 __u32 flags; 412 __u32 page_shift; 413 __u32 __resv1; 414 __u64 window_size; 415 __u32 levels; 416 __u32 __resv2; 417 __u64 start_addr; 418 }; 419 #define VFIO_IOMMU_SPAPR_TCE_CREATE _IO(VFIO_TYPE, VFIO_BASE + 19) 420 struct vfio_iommu_spapr_tce_remove { 421 __u32 argsz; 422 __u32 flags; 423 __u64 start_addr; 424 }; 425 #define VFIO_IOMMU_SPAPR_TCE_REMOVE _IO(VFIO_TYPE, VFIO_BASE + 20) 426 #endif 427