1; 2; Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3; Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 4; 5; Redistribution and use in source and binary forms, with or without modification, 6; are permitted provided that the following conditions are met: 7; 8; 1. Redistributions of source code must retain the above copyright notice, this list of 9; conditions and the following disclaimer. 10; 11; 2. Redistributions in binary form must reproduce the above copyright notice, this list 12; of conditions and the following disclaimer in the documentation and/or other materials 13; provided with the distribution. 14; 15; 3. Neither the name of the copyright holder nor the names of its contributors may be used 16; to endorse or promote products derived from this software without specific prior written 17; permission. 18; 19; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30; 31 32 PRESERVE8 33 ; SECTION .text:CODE(2) 34 AREA |.text|, CODE, READONLY 35 THUMB 36 37 EXPORT HalExcNMI 38 EXPORT HalExcHardFault 39 EXPORT HalExcMemFault 40 EXPORT HalExcBusFault 41 EXPORT HalExcUsageFault 42 EXPORT HalExcSvcCall 43 44 IMPORT HalExcHandleEntry 45 IMPORT g_uwExcTbl 46 IMPORT g_taskScheduled 47 48OS_FLG_BGD_ACTIVE EQU 0x0002 49 50OS_EXC_CAUSE_NMI EQU 16 51OS_EXC_CAUSE_HARDFAULT EQU 17 52 53HF_DEBUGEVT EQU 20 54HF_VECTBL EQU 21 55 56FLAG_ADDR_VALID EQU 0x10000 57FLAG_HWI_ACTIVE EQU 0x20000 58FLAG_NO_FLOAT EQU 0x10000000 59 60OS_NVIC_FSR EQU 0xE000ED28 ;include BusFault/MemFault/UsageFault State Register 61OS_NVIC_HFSR EQU 0xE000ED2C ;HardFault State Register 62OS_NVIC_BFAR EQU 0xE000ED38 63OS_NVIC_MMAR EQU 0xE000ED34 64OS_NVIC_ACT_BASE EQU 0xE000E300 65OS_NVIC_SHCSRS EQU 0xE000ED24 66OS_NVIC_SHCSR_MASK EQU 0xC00 67 68HalExcNMI 69 MOV R0, #OS_EXC_CAUSE_NMI 70 MOV R1, #0 71 B osExcDispatch 72 73HalExcHardFault 74 MOV R0, #OS_EXC_CAUSE_HARDFAULT 75 LDR R2, =OS_NVIC_HFSR 76 LDR R2, [R2] 77 78 MOV R1, #HF_DEBUGEVT 79 ORR R0, R0, R1, LSL #0x8 80 TST R2, #0x80000000 81 BNE osExcDispatch ; DEBUGEVT 82 83 AND R0, R0 , #0x000000FF 84 MOV R1, #HF_VECTBL 85 ORR R0, R0, R1, LSL #0x8 86 TST R2, #0x00000002 87 BNE osExcDispatch ; VECTBL 88 89 ;if not DEBUGEVT and VECTBL then is FORCED 90 AND R0, R0, #0x000000FF 91 92 LDR R2, =OS_NVIC_FSR 93 LDR R2, [R2] 94 95 TST R2, #0x8000 ; BFARVALID 96 BNE _HFBusFault ; BusFault 97 98 TST R2, #0x80 ; MMARVALID 99 BNE _HFMemFault ; MemFault 100 101 MOV R12,#0 102 B osHFExcCommonBMU 103 104_HFBusFault 105 LDR R1, =OS_NVIC_BFAR 106 LDR R1, [R1] 107 MOV R12, #FLAG_ADDR_VALID 108 B osHFExcCommonBMU 109 110_HFMemFault 111 LDR R1, =OS_NVIC_MMAR 112 LDR R1, [R1] 113 MOV R12, #FLAG_ADDR_VALID 114 115osHFExcCommonBMU 116 CLZ R2, R2 117 LDR R3, =g_uwExcTbl 118 ADD R3, R3, R2 119 LDRB R2, [R3] 120 ORR R0, R0, R2, LSL #0x8 121 ORR R0, R0 ,R12 122 B osExcDispatch 123 124HalExcSvcCall 125 TST LR, #0x4 126 ITE EQ 127 MRSEQ R0, MSP 128 MRSNE R0, PSP 129 LDR R1, [R0,#24] 130 LDRB R0, [R1,#-2] 131 MOV R1, #0 132 B osExcDispatch 133 134HalExcBusFault 135 LDR R0, =OS_NVIC_FSR 136 LDR R0, [R0] 137 138 TST R0, #0x8000 ; BFARVALID 139 BEQ _ExcBusNoADDR 140 LDR R1, =OS_NVIC_BFAR 141 LDR R1, [R1] 142 MOV R12, #FLAG_ADDR_VALID 143 AND R0, R0, #0x1F00 144 145 B osExcCommonBMU 146 147_ExcBusNoADDR 148 MOV R12,#0 149 B osExcCommonBMU 150 151HalExcMemFault 152 LDR R0, =OS_NVIC_FSR 153 LDR R0, [R0] 154 155 TST R0, #0x80 ; MMARVALID 156 BEQ _ExcMemNoADDR 157 LDR R1, =OS_NVIC_MMAR 158 LDR R1, [R1] 159 MOV R12, #FLAG_ADDR_VALID 160 AND R0, R0, #0x1B 161 162 B osExcCommonBMU 163 164_ExcMemNoADDR 165 MOV R12,#0 166 B osExcCommonBMU 167 168HalExcUsageFault 169 LDR R0, =OS_NVIC_FSR 170 LDR R0, [R0] 171 172 MOV R1, #0x030F 173 LSL R1, R1, #16 174 AND R0, R0, R1 175 MOV R12, #0 176 177osExcCommonBMU 178 CLZ R0, R0 179 LDR R3, =g_uwExcTbl 180 ADD R3, R3, R0 181 LDRB R0, [R3] 182 ORR R0, R0, R12 183 184; R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid), R1 -- EXCADDR 185osExcDispatch 186 LDR R2, =OS_NVIC_ACT_BASE 187 MOV R12, #8 ; R12 is hwi check loop counter 188 189_hwiActiveCheck 190 LDR R3, [R2] ; R3 store active hwi register when exc 191 CMP R3, #0 192 BEQ _hwiActiveCheckNext 193 194 ; exc occurred in IRQ 195 ORR R0, R0, #FLAG_HWI_ACTIVE 196 RBIT R2, R3 197 CLZ R2, R2 198 AND R12, R12, #1 199 ADD R2, R2, R12, LSL #5 ; calculate R2 (hwi number) as pid 200 201_ExcInMSP 202 CMP LR, #0xFFFFFFE9 203 BNE _NoFloatInMsp 204 ADD R3, R13, #104 205 PUSH {R3} 206 MRS R12, PRIMASK ; store message-->exc: disable int? 207 PUSH {R4-R12} ; store message-->exc: {R4-R12} 208 VPUSH {D8-D15} 209 B _handleEntry 210 211_NoFloatInMsp 212 ADD R3, R13, #32 213 PUSH {R3} ; save IRQ SP ; store message-->exc: MSP(R13) 214 215 MRS R12, PRIMASK ; store message-->exc: disable int? 216 PUSH {R4-R12} ; store message-->exc: {R4-R12} 217 ORR R0, R0, #FLAG_NO_FLOAT 218 B _handleEntry 219 220_hwiActiveCheckNext 221 ADD R2, R2, #4 ; next NVIC ACT ADDR 222 SUBS R12, R12, #1 223 BNE _hwiActiveCheck 224 225 ;/*NMI interrupt excption*/ 226 LDR R2, =OS_NVIC_SHCSRS 227 LDRH R2,[R2] 228 LDR R3,=OS_NVIC_SHCSR_MASK 229 AND R2, R2,R3 230 CMP R2,#0 231 BNE _ExcInMSP 232 ; exc occurred in Task or Init or exc 233 ; reserved for register info from task stack 234 235 LDR R2, =g_taskScheduled 236 LDR R2, [R2] 237 TST R2, #1 ; OS_FLG_BGD_ACTIVE 238 BEQ _ExcInMSP ; if exc occurred in Init then branch 239 240 241 CMP LR, #0xFFFFFFED ;auto push floating registers 242 BNE _NoFloatInPsp 243 244 ; exc occurred in Task 245 MOV R2, R13 246 SUB R13, #96 ; add 8 Bytes reg(for STMFD) 247 248 MRS R3, PSP 249 ADD R12, R3, #104 250 PUSH {R12} ; save task SP 251 252 MRS R12, PRIMASK 253 PUSH {R4-R12} 254 VPUSH {D8-D15} 255 256 ; copy auto saved task register 257 258 LDMFD R3!, {R4-R11} ; R4-R11 store PSP reg(auto push when exc in task) 259 VLDMIA R3!, {D8-D15} 260 VSTMDB R2!, {D8-D15} 261 STMFD R2!, {R4-R11} 262 B _handleEntry 263 264_NoFloatInPsp 265 MOV R2, R13 ;no auto push floating registers 266 SUB R13, #32 ; add 8 Bytes reg(for STMFD) 267 268 MRS R3, PSP 269 ADD R12, R3, #32 270 PUSH {R12} ; save task SP 271 272 MRS R12, PRIMASK 273 PUSH {R4-R12} 274 275 LDMFD R3, {R4-R11} ; R4-R11 store PSP reg(auto push when exc in task) 276 STMFD R2!, {R4-R11} 277 ORR R0, R0, #FLAG_NO_FLOAT 278 279_handleEntry 280 MOV R3, R13 ; R13:the 4th param 281 CPSID I 282 CPSID F 283 B HalExcHandleEntry 284 285 NOP 286 END 287