1 #include <stdio.h>
2 #include <stdlib.h>
3 #include <unistd.h>
4 #include <sys/types.h>
5 #include <sys/stat.h>
6 #include <string.h>
7
8 #include "CUnit/Basic.h"
9 #include "amdgpu_test.h"
10 #include "shader_code.h"
11
12 #define PACKET3_DISPATCH_DIRECT 0x15
13 #define PACKET3_CONTEXT_CONTROL 0x28
14 #define PACKET3_DRAW_INDEX_AUTO 0x2D
15 #define PACKET3_SET_CONTEXT_REG 0x69
16 #define PACKET3_SET_SH_REG 0x76
17 #define PACKET3_SET_SH_REG_OFFSET 0x77
18 #define PACKET3_SET_UCONFIG_REG 0x79
19 #define PACKET3_SET_SH_REG_INDEX 0x9B
20
21 #define PACKET_TYPE3 3
22 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
23 (((op) & 0xFF) << 8) | \
24 ((n) & 0x3FFF) << 16)
25 #define PACKET3_COMPUTE(op, n) PACKET3(op, n) | (1 << 1)
26
27
28 struct shader_test_bo {
29 amdgpu_bo_handle bo;
30 unsigned size;
31 unsigned heap;
32 void *ptr;
33 uint64_t mc_address;
34 amdgpu_va_handle va;
35 };
36
37 struct shader_test_draw {
38 struct shader_test_bo ps_bo;
39 enum ps_type ps_type;
40 struct shader_test_bo vs_bo;
41 enum vs_type vs_type;
42 };
43 struct shader_test_dispatch {
44 struct shader_test_bo cs_bo;
45 enum cs_type cs_type;
46 };
47
48 struct shader_test_info {
49 amdgpu_device_handle device_handle;
50 enum amdgpu_test_gfx_version version;
51 unsigned ip;
52 unsigned ring;
53 int hang;
54 int hang_slow;
55 };
56
57 struct shader_test_priv {
58 const struct shader_test_info *info;
59 unsigned cmd_curr;
60
61 union {
62 struct shader_test_draw shader_draw;
63 struct shader_test_dispatch shader_dispatch;
64 };
65 struct shader_test_bo vtx_attributes_mem;
66 struct shader_test_bo cmd;
67 struct shader_test_bo src;
68 struct shader_test_bo dst;
69 };
70
shader_test_bo_alloc(amdgpu_device_handle device_handle,struct shader_test_bo * shader_test_bo)71 static int shader_test_bo_alloc(amdgpu_device_handle device_handle,
72 struct shader_test_bo *shader_test_bo)
73 {
74 return amdgpu_bo_alloc_and_map(device_handle, shader_test_bo->size, 4096,
75 shader_test_bo->heap, 0,
76 &(shader_test_bo->bo), (void **)&(shader_test_bo->ptr),
77 &(shader_test_bo->mc_address), &(shader_test_bo->va));
78 }
79
shader_test_bo_free(struct shader_test_bo * shader_test_bo)80 static int shader_test_bo_free(struct shader_test_bo *shader_test_bo)
81 {
82 return amdgpu_bo_unmap_and_free(shader_test_bo->bo, shader_test_bo->va,
83 shader_test_bo->mc_address,
84 shader_test_bo->size);
85 }
86
shader_test_for_each(amdgpu_device_handle device_handle,unsigned ip,void (* fn)(struct shader_test_info * test_info))87 void shader_test_for_each(amdgpu_device_handle device_handle, unsigned ip,
88 void (*fn)(struct shader_test_info *test_info))
89 {
90 int r;
91 uint32_t ring_id;
92 struct shader_test_info test_info = {0};
93 struct drm_amdgpu_info_hw_ip info = {0};
94
95 r = amdgpu_query_hw_ip_info(device_handle, ip, 0, &info);
96 CU_ASSERT_EQUAL(r, 0);
97 if (!info.available_rings) {
98 printf("SKIP ... as there's no %s ring\n",
99 (ip == AMDGPU_HW_IP_GFX) ? "graphics": "compute");
100 return;
101 }
102
103 switch (info.hw_ip_version_major) {
104 case 9:
105 test_info.version = AMDGPU_TEST_GFX_V9;
106 break;
107 case 10:
108 test_info.version = AMDGPU_TEST_GFX_V10;
109 break;
110 case 11:
111 test_info.version = AMDGPU_TEST_GFX_V11;
112 break;
113 default:
114 printf("SKIP ... unsupported gfx version %d\n", info.hw_ip_version_major);
115 return;
116 }
117
118 test_info.device_handle = device_handle;
119 test_info.ip = ip;
120
121 printf("\n");
122 for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
123 printf("%s ring %d\n", (ip == AMDGPU_HW_IP_GFX) ? "graphics": "compute",
124 ring_id);
125 test_info.ring = ring_id;
126 fn(&test_info);
127 }
128 }
129
write_context_control(struct shader_test_priv * test_priv)130 static void write_context_control(struct shader_test_priv *test_priv)
131 {
132 int i = test_priv->cmd_curr;
133 uint32_t *ptr = test_priv->cmd.ptr;
134
135 if (test_priv->info->ip == AMDGPU_HW_IP_GFX) {
136 ptr[i++] = PACKET3(PACKET3_CONTEXT_CONTROL, 1);
137 ptr[i++] = 0x80000000;
138 ptr[i++] = 0x80000000;
139 }
140
141 test_priv->cmd_curr = i;
142 }
143
shader_test_load_shader_hang_slow(struct shader_test_bo * shader_bo,struct shader_test_shader_bin * shader_bin)144 static void shader_test_load_shader_hang_slow(struct shader_test_bo *shader_bo,
145 struct shader_test_shader_bin *shader_bin)
146 {
147 int i, j, loop;
148
149 loop = (shader_bo->size / sizeof(uint32_t) - shader_bin->header_length
150 - shader_bin->foot_length) / shader_bin->body_length;
151
152 memcpy(shader_bo->ptr, shader_bin->shader, shader_bin->header_length * sizeof(uint32_t));
153
154 j = shader_bin->header_length;
155 for (i = 0; i < loop; i++) {
156 memcpy(shader_bo->ptr + j,
157 shader_bin->shader + shader_bin->header_length,
158 shader_bin->body_length * sizeof(uint32_t));
159 j += shader_bin->body_length;
160 }
161
162 memcpy(shader_bo->ptr + j,
163 shader_bin->shader + shader_bin->header_length + shader_bin->body_length,
164 shader_bin->foot_length * sizeof(uint32_t));
165 }
166
amdgpu_dispatch_load_cs_shader_hang_slow(struct shader_test_priv * test_priv)167 static void amdgpu_dispatch_load_cs_shader_hang_slow(struct shader_test_priv *test_priv)
168 {
169 struct amdgpu_gpu_info gpu_info = {0};
170 struct shader_test_shader_bin *cs_shader_bin;
171 int r;
172
173 r = amdgpu_query_gpu_info(test_priv->info->device_handle, &gpu_info);
174 CU_ASSERT_EQUAL(r, 0);
175
176 switch (gpu_info.family_id) {
177 case AMDGPU_FAMILY_AI:
178 cs_shader_bin = &memcpy_cs_hang_slow_ai;
179 break;
180 case AMDGPU_FAMILY_RV:
181 cs_shader_bin = &memcpy_cs_hang_slow_rv;
182 break;
183 default:
184 cs_shader_bin = &memcpy_cs_hang_slow_nv;
185 break;
186 }
187
188 shader_test_load_shader_hang_slow(&test_priv->shader_dispatch.cs_bo, cs_shader_bin);
189 }
190
amdgpu_dispatch_load_cs_shader(struct shader_test_priv * test_priv)191 static void amdgpu_dispatch_load_cs_shader(struct shader_test_priv *test_priv)
192 {
193 if (test_priv->info->hang) {
194 if (test_priv->info->hang_slow)
195 amdgpu_dispatch_load_cs_shader_hang_slow(test_priv);
196 else
197 memcpy(test_priv->shader_dispatch.cs_bo.ptr, memcpy_shader_hang,
198 sizeof(memcpy_shader_hang));
199 } else {
200 memcpy(test_priv->shader_dispatch.cs_bo.ptr,
201 shader_test_cs[test_priv->info->version][test_priv->shader_dispatch.cs_type].shader,
202 shader_test_cs[test_priv->info->version][test_priv->shader_dispatch.cs_type].shader_size);
203 }
204 }
205
amdgpu_dispatch_init_gfx9(struct shader_test_priv * test_priv)206 static void amdgpu_dispatch_init_gfx9(struct shader_test_priv *test_priv)
207 {
208 int i;
209 uint32_t *ptr = test_priv->cmd.ptr;
210
211 /* Write context control and load shadowing register if necessary */
212 write_context_control(test_priv);
213
214 i = test_priv->cmd_curr;
215
216 /* Issue commands to set default compute state. */
217 /* clear mmCOMPUTE_START_Z - mmCOMPUTE_START_X */
218 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 3);
219 ptr[i++] = 0x204;
220 i += 3;
221
222 /* clear mmCOMPUTE_TMPRING_SIZE */
223 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1);
224 ptr[i++] = 0x218;
225 ptr[i++] = 0;
226
227 test_priv->cmd_curr = i;
228 }
229
amdgpu_dispatch_init_gfx10(struct shader_test_priv * test_priv)230 static void amdgpu_dispatch_init_gfx10(struct shader_test_priv *test_priv)
231 {
232 int i;
233 uint32_t *ptr = test_priv->cmd.ptr;
234
235 amdgpu_dispatch_init_gfx9(test_priv);
236
237 i = test_priv->cmd_curr;
238
239 /* mmCOMPUTE_SHADER_CHKSUM */
240 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1);
241 ptr[i++] = 0x22a;
242 ptr[i++] = 0;
243 /* mmCOMPUTE_REQ_CTRL */
244 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 6);
245 ptr[i++] = 0x222;
246 i += 6;
247 /* mmCP_COHER_START_DELAY */
248 ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
249 ptr[i++] = 0x7b;
250 ptr[i++] = 0x20;
251
252 test_priv->cmd_curr = i;
253 }
254
amdgpu_dispatch_init_gfx11(struct shader_test_priv * test_priv)255 static void amdgpu_dispatch_init_gfx11(struct shader_test_priv *test_priv)
256 {
257 int i;
258 uint32_t *ptr = test_priv->cmd.ptr;
259
260 /* Write context control and load shadowing register if necessary */
261 write_context_control(test_priv);
262
263 i = test_priv->cmd_curr;
264
265 /* Issue commands to set default compute state. */
266 /* clear mmCOMPUTE_START_Z - mmCOMPUTE_START_X */
267 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 3);
268 ptr[i++] = 0x204;
269 i += 3;
270
271 /* clear mmCOMPUTE_TMPRING_SIZE */
272 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1);
273 ptr[i++] = 0x218;
274 ptr[i++] = 0;
275
276 /* mmCOMPUTE_REQ_CTRL */
277 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1);
278 ptr[i++] = 0x222;
279 ptr[i++] = 0;
280
281 /* mmCOMPUTE_USER_ACCUM_0 .. 3*/
282 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
283 ptr[i++] = 0x224;
284 i += 4;
285
286 /* mmCOMPUTE_SHADER_CHKSUM */
287 ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
288 ptr[i++] = 0x22a;
289 ptr[i++] = 0;
290
291 test_priv->cmd_curr = i;
292 }
293
amdgpu_dispatch_init(struct shader_test_priv * test_priv)294 static void amdgpu_dispatch_init(struct shader_test_priv *test_priv)
295 {
296 switch (test_priv->info->version) {
297 case AMDGPU_TEST_GFX_V9:
298 amdgpu_dispatch_init_gfx9(test_priv);
299 break;
300 case AMDGPU_TEST_GFX_V10:
301 amdgpu_dispatch_init_gfx10(test_priv);
302 break;
303 case AMDGPU_TEST_GFX_V11:
304 amdgpu_dispatch_init_gfx11(test_priv);
305 break;
306 }
307 }
308
amdgpu_dispatch_write_cumask(struct shader_test_priv * test_priv)309 static void amdgpu_dispatch_write_cumask(struct shader_test_priv *test_priv)
310 {
311 int i = test_priv->cmd_curr;
312 uint32_t *ptr = test_priv->cmd.ptr;
313
314 /* Issue commands to set cu mask used in current dispatch */
315 switch (test_priv->info->version) {
316 case AMDGPU_TEST_GFX_V9:
317 /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE1 - mmCOMPUTE_STATIC_THREAD_MGMT_SE0 */
318 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 2);
319 ptr[i++] = 0x216;
320 ptr[i++] = 0xffffffff;
321 ptr[i++] = 0xffffffff;
322 /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE3 - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 */
323 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 2);
324 ptr[i++] = 0x219;
325 ptr[i++] = 0xffffffff;
326 ptr[i++] = 0xffffffff;
327 break;
328 case AMDGPU_TEST_GFX_V10:
329 case AMDGPU_TEST_GFX_V11:
330 /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE1 - mmCOMPUTE_STATIC_THREAD_MGMT_SE0 */
331 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG_INDEX, 2);
332 ptr[i++] = 0x30000216;
333 ptr[i++] = 0xffffffff;
334 ptr[i++] = 0xffffffff;
335 /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE3 - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 */
336 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG_INDEX, 2);
337 ptr[i++] = 0x30000219;
338 ptr[i++] = 0xffffffff;
339 ptr[i++] = 0xffffffff;
340 break;
341 }
342
343 test_priv->cmd_curr = i;
344 }
345
amdgpu_dispatch_write2hw_gfx9(struct shader_test_priv * test_priv)346 static void amdgpu_dispatch_write2hw_gfx9(struct shader_test_priv *test_priv)
347 {
348 const struct shader_test_cs_shader *cs_shader = &shader_test_cs[test_priv->info->version][test_priv->shader_dispatch.cs_type];
349 int j, i = test_priv->cmd_curr;
350 uint32_t *ptr = test_priv->cmd.ptr;
351 uint64_t shader_addr = test_priv->shader_dispatch.cs_bo.mc_address;
352
353 /* Writes shader state to HW */
354 /* set mmCOMPUTE_PGM_HI - mmCOMPUTE_PGM_LO */
355 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 2);
356 ptr[i++] = 0x20c;
357 ptr[i++] = (shader_addr >> 8);
358 ptr[i++] = (shader_addr >> 40);
359 /* write sh regs*/
360 for (j = 0; j < cs_shader->num_sh_reg; j++) {
361 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1);
362 /* - Gfx9ShRegBase */
363 ptr[i++] = cs_shader->sh_reg[j].reg_offset - shader_test_gfx_info[test_priv->info->version].sh_reg_base;
364 ptr[i++] = cs_shader->sh_reg[j].reg_value;
365 }
366
367 /* Write constant data */
368 if (CS_BUFFERCLEAR == test_priv->shader_dispatch.cs_type) {
369 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
370 ptr[i++] = 0x240;
371 ptr[i++] = test_priv->dst.mc_address;
372 ptr[i++] = (test_priv->dst.mc_address >> 32) | 0x100000;
373 ptr[i++] = test_priv->dst.size / 16;
374 ptr[i++] = 0x74fac;
375
376 /* Sets a range of pixel shader constants */
377 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
378 ptr[i++] = 0x244;
379 ptr[i++] = 0x22222222;
380 ptr[i++] = 0x22222222;
381 ptr[i++] = 0x22222222;
382 ptr[i++] = 0x22222222;
383 } else {
384 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
385 ptr[i++] = 0x240;
386 ptr[i++] = test_priv->src.mc_address;
387 ptr[i++] = (test_priv->src.mc_address >> 32) | 0x100000;
388 ptr[i++] = test_priv->src.size / 16;
389 ptr[i++] = 0x74fac;
390
391 /* Writes the UAV constant data to the SGPRs. */
392 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
393 ptr[i++] = 0x244;
394 ptr[i++] = test_priv->dst.mc_address;
395 ptr[i++] = (test_priv->dst.mc_address >> 32) | 0x100000;
396 ptr[i++] = test_priv->dst.size / 16;
397 ptr[i++] = 0x74fac;
398 }
399
400 test_priv->cmd_curr = i;
401 }
402
amdgpu_dispatch_write2hw_gfx10(struct shader_test_priv * test_priv)403 static void amdgpu_dispatch_write2hw_gfx10(struct shader_test_priv *test_priv)
404 {
405 int i = test_priv->cmd_curr;
406 uint32_t *ptr = test_priv->cmd.ptr;
407 const struct shader_test_cs_shader *cs_shader = &shader_test_cs[test_priv->info->version][test_priv->shader_dispatch.cs_type];
408 int j;
409 uint64_t shader_addr = test_priv->shader_dispatch.cs_bo.mc_address;
410
411 /* Writes shader state to HW */
412 /* set mmCOMPUTE_PGM_HI - mmCOMPUTE_PGM_LO */
413 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 2);
414 ptr[i++] = 0x20c;
415 ptr[i++] = (shader_addr >> 8);
416 ptr[i++] = (shader_addr >> 40);
417 /* write sh regs*/
418 for (j = 0; j < cs_shader->num_sh_reg; j++) {
419 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1);
420 /* - Gfx9ShRegBase */
421 ptr[i++] = cs_shader->sh_reg[j].reg_offset - shader_test_gfx_info[test_priv->info->version].sh_reg_base;
422 ptr[i++] = cs_shader->sh_reg[j].reg_value;
423 }
424
425 /* mmCOMPUTE_PGM_RSRC3 */
426 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1);
427 ptr[i++] = 0x228;
428 ptr[i++] = 0;
429
430 if (CS_BUFFERCLEAR == test_priv->shader_dispatch.cs_type) {
431 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
432 ptr[i++] = 0x240;
433 ptr[i++] = test_priv->dst.mc_address;
434 ptr[i++] = (test_priv->dst.mc_address >> 32) | 0x100000;
435 ptr[i++] = test_priv->dst.size / 16;
436 ptr[i++] = 0x1104bfac;
437
438 /* Sets a range of pixel shader constants */
439 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
440 ptr[i++] = 0x244;
441 ptr[i++] = 0x22222222;
442 ptr[i++] = 0x22222222;
443 ptr[i++] = 0x22222222;
444 ptr[i++] = 0x22222222;
445 } else {
446 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
447 ptr[i++] = 0x240;
448 ptr[i++] = test_priv->src.mc_address;
449 ptr[i++] = (test_priv->src.mc_address >> 32) | 0x100000;
450 ptr[i++] = test_priv->src.size / 16;
451 ptr[i++] = 0x1104bfac;
452
453 /* Writes the UAV constant data to the SGPRs. */
454 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
455 ptr[i++] = 0x244;
456 ptr[i++] = test_priv->dst.mc_address;
457 ptr[i++] = (test_priv->dst.mc_address>> 32) | 0x100000;
458 ptr[i++] = test_priv->dst.size / 16;
459 ptr[i++] = 0x1104bfac;
460 }
461
462 test_priv->cmd_curr = i;
463 }
464
amdgpu_dispatch_write2hw_gfx11(struct shader_test_priv * test_priv)465 static void amdgpu_dispatch_write2hw_gfx11(struct shader_test_priv *test_priv)
466 {
467 enum amdgpu_test_gfx_version version = test_priv->info->version;
468 const struct shader_test_cs_shader *cs_shader = &shader_test_cs[version][test_priv->shader_dispatch.cs_type];
469 int j, i = test_priv->cmd_curr;
470 uint32_t *ptr = test_priv->cmd.ptr;
471 uint64_t shader_addr = test_priv->shader_dispatch.cs_bo.mc_address;
472
473 /* Writes shader state to HW */
474 /* set mmCOMPUTE_PGM_HI - mmCOMPUTE_PGM_LO */
475 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 2);
476 ptr[i++] = 0x20c;
477 ptr[i++] = (shader_addr >> 8);
478 ptr[i++] = (shader_addr >> 40);
479
480 /* write sh regs*/
481 for (j = 0; j < cs_shader->num_sh_reg; j++) {
482 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1);
483 /* - Gfx9ShRegBase */
484 ptr[i++] = cs_shader->sh_reg[j].reg_offset - shader_test_gfx_info[version].sh_reg_base;
485 ptr[i++] = cs_shader->sh_reg[j].reg_value;
486 if (cs_shader->sh_reg[j].reg_offset == 0x2E12)
487 ptr[i-1] &= ~(1<<29);
488 }
489
490 /* mmCOMPUTE_PGM_RSRC3 */
491 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1);
492 ptr[i++] = 0x228;
493 ptr[i++] = 0x3f0;
494
495 /* Write constant data */
496 /* Writes the texture resource constants data to the SGPRs */
497 if (CS_BUFFERCLEAR == test_priv->shader_dispatch.cs_type) {
498 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
499 ptr[i++] = 0x240;
500 ptr[i++] = test_priv->dst.mc_address;
501 ptr[i++] = (test_priv->dst.mc_address >> 32) | 0x100000;
502 ptr[i++] = test_priv->dst.size / 16;
503 ptr[i++] = 0x1003dfac;
504
505 /* Sets a range of pixel shader constants */
506 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
507 ptr[i++] = 0x244;
508 ptr[i++] = 0x22222222;
509 ptr[i++] = 0x22222222;
510 ptr[i++] = 0x22222222;
511 ptr[i++] = 0x22222222;
512 } else {
513 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
514 ptr[i++] = 0x240;
515 ptr[i++] = test_priv->src.mc_address;
516 ptr[i++] = (test_priv->src.mc_address >> 32) | 0x100000;
517 ptr[i++] = test_priv->src.size / 16;
518 ptr[i++] = 0x1003dfac;
519
520 /* Writes the UAV constant data to the SGPRs. */
521 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
522 ptr[i++] = 0x244;
523 ptr[i++] = test_priv->dst.mc_address;
524 ptr[i++] = (test_priv->dst.mc_address>> 32) | 0x100000;
525 ptr[i++] = test_priv->dst.size / 16;
526 ptr[i++] = 0x1003dfac;
527 }
528
529 test_priv->cmd_curr = i;
530 }
531
amdgpu_dispatch_write2hw(struct shader_test_priv * test_priv)532 static void amdgpu_dispatch_write2hw(struct shader_test_priv *test_priv)
533 {
534 switch (test_priv->info->version) {
535 case AMDGPU_TEST_GFX_V9:
536 amdgpu_dispatch_write2hw_gfx9(test_priv);
537 break;
538 case AMDGPU_TEST_GFX_V10:
539 amdgpu_dispatch_write2hw_gfx10(test_priv);
540 break;
541 case AMDGPU_TEST_GFX_V11:
542 amdgpu_dispatch_write2hw_gfx11(test_priv);
543 break;
544 }
545 }
546
amdgpu_dispatch_write_dispatch_cmd(struct shader_test_priv * test_priv)547 static void amdgpu_dispatch_write_dispatch_cmd(struct shader_test_priv *test_priv)
548 {
549 int i = test_priv->cmd_curr;
550 uint32_t *ptr = test_priv->cmd.ptr;
551
552 /* clear mmCOMPUTE_RESOURCE_LIMITS */
553 ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1);
554 ptr[i++] = 0x215;
555 ptr[i++] = 0;
556
557 /* dispatch direct command */
558 ptr[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
559 ptr[i++] = (test_priv->dst.size / 16 + 0x40 - 1 ) / 0x40;//0x10;
560 ptr[i++] = 1;
561 ptr[i++] = 1;
562 ptr[i++] = 1;
563
564 test_priv->cmd_curr = i;
565 }
amdgpu_test_dispatch_memset(struct shader_test_info * test_info)566 static void amdgpu_test_dispatch_memset(struct shader_test_info *test_info)
567 {
568 amdgpu_context_handle context_handle;
569 amdgpu_bo_handle resources[3];
570 struct shader_test_priv test_priv;
571 struct shader_test_bo *cmd = &(test_priv.cmd);
572 struct shader_test_bo *dst = &(test_priv.dst);
573 struct shader_test_bo *shader = &(test_priv.shader_dispatch.cs_bo);
574 uint32_t *ptr_cmd;
575 uint8_t *ptr_dst;
576 int i, r;
577 struct amdgpu_cs_request ibs_request = {0};
578 struct amdgpu_cs_ib_info ib_info= {0};
579 amdgpu_bo_list_handle bo_list;
580 struct amdgpu_cs_fence fence_status = {0};
581 uint32_t expired;
582 uint8_t cptr[16];
583
584 memset(&test_priv, 0, sizeof(test_priv));
585 test_priv.info = test_info;
586 test_priv.shader_dispatch.cs_type = CS_BUFFERCLEAR;
587 r = amdgpu_cs_ctx_create(test_info->device_handle, &context_handle);
588 CU_ASSERT_EQUAL(r, 0);
589
590 cmd->size = 4096;
591 cmd->heap = AMDGPU_GEM_DOMAIN_GTT;
592 r = shader_test_bo_alloc(test_info->device_handle, cmd);
593 CU_ASSERT_EQUAL(r, 0);
594 ptr_cmd = cmd->ptr;
595 memset(ptr_cmd, 0, cmd->size);
596
597 shader->size = 4096;
598 shader->heap = AMDGPU_GEM_DOMAIN_VRAM;
599 r = shader_test_bo_alloc(test_info->device_handle, shader);
600 CU_ASSERT_EQUAL(r, 0);
601 memset(shader->ptr, 0, shader->size);
602 amdgpu_dispatch_load_cs_shader(&test_priv);
603
604 dst->size = 0x4000;
605 dst->heap = AMDGPU_GEM_DOMAIN_VRAM;
606 r = shader_test_bo_alloc(test_info->device_handle, dst);
607 CU_ASSERT_EQUAL(r, 0);
608
609 amdgpu_dispatch_init(&test_priv);
610
611 /* Issue commands to set cu mask used in current dispatch */
612 amdgpu_dispatch_write_cumask(&test_priv);
613
614 /* Writes shader state to HW */
615 amdgpu_dispatch_write2hw(&test_priv);
616
617 amdgpu_dispatch_write_dispatch_cmd(&test_priv);
618
619 i = test_priv.cmd_curr;
620 while (i & 7)
621 ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
622 test_priv.cmd_curr = i;
623
624 resources[0] = dst->bo;
625 resources[1] = shader->bo;
626 resources[2] = cmd->bo;
627 r = amdgpu_bo_list_create(test_info->device_handle, 3, resources, NULL, &bo_list);
628 CU_ASSERT_EQUAL(r, 0);
629
630 ib_info.ib_mc_address = cmd->mc_address;
631 ib_info.size = test_priv.cmd_curr;
632 ibs_request.ip_type = test_info->ip;
633 ibs_request.ring = test_info->ring;
634 ibs_request.resources = bo_list;
635 ibs_request.number_of_ibs = 1;
636 ibs_request.ibs = &ib_info;
637 ibs_request.fence_info.handle = NULL;
638
639 /* submit CS */
640 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
641 CU_ASSERT_EQUAL(r, 0);
642
643 r = amdgpu_bo_list_destroy(bo_list);
644 CU_ASSERT_EQUAL(r, 0);
645
646 fence_status.ip_type = test_info->ip;
647 fence_status.ip_instance = 0;
648 fence_status.ring = test_info->ring;
649 fence_status.context = context_handle;
650 fence_status.fence = ibs_request.seq_no;
651
652 /* wait for IB accomplished */
653 r = amdgpu_cs_query_fence_status(&fence_status,
654 AMDGPU_TIMEOUT_INFINITE,
655 0, &expired);
656 CU_ASSERT_EQUAL(r, 0);
657 CU_ASSERT_EQUAL(expired, true);
658
659 /* verify if memset test result meets with expected */
660 i = 0;
661 ptr_dst = (uint8_t *)(dst->ptr);
662 memset(cptr, 0x22, 16);
663 CU_ASSERT_EQUAL(memcmp(ptr_dst + i, cptr, 16), 0);
664 i = dst->size - 16;
665 CU_ASSERT_EQUAL(memcmp(ptr_dst + i, cptr, 16), 0);
666 i = dst->size / 2;
667 CU_ASSERT_EQUAL(memcmp(ptr_dst + i, cptr, 16), 0);
668
669 r = shader_test_bo_free(dst);
670 CU_ASSERT_EQUAL(r, 0);
671
672 r = shader_test_bo_free(shader);
673 CU_ASSERT_EQUAL(r, 0);
674
675 r = shader_test_bo_free(cmd);
676 CU_ASSERT_EQUAL(r, 0);
677
678 r = amdgpu_cs_ctx_free(context_handle);
679 CU_ASSERT_EQUAL(r, 0);
680 }
681
682 static
amdgpu_test_dispatch_memcpy(struct shader_test_info * test_info)683 void amdgpu_test_dispatch_memcpy(struct shader_test_info *test_info)
684 {
685 struct shader_test_priv test_priv;
686 amdgpu_context_handle context_handle;
687 amdgpu_bo_handle resources[4];
688 struct shader_test_bo *cmd = &(test_priv.cmd);
689 struct shader_test_bo *src = &(test_priv.src);
690 struct shader_test_bo *dst = &(test_priv.dst);
691 struct shader_test_bo *shader = &(test_priv.shader_dispatch.cs_bo);
692 uint32_t *ptr_cmd;
693 uint8_t *ptr_src;
694 uint8_t *ptr_dst;
695 int i, r;
696 struct amdgpu_cs_request ibs_request = {0};
697 struct amdgpu_cs_ib_info ib_info= {0};
698 uint32_t expired, hang_state, hangs;
699 amdgpu_bo_list_handle bo_list;
700 struct amdgpu_cs_fence fence_status = {0};
701
702 memset(&test_priv, 0, sizeof(test_priv));
703 test_priv.info = test_info;
704 test_priv.cmd.size = 4096;
705 test_priv.cmd.heap = AMDGPU_GEM_DOMAIN_GTT;
706
707 test_priv.shader_dispatch.cs_bo.heap = AMDGPU_GEM_DOMAIN_VRAM;
708 test_priv.shader_dispatch.cs_type = CS_BUFFERCOPY;
709 test_priv.src.heap = AMDGPU_GEM_DOMAIN_VRAM;
710 test_priv.dst.heap = AMDGPU_GEM_DOMAIN_VRAM;
711 if (test_info->hang_slow) {
712 test_priv.shader_dispatch.cs_bo.size = 0x4000000;
713 test_priv.src.size = 0x4000000;
714 test_priv.dst.size = 0x4000000;
715 } else {
716 test_priv.shader_dispatch.cs_bo.size = 4096;
717 test_priv.src.size = 0x4000;
718 test_priv.dst.size = 0x4000;
719 }
720
721 r = amdgpu_cs_ctx_create(test_info->device_handle, &context_handle);
722 CU_ASSERT_EQUAL(r, 0);
723
724 r = shader_test_bo_alloc(test_info->device_handle, cmd);
725 CU_ASSERT_EQUAL(r, 0);
726 ptr_cmd = cmd->ptr;
727 memset(ptr_cmd, 0, cmd->size);
728
729 r = shader_test_bo_alloc(test_info->device_handle, shader);
730 CU_ASSERT_EQUAL(r, 0);
731 memset(shader->ptr, 0, shader->size);
732 amdgpu_dispatch_load_cs_shader(&test_priv);
733
734 r = shader_test_bo_alloc(test_info->device_handle, src);
735 CU_ASSERT_EQUAL(r, 0);
736 ptr_src = (uint8_t *)(src->ptr);
737 memset(ptr_src, 0x55, src->size);
738
739 r = shader_test_bo_alloc(test_info->device_handle, dst);
740 CU_ASSERT_EQUAL(r, 0);
741
742 amdgpu_dispatch_init(&test_priv);
743
744 /* Issue commands to set cu mask used in current dispatch */
745 amdgpu_dispatch_write_cumask(&test_priv);
746
747 /* Writes shader state to HW */
748 amdgpu_dispatch_write2hw(&test_priv);
749
750 amdgpu_dispatch_write_dispatch_cmd(&test_priv);
751
752 i = test_priv.cmd_curr;
753 while (i & 7)
754 ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
755 test_priv.cmd_curr = i;
756
757 resources[0] = shader->bo;
758 resources[1] = src->bo;
759 resources[2] = dst->bo;
760 resources[3] = cmd->bo;
761 r = amdgpu_bo_list_create(test_info->device_handle, 4, resources, NULL, &bo_list);
762 CU_ASSERT_EQUAL(r, 0);
763
764 ib_info.ib_mc_address = cmd->mc_address;
765 ib_info.size = test_priv.cmd_curr;
766 ibs_request.ip_type = test_info->ip;
767 ibs_request.ring = test_info->ring;
768 ibs_request.resources = bo_list;
769 ibs_request.number_of_ibs = 1;
770 ibs_request.ibs = &ib_info;
771 ibs_request.fence_info.handle = NULL;
772 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
773 CU_ASSERT_EQUAL(r, 0);
774
775 fence_status.ip_type = test_info->ip;
776 fence_status.ip_instance = 0;
777 fence_status.ring = test_info->ring;
778 fence_status.context = context_handle;
779 fence_status.fence = ibs_request.seq_no;
780
781 /* wait for IB accomplished */
782 r = amdgpu_cs_query_fence_status(&fence_status,
783 AMDGPU_TIMEOUT_INFINITE,
784 0, &expired);
785
786 if (!test_info->hang) {
787 CU_ASSERT_EQUAL(r, 0);
788 CU_ASSERT_EQUAL(expired, true);
789
790 /* verify if memcpy test result meets with expected */
791 i = 0;
792 ptr_dst = (uint8_t *)dst->ptr;
793 CU_ASSERT_EQUAL(memcmp(ptr_dst + i, ptr_src + i, 16), 0);
794 i = dst->size - 16;
795 CU_ASSERT_EQUAL(memcmp(ptr_dst + i, ptr_src + i, 16), 0);
796 i = dst->size / 2;
797 CU_ASSERT_EQUAL(memcmp(ptr_dst + i, ptr_src + i, 16), 0);
798 } else {
799 r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs);
800 CU_ASSERT_EQUAL(r, 0);
801 CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET);
802 }
803
804 r = amdgpu_bo_list_destroy(bo_list);
805 CU_ASSERT_EQUAL(r, 0);
806
807 r = shader_test_bo_free(src);
808 CU_ASSERT_EQUAL(r, 0);
809 r = shader_test_bo_free(dst);
810 CU_ASSERT_EQUAL(r, 0);
811
812 r = shader_test_bo_free(shader);
813 CU_ASSERT_EQUAL(r, 0);
814
815 r = shader_test_bo_free(cmd);
816
817 r = amdgpu_cs_ctx_free(context_handle);
818 CU_ASSERT_EQUAL(r, 0);
819 }
820
shader_test_dispatch_cb(struct shader_test_info * test_info)821 static void shader_test_dispatch_cb(struct shader_test_info *test_info)
822 {
823 amdgpu_test_dispatch_memset(test_info);
824 amdgpu_test_dispatch_memcpy(test_info);
825 }
shader_test_dispatch_hang_cb(struct shader_test_info * test_info)826 static void shader_test_dispatch_hang_cb(struct shader_test_info *test_info)
827 {
828 test_info->hang = 0;
829 amdgpu_test_dispatch_memcpy(test_info);
830
831 test_info->hang = 1;
832 amdgpu_test_dispatch_memcpy(test_info);
833
834 test_info->hang = 0;
835 amdgpu_test_dispatch_memcpy(test_info);
836 }
837
shader_test_dispatch_hang_slow_cb(struct shader_test_info * test_info)838 static void shader_test_dispatch_hang_slow_cb(struct shader_test_info *test_info)
839 {
840 test_info->hang = 0;
841 test_info->hang_slow = 0;
842 amdgpu_test_dispatch_memcpy(test_info);
843
844 test_info->hang = 1;
845 test_info->hang_slow = 1;
846 amdgpu_test_dispatch_memcpy(test_info);
847
848 test_info->hang = 0;
849 test_info->hang_slow = 0;
850 amdgpu_test_dispatch_memcpy(test_info);
851 }
852
amdgpu_test_dispatch_helper(amdgpu_device_handle device_handle,unsigned ip)853 void amdgpu_test_dispatch_helper(amdgpu_device_handle device_handle, unsigned ip)
854 {
855 shader_test_for_each(device_handle, ip, shader_test_dispatch_cb);
856 }
857
amdgpu_test_dispatch_hang_helper(amdgpu_device_handle device_handle,uint32_t ip)858 void amdgpu_test_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip)
859 {
860 shader_test_for_each(device_handle, ip, shader_test_dispatch_hang_cb);
861 }
862
amdgpu_test_dispatch_hang_slow_helper(amdgpu_device_handle device_handle,uint32_t ip)863 void amdgpu_test_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip)
864 {
865 shader_test_for_each(device_handle, ip, shader_test_dispatch_hang_slow_cb);
866 }
867
amdgpu_draw_load_ps_shader_hang_slow(struct shader_test_priv * test_priv)868 static void amdgpu_draw_load_ps_shader_hang_slow(struct shader_test_priv *test_priv)
869 {
870 struct amdgpu_gpu_info gpu_info = {0};
871 struct shader_test_shader_bin *ps_shader_bin = &memcpy_ps_hang_slow_navi21;
872 int r;
873
874 r = amdgpu_query_gpu_info(test_priv->info->device_handle, &gpu_info);
875 CU_ASSERT_EQUAL(r, 0);
876
877 switch (gpu_info.family_id) {
878 case AMDGPU_FAMILY_AI:
879 case AMDGPU_FAMILY_RV:
880 ps_shader_bin = &memcpy_ps_hang_slow_ai;
881 break;
882 case AMDGPU_FAMILY_NV:
883 if (gpu_info.chip_external_rev < 40)
884 ps_shader_bin = &memcpy_ps_hang_slow_navi10;
885 break;
886 }
887
888 shader_test_load_shader_hang_slow(&test_priv->shader_draw.ps_bo, ps_shader_bin);
889 }
890
round_up_size(uint32_t size)891 static uint32_t round_up_size(uint32_t size)
892 {
893 return (size + 255) & ~255;
894 }
amdgpu_draw_load_ps_shader(struct shader_test_priv * test_priv)895 static void amdgpu_draw_load_ps_shader(struct shader_test_priv *test_priv)
896 {
897 uint8_t *ptr_shader = test_priv->shader_draw.ps_bo.ptr;
898 const struct shader_test_ps_shader *shader;
899 uint32_t shader_offset, num_export_fmt;
900 uint32_t mem_offset, patch_code_offset;
901 int i;
902
903 if (test_priv->info->hang) {
904 if (test_priv->info->hang_slow)
905 amdgpu_draw_load_ps_shader_hang_slow(test_priv);
906 else
907 memcpy(ptr_shader, memcpy_shader_hang, sizeof(memcpy_shader_hang));
908
909 return;
910 }
911
912 shader = &shader_test_ps[test_priv->info->version][test_priv->shader_draw.ps_type];
913 num_export_fmt = 10;
914 shader_offset = round_up_size(shader->shader_size);
915 /* write main shader program */
916 for (i = 0 ; i < num_export_fmt; i++) {
917 mem_offset = i * shader_offset;
918 memcpy(ptr_shader + mem_offset, shader->shader, shader->shader_size);
919 }
920
921 /* overwrite patch codes */
922 for (i = 0 ; i < num_export_fmt; i++) {
923 mem_offset = i * shader_offset + shader->patchinfo_code_offset[0] * sizeof(uint32_t);
924 patch_code_offset = i * shader->patchinfo_code_size;
925 memcpy(ptr_shader + mem_offset,
926 shader->patchinfo_code + patch_code_offset,
927 shader->patchinfo_code_size * sizeof(uint32_t));
928 }
929 }
930
931 /* load RectPosTexFast_VS */
amdgpu_draw_load_vs_shader(struct shader_test_priv * test_priv)932 static void amdgpu_draw_load_vs_shader(struct shader_test_priv *test_priv)
933 {
934 uint8_t *ptr_shader = test_priv->shader_draw.vs_bo.ptr;
935 const struct shader_test_vs_shader *shader = &shader_test_vs[test_priv->info->version][test_priv->shader_draw.vs_type];
936
937 memcpy(ptr_shader, shader->shader, shader->shader_size);
938 }
939
amdgpu_draw_init(struct shader_test_priv * test_priv)940 static void amdgpu_draw_init(struct shader_test_priv *test_priv)
941 {
942 int i;
943 uint32_t *ptr = test_priv->cmd.ptr;
944 const struct shader_test_gfx_info *gfx_info = &shader_test_gfx_info[test_priv->info->version];
945
946 /* Write context control and load shadowing register if necessary */
947 write_context_control(test_priv);
948 i = test_priv->cmd_curr;
949
950 if (test_priv->info->version == AMDGPU_TEST_GFX_V11) {
951 ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
952 ptr[i++] = 0x446;
953 ptr[i++] = (test_priv->vtx_attributes_mem.mc_address >> 16);
954 // mmSPI_ATTRIBUTE_RING_SIZE
955 ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
956 ptr[i++] = 0x447;
957 ptr[i++] = 0x20001;
958 }
959 memcpy(ptr + i, gfx_info->preamble_cache, gfx_info->size_preamble_cache);
960
961 test_priv->cmd_curr = i + gfx_info->size_preamble_cache/sizeof(uint32_t);
962 }
963
amdgpu_draw_setup_and_write_drawblt_surf_info_gfx9(struct shader_test_priv * test_priv)964 static void amdgpu_draw_setup_and_write_drawblt_surf_info_gfx9(struct shader_test_priv *test_priv)
965 {
966 int i = test_priv->cmd_curr;
967 uint32_t *ptr = test_priv->cmd.ptr;
968
969 /* setup color buffer */
970 /* offset reg
971 0xA318 CB_COLOR0_BASE
972 0xA319 CB_COLOR0_BASE_EXT
973 0xA31A CB_COLOR0_ATTRIB2
974 0xA31B CB_COLOR0_VIEW
975 0xA31C CB_COLOR0_INFO
976 0xA31D CB_COLOR0_ATTRIB
977 0xA31E CB_COLOR0_DCC_CONTROL
978 0xA31F CB_COLOR0_CMASK
979 0xA320 CB_COLOR0_CMASK_BASE_EXT
980 0xA321 CB_COLOR0_FMASK
981 0xA322 CB_COLOR0_FMASK_BASE_EXT
982 0xA323 CB_COLOR0_CLEAR_WORD0
983 0xA324 CB_COLOR0_CLEAR_WORD1
984 0xA325 CB_COLOR0_DCC_BASE
985 0xA326 CB_COLOR0_DCC_BASE_EXT */
986 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 15);
987 ptr[i++] = 0x318;
988 ptr[i++] = test_priv->dst.mc_address >> 8;
989 ptr[i++] = test_priv->dst.mc_address >> 40;
990 ptr[i++] = test_priv->info->hang_slow ? 0x3ffc7ff : 0x7c01f;
991 ptr[i++] = 0;
992 ptr[i++] = 0x50438;
993 ptr[i++] = 0x10140000;
994 i += 9;
995
996 /* mmCB_MRT0_EPITCH */
997 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
998 ptr[i++] = 0x1e8;
999 ptr[i++] = test_priv->info->hang_slow ? 0xfff : 0x1f;
1000
1001 /* 0xA32B CB_COLOR1_BASE */
1002 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1003 ptr[i++] = 0x32b;
1004 ptr[i++] = 0;
1005
1006 /* 0xA33A CB_COLOR1_BASE */
1007 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1008 ptr[i++] = 0x33a;
1009 ptr[i++] = 0;
1010
1011 /* SPI_SHADER_COL_FORMAT */
1012 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1013 ptr[i++] = 0x1c5;
1014 ptr[i++] = 9;
1015
1016 /* Setup depth buffer */
1017 /* mmDB_Z_INFO */
1018 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
1019 ptr[i++] = 0xe;
1020 i += 2;
1021
1022 test_priv->cmd_curr = i;
1023 }
amdgpu_draw_setup_and_write_drawblt_surf_info_gfx10(struct shader_test_priv * test_priv)1024 static void amdgpu_draw_setup_and_write_drawblt_surf_info_gfx10(struct shader_test_priv *test_priv)
1025 {
1026 int i = test_priv->cmd_curr;
1027 uint32_t *ptr = test_priv->cmd.ptr;
1028
1029 /* setup color buffer */
1030 /* 0xA318 CB_COLOR0_BASE
1031 0xA319 CB_COLOR0_PITCH
1032 0xA31A CB_COLOR0_SLICE
1033 0xA31B CB_COLOR0_VIEW
1034 0xA31C CB_COLOR0_INFO
1035 0xA31D CB_COLOR0_ATTRIB
1036 0xA31E CB_COLOR0_DCC_CONTROL
1037 0xA31F CB_COLOR0_CMASK
1038 0xA320 CB_COLOR0_CMASK_SLICE
1039 0xA321 CB_COLOR0_FMASK
1040 0xA322 CB_COLOR0_FMASK_SLICE
1041 0xA323 CB_COLOR0_CLEAR_WORD0
1042 0xA324 CB_COLOR0_CLEAR_WORD1
1043 0xA325 CB_COLOR0_DCC_BASE */
1044 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 14);
1045 ptr[i++] = 0x318;
1046 ptr[i++] = test_priv->dst.mc_address >> 8;
1047 i += 3;
1048 ptr[i++] = 0x50438;
1049 i += 9;
1050
1051 /* 0xA390 CB_COLOR0_BASE_EXT */
1052 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1053 ptr[i++] = 0x390;
1054 ptr[i++] = test_priv->dst.mc_address >> 40;
1055
1056 /* 0xA398 CB_COLOR0_CMASK_BASE_EXT */
1057 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1058 ptr[i++] = 0x398;
1059 ptr[i++] = 0;
1060
1061 /* 0xA3A0 CB_COLOR0_FMASK_BASE_EXT */
1062 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1063 ptr[i++] = 0x3a0;
1064 ptr[i++] = 0;
1065
1066 /* 0xA3A8 CB_COLOR0_DCC_BASE_EXT */
1067 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1068 ptr[i++] = 0x3a8;
1069 ptr[i++] = 0;
1070
1071 /* 0xA3B0 CB_COLOR0_ATTRIB2 */
1072 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1073 ptr[i++] = 0x3b0;
1074 ptr[i++] = test_priv->info->hang_slow ? 0x3ffc7ff : 0x7c01f;
1075
1076 /* 0xA3B8 CB_COLOR0_ATTRIB3 */
1077 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1078 ptr[i++] = 0x3b8;
1079 ptr[i++] = 0x9014000;
1080
1081 /* 0xA32B CB_COLOR1_BASE */
1082 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1083 ptr[i++] = 0x32b;
1084 ptr[i++] = 0;
1085
1086 /* 0xA33A CB_COLOR1_BASE */
1087 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1088 ptr[i++] = 0x33a;
1089 ptr[i++] = 0;
1090
1091 /* SPI_SHADER_COL_FORMAT */
1092 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1093 ptr[i++] = 0x1c5;
1094 ptr[i++] = 9;
1095
1096 /* Setup depth buffer */
1097 /* mmDB_Z_INFO */
1098 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
1099 ptr[i++] = 0x10;
1100 i += 2;
1101
1102 test_priv->cmd_curr = i;
1103 }
1104
amdgpu_draw_setup_and_write_drawblt_surf_info_gfx11(struct shader_test_priv * test_priv)1105 static void amdgpu_draw_setup_and_write_drawblt_surf_info_gfx11(struct shader_test_priv *test_priv)
1106 {
1107 int i = test_priv->cmd_curr;
1108 uint32_t *ptr = test_priv->cmd.ptr;
1109
1110 /* mmCB_COLOR0_BASE */
1111 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1112 ptr[i++] = 0x318;
1113 ptr[i++] = test_priv->dst.mc_address >> 8;
1114 /* mmCB_COLOR0_VIEW .. mmCB_COLOR0_DCC_CONTROL */
1115 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 4);
1116 ptr[i++] = 0x31b;
1117 i++;
1118 ptr[i++] = 0x5040e;
1119 i += 2;
1120 /* mmCB_COLOR0_DCC_BASE */
1121 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1122 ptr[i++] = 0x325;
1123 ptr[i++] = 0;
1124 /* mmCB_COLOR0_BASE_EXT */
1125 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1126 ptr[i++] = 0x390;
1127 ptr[i++] = (test_priv->dst.mc_address >> 40) & 0xFF;
1128 /* mmCB_COLOR0_DCC_BASE_EXT */
1129 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1130 ptr[i++] = 0x3a8;
1131 ptr[i++] = 0;
1132 /* mmCB_COLOR0_ATTRIB2 */
1133 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1134 ptr[i++] = 0x3b0;
1135 ptr[i++] = test_priv->info->hang_slow ? 0x1ffc7ff : 0x7c01f;
1136 /* mmCB_COLOR0_ATTRIB3 */
1137 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1138 ptr[i++] = 0x3b8;
1139 ptr[i++] = test_priv->info->hang_slow ? 0x1028000 : 0x1018000;
1140 /* mmCB_COLOR0_INFO */
1141 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1142 ptr[i++] = 0x32b;
1143 ptr[i++] = 0;
1144 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1145 ptr[i++] = 0x33a;
1146 ptr[i++] = 0;
1147 /* mmSPI_SHADER_COL_FORMAT */
1148 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1149 ptr[i++] = 0x1c5;
1150 ptr[i++] = 0x9;
1151 /* mmDB_Z_INFO */
1152 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
1153 ptr[i++] = 0x10;
1154 i += 2;
1155
1156 test_priv->cmd_curr = i;
1157 }
1158
amdgpu_draw_setup_and_write_drawblt_surf_info(struct shader_test_priv * test_priv)1159 static void amdgpu_draw_setup_and_write_drawblt_surf_info(struct shader_test_priv *test_priv)
1160 {
1161 switch (test_priv->info->version) {
1162 case AMDGPU_TEST_GFX_V9:
1163 amdgpu_draw_setup_and_write_drawblt_surf_info_gfx9(test_priv);
1164 break;
1165 case AMDGPU_TEST_GFX_V10:
1166 amdgpu_draw_setup_and_write_drawblt_surf_info_gfx10(test_priv);
1167 break;
1168 case AMDGPU_TEST_GFX_V11:
1169 amdgpu_draw_setup_and_write_drawblt_surf_info_gfx11(test_priv);
1170 break;
1171 }
1172 }
1173
amdgpu_draw_setup_and_write_drawblt_state_gfx9(struct shader_test_priv * test_priv)1174 static void amdgpu_draw_setup_and_write_drawblt_state_gfx9(struct shader_test_priv *test_priv)
1175 {
1176 int i = test_priv->cmd_curr;
1177 uint32_t *ptr = test_priv->cmd.ptr;
1178 const struct shader_test_gfx_info *gfx_info = &shader_test_gfx_info[test_priv->info->version];
1179
1180 /* mmPA_SC_TILE_STEERING_OVERRIDE */
1181 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1182 ptr[i++] = 0xd7;
1183 ptr[i++] = 0;
1184
1185 ptr[i++] = 0xffff1000;
1186 ptr[i++] = 0xc0021000;
1187
1188 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1189 ptr[i++] = 0xd7;
1190 ptr[i++] = 1;
1191
1192 /* mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
1193 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 16);
1194 ptr[i++] = 0x2fe;
1195 i += 16;
1196
1197 /* mmPA_SC_CENTROID_PRIORITY_0 */
1198 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
1199 ptr[i++] = 0x2f5;
1200 i += 2;
1201
1202 memcpy(ptr + i, gfx_info->cached_cmd, gfx_info->size_cached_cmd);
1203 if (test_priv->info->hang_slow)
1204 *(ptr + i + 12) = 0x8000800;
1205
1206 test_priv->cmd_curr = i + gfx_info->size_cached_cmd/sizeof(uint32_t);
1207 }
1208
amdgpu_draw_setup_and_write_drawblt_state_gfx10(struct shader_test_priv * test_priv)1209 static void amdgpu_draw_setup_and_write_drawblt_state_gfx10(struct shader_test_priv *test_priv)
1210 {
1211 int i = test_priv->cmd_curr;
1212 uint32_t *ptr = test_priv->cmd.ptr;
1213 const struct shader_test_gfx_info *gfx_info = &shader_test_gfx_info[test_priv->info->version];
1214
1215 /* mmPA_SC_TILE_STEERING_OVERRIDE */
1216 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1217 ptr[i++] = 0xd7;
1218 ptr[i++] = 0;
1219
1220 ptr[i++] = 0xffff1000;
1221 ptr[i++] = 0xc0021000;
1222
1223 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1224 ptr[i++] = 0xd7;
1225 ptr[i++] = 0;
1226
1227 /* mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
1228 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 16);
1229 ptr[i++] = 0x2fe;
1230 i += 16;
1231
1232 /* mmPA_SC_CENTROID_PRIORITY_0 */
1233 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
1234 ptr[i++] = 0x2f5;
1235 i += 2;
1236
1237 memcpy(ptr + i, gfx_info->cached_cmd, gfx_info->size_cached_cmd);
1238 if (test_priv->info->hang_slow)
1239 *(ptr + i + 12) = 0x8000800;
1240 i += gfx_info->size_cached_cmd/sizeof(uint32_t);
1241
1242 /* mmCB_RMI_GL2_CACHE_CONTROL */
1243 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1244 ptr[i++] = 0x104;
1245 ptr[i++] = 0x40aa0055;
1246 /* mmDB_RMI_L2_CACHE_CONTROL */
1247 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1248 ptr[i++] = 0x1f;
1249 ptr[i++] = 0x2a0055;
1250
1251 test_priv->cmd_curr = i;
1252 }
1253
amdgpu_draw_setup_and_write_drawblt_state_gfx11(struct shader_test_priv * test_priv)1254 static void amdgpu_draw_setup_and_write_drawblt_state_gfx11(struct shader_test_priv *test_priv)
1255 {
1256 int i = test_priv->cmd_curr;
1257 uint32_t *ptr = test_priv->cmd.ptr;
1258 const struct shader_test_gfx_info *gfx_info = &shader_test_gfx_info[test_priv->info->version];
1259
1260 /* mmPA_SC_TILE_STEERING_OVERRIDE */
1261 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1262 ptr[i++] = 0xd7;
1263 ptr[i++] = 0;
1264
1265 ptr[i++] = 0xffff1000;
1266 ptr[i++] = 0xc0021000;
1267
1268 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1269 ptr[i++] = 0xd7;
1270 i++;
1271
1272 /* mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
1273 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 16);
1274 ptr[i++] = 0x2fe;
1275 i += 16;
1276
1277 /* mmPA_SC_CENTROID_PRIORITY_0 */
1278 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
1279 ptr[i++] = 0x2f5;
1280 i += 2;
1281
1282 memcpy(ptr + i, gfx_info->cached_cmd, gfx_info->size_cached_cmd);
1283 if (test_priv->info->hang_slow)
1284 *(ptr + i + 12) = 0x8000800;
1285
1286 test_priv->cmd_curr = i + gfx_info->size_cached_cmd/sizeof(uint32_t);
1287 }
1288
amdgpu_draw_setup_and_write_drawblt_state(struct shader_test_priv * test_priv)1289 static void amdgpu_draw_setup_and_write_drawblt_state(struct shader_test_priv *test_priv)
1290 {
1291 switch (test_priv->info->version) {
1292 case AMDGPU_TEST_GFX_V9:
1293 amdgpu_draw_setup_and_write_drawblt_state_gfx9(test_priv);
1294 break;
1295 case AMDGPU_TEST_GFX_V10:
1296 amdgpu_draw_setup_and_write_drawblt_state_gfx10(test_priv);
1297 break;
1298 case AMDGPU_TEST_GFX_V11:
1299 amdgpu_draw_setup_and_write_drawblt_state_gfx11(test_priv);
1300 break;
1301 }
1302 }
1303
amdgpu_draw_vs_RectPosTexFast_write2hw_gfx9(struct shader_test_priv * test_priv)1304 static void amdgpu_draw_vs_RectPosTexFast_write2hw_gfx9(struct shader_test_priv *test_priv)
1305 {
1306 int i = test_priv->cmd_curr;
1307 uint32_t *ptr = test_priv->cmd.ptr;
1308 uint64_t shader_addr = test_priv->shader_draw.vs_bo.mc_address;
1309 enum ps_type ps = test_priv->shader_draw.ps_type;
1310
1311 /* mmPA_CL_VS_OUT_CNTL */
1312 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1313 ptr[i++] = 0x207;
1314 ptr[i++] = 0;
1315
1316 /* mmSPI_SHADER_PGM_RSRC3_VS */
1317 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1);
1318 ptr[i++] = 0x46;
1319 ptr[i++] = 0xffff;
1320
1321 /* mmSPI_SHADER_PGM_LO_VS...mmSPI_SHADER_PGM_HI_VS */
1322 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 2);
1323 ptr[i++] = 0x48;
1324 ptr[i++] = shader_addr >> 8;
1325 ptr[i++] = shader_addr >> 40;
1326
1327 /* mmSPI_SHADER_PGM_RSRC1_VS */
1328 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1);
1329 ptr[i++] = 0x4a;
1330 ptr[i++] = 0xc0081;
1331
1332 /* mmSPI_SHADER_PGM_RSRC2_VS */
1333 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1);
1334 ptr[i++] = 0x4b;
1335 ptr[i++] = 0x18;
1336
1337 /* mmSPI_VS_OUT_CONFIG */
1338 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1339 ptr[i++] = 0x1b1;
1340 ptr[i++] = 2;
1341
1342 /* mmSPI_SHADER_POS_FORMAT */
1343 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1344 ptr[i++] = 0x1c3;
1345 ptr[i++] = 4;
1346
1347 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
1348 ptr[i++] = 0x4c;
1349 i += 2;
1350 ptr[i++] = test_priv->info->hang_slow ? 0x45000000 : 0x42000000;
1351 ptr[i++] = test_priv->info->hang_slow ? 0x45000000 : 0x42000000;
1352
1353 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
1354 ptr[i++] = 0x50;
1355 i += 2;
1356 if (ps == PS_CONST) {
1357 i += 2;
1358 } else if (ps == PS_TEX) {
1359 ptr[i++] = 0x3f800000;
1360 ptr[i++] = 0x3f800000;
1361 }
1362
1363 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
1364 ptr[i++] = 0x54;
1365 i += 4;
1366
1367 test_priv->cmd_curr = i;
1368 }
1369
amdgpu_draw_vs_RectPosTexFast_write2hw_gfx10(struct shader_test_priv * test_priv)1370 static void amdgpu_draw_vs_RectPosTexFast_write2hw_gfx10(struct shader_test_priv *test_priv)
1371 {
1372 int i = test_priv->cmd_curr;
1373 uint32_t *ptr = test_priv->cmd.ptr;
1374 uint64_t shader_addr = test_priv->shader_draw.vs_bo.mc_address;
1375 enum ps_type ps = test_priv->shader_draw.ps_type;
1376
1377 /* mmPA_CL_VS_OUT_CNTL */
1378 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1379 ptr[i++] = 0x207;
1380 ptr[i++] = 0;
1381
1382 /* mmSPI_SHADER_PGM_RSRC3_VS */
1383 ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1);
1384 ptr[i++] = 0x30000046;
1385 ptr[i++] = 0xffff;
1386 /* mmSPI_SHADER_PGM_RSRC4_VS */
1387 ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1);
1388 ptr[i++] = 0x30000041;
1389 ptr[i++] = 0xffff;
1390
1391 /* mmSPI_SHADER_PGM_LO_VS...mmSPI_SHADER_PGM_HI_VS */
1392 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 2);
1393 ptr[i++] = 0x48;
1394 ptr[i++] = shader_addr >> 8;
1395 ptr[i++] = shader_addr >> 40;
1396
1397 /* mmSPI_SHADER_PGM_RSRC1_VS */
1398 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1);
1399 ptr[i++] = 0x4a;
1400 ptr[i++] = 0xc0041;
1401 /* mmSPI_SHADER_PGM_RSRC2_VS */
1402 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1);
1403 ptr[i++] = 0x4b;
1404 ptr[i++] = 0x18;
1405
1406 /* mmSPI_VS_OUT_CONFIG */
1407 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1408 ptr[i++] = 0x1b1;
1409 ptr[i++] = 2;
1410
1411 /* mmSPI_SHADER_POS_FORMAT */
1412 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1413 ptr[i++] = 0x1c3;
1414 ptr[i++] = 4;
1415
1416 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
1417 ptr[i++] = 0x4c;
1418 i += 2;
1419 ptr[i++] = test_priv->info->hang_slow ? 0x45000000 : 0x42000000;
1420 ptr[i++] = test_priv->info->hang_slow ? 0x45000000 : 0x42000000;
1421
1422 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
1423 ptr[i++] = 0x50;
1424 i += 2;
1425 if (ps == PS_CONST) {
1426 i += 2;
1427 } else if (ps == PS_TEX) {
1428 ptr[i++] = 0x3f800000;
1429 ptr[i++] = 0x3f800000;
1430 }
1431
1432 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
1433 ptr[i++] = 0x54;
1434 i += 4;
1435
1436 test_priv->cmd_curr = i;
1437 }
1438
1439
amdgpu_draw_vs_RectPosTexFast_write2hw_gfx11(struct shader_test_priv * test_priv)1440 static void amdgpu_draw_vs_RectPosTexFast_write2hw_gfx11(struct shader_test_priv *test_priv)
1441 {
1442 int i = test_priv->cmd_curr;
1443 uint32_t *ptr = test_priv->cmd.ptr;
1444 const struct shader_test_gfx_info *gfx_info = &shader_test_gfx_info[test_priv->info->version];
1445 uint64_t shader_addr = test_priv->shader_draw.vs_bo.mc_address;
1446 const struct shader_test_vs_shader *shader = &shader_test_vs[test_priv->info->version][test_priv->shader_draw.vs_type];
1447 enum ps_type ps = test_priv->shader_draw.ps_type;
1448 int j, offset;
1449
1450 /* mmPA_CL_VS_OUT_CNTL */
1451 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1452 ptr[i++] = 0x207;
1453 ptr[i++] = 0;
1454
1455 /* mmSPI_SHADER_PGM_RSRC3_GS */
1456 ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1);
1457 ptr[i++] = 0x30000087;
1458 ptr[i++] = 0xffff;
1459 /* mmSPI_SHADER_PGM_RSRC4_GS */
1460 ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1);
1461 ptr[i++] = 0x30000081;
1462 ptr[i++] = 0x1fff0001;
1463
1464 /* mmSPI_SHADER_PGM_LO_ES */
1465 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 2);
1466 ptr[i++] = 0xc8;
1467 ptr[i++] = shader_addr >> 8;
1468 ptr[i++] = shader_addr >> 40;
1469
1470 /* write sh reg */
1471 for (j = 0; j < shader->num_sh_reg; j++) {
1472 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1);
1473 ptr[i++] = shader->sh_reg[j].reg_offset - gfx_info->sh_reg_base;
1474 ptr[i++] = shader->sh_reg[j].reg_value;
1475 }
1476 /* write context reg */
1477 for (j = 0; j < shader->num_context_reg; j++) {
1478 switch (shader->context_reg[j].reg_offset) {
1479 case 0xA1B1: //mmSPI_VS_OUT_CONFIG
1480 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1481 ptr[i++] = shader->context_reg[j].reg_offset - gfx_info->context_reg_base;
1482 ptr[i++] = 2;
1483 break;
1484 case 0xA1C3: //mmSPI_SHADER_POS_FORMAT
1485 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1486 ptr[i++] = shader->context_reg[j].reg_offset - gfx_info->context_reg_base;
1487 ptr[i++] = 4;
1488 break;
1489 case 0xA2E4: //mmVGT_GS_INSTANCE_CNT
1490 case 0xA2CE: //mmVGT_GS_MAX_VERT_OUT
1491 break;
1492 default:
1493 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1494 ptr[i++] = shader->context_reg[j].reg_offset - gfx_info->context_reg_base;
1495 ptr[i++] = shader->context_reg[j].reg_value;
1496 break;
1497 }
1498 }
1499
1500 // write constant
1501 // dst rect
1502 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
1503 ptr[i++] = 0x8c;
1504 i += 2;
1505 ptr[i++] = test_priv->info->hang_slow ? 0x45000000 : 0x42000000;
1506 ptr[i++] = test_priv->info->hang_slow ? 0x45000000 : 0x42000000;
1507 // src rect
1508 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
1509 ptr[i++] = 0x90;
1510 i += 2;
1511 if (ps == PS_CONST) {
1512 i += 2;
1513 } else if (ps == PS_TEX) {
1514 ptr[i++] = 0x3f800000;
1515 ptr[i++] = 0x3f800000;
1516 }
1517
1518 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
1519 ptr[i++] = 0x94;
1520 i += 4;
1521 // vtx_attributes_mem
1522 ptr[i++] = 0xc02f1000;
1523 offset = i * sizeof(uint32_t);
1524 i += 44;
1525 ptr[i++] = test_priv->vtx_attributes_mem.mc_address & 0xffffffff;
1526 ptr[i++] = 0xc0100000 | ((test_priv->vtx_attributes_mem.mc_address >> 32) & 0xffff);
1527 ptr[i++] = test_priv->vtx_attributes_mem.size / 16;
1528 ptr[i++] = 0x2043ffac;
1529 ptr[i++] = PACKET3(PACKET3_SET_SH_REG_OFFSET, 2);
1530 ptr[i++] = 0x98;
1531 ptr[i++] = offset;
1532 i++;
1533
1534 test_priv->cmd_curr = i;
1535 }
1536
amdgpu_draw_vs_RectPosTexFast_write2hw(struct shader_test_priv * test_priv)1537 static void amdgpu_draw_vs_RectPosTexFast_write2hw(struct shader_test_priv *test_priv)
1538 {
1539 switch (test_priv->info->version) {
1540 case AMDGPU_TEST_GFX_V9:
1541 amdgpu_draw_vs_RectPosTexFast_write2hw_gfx9(test_priv);
1542 break;
1543 case AMDGPU_TEST_GFX_V10:
1544 amdgpu_draw_vs_RectPosTexFast_write2hw_gfx10(test_priv);
1545 break;
1546 case AMDGPU_TEST_GFX_V11:
1547 amdgpu_draw_vs_RectPosTexFast_write2hw_gfx11(test_priv);
1548 break;
1549 }
1550 }
1551
amdgpu_draw_ps_write2hw_gfx9_10(struct shader_test_priv * test_priv)1552 static void amdgpu_draw_ps_write2hw_gfx9_10(struct shader_test_priv *test_priv)
1553 {
1554 int i, j;
1555 uint64_t shader_addr = test_priv->shader_draw.ps_bo.mc_address;
1556 const struct shader_test_ps_shader *ps = &shader_test_ps[test_priv->info->version][test_priv->shader_draw.ps_type];
1557 uint32_t *ptr = test_priv->cmd.ptr;
1558
1559 i = test_priv->cmd_curr;
1560
1561 if (test_priv->info->version == AMDGPU_TEST_GFX_V9) {
1562 /* 0x2c07 SPI_SHADER_PGM_RSRC3_PS
1563 0x2c08 SPI_SHADER_PGM_LO_PS
1564 0x2c09 SPI_SHADER_PGM_HI_PS */
1565 /* multiplicator 9 is from SPI_SHADER_COL_FORMAT */
1566 if (!test_priv->info->hang)
1567 shader_addr += 256 * 9;
1568 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 3);
1569 ptr[i++] = 0x7;
1570 ptr[i++] = 0xffff;
1571 ptr[i++] = shader_addr >> 8;
1572 ptr[i++] = shader_addr >> 40;
1573 } else {
1574 //if (!test_priv->info->hang)
1575 shader_addr += 256 * 9;
1576 /* 0x2c08 SPI_SHADER_PGM_LO_PS
1577 0x2c09 SPI_SHADER_PGM_HI_PS */
1578 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 2);
1579 ptr[i++] = 0x8;
1580 ptr[i++] = shader_addr >> 8;
1581 ptr[i++] = shader_addr >> 40;
1582
1583 /* mmSPI_SHADER_PGM_RSRC3_PS */
1584 ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1);
1585 ptr[i++] = 0x30000007;
1586 ptr[i++] = 0xffff;
1587 /* mmSPI_SHADER_PGM_RSRC4_PS */
1588 ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1);
1589 ptr[i++] = 0x30000001;
1590 ptr[i++] = 0xffff;
1591 }
1592
1593 for (j = 0; j < ps->num_sh_reg; j++) {
1594 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1);
1595 ptr[i++] = ps->sh_reg[j].reg_offset - 0x2c00;
1596 ptr[i++] = ps->sh_reg[j].reg_value;
1597 }
1598
1599 for (j = 0; j < ps->num_context_reg; j++) {
1600 if (ps->context_reg[j].reg_offset != 0xA1C5) {
1601 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1602 ptr[i++] = ps->context_reg[j].reg_offset - 0xa000;
1603 ptr[i++] = ps->context_reg[j].reg_value;
1604 }
1605
1606 if (ps->context_reg[j].reg_offset == 0xA1B4) {
1607 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1608 ptr[i++] = 0x1b3;
1609 ptr[i++] = 2;
1610 }
1611 }
1612
1613 test_priv->cmd_curr = i;
1614 }
1615
amdgpu_draw_ps_write2hw_gfx11(struct shader_test_priv * test_priv)1616 static void amdgpu_draw_ps_write2hw_gfx11(struct shader_test_priv *test_priv)
1617 {
1618 int i, j;
1619 uint64_t shader_addr = test_priv->shader_draw.ps_bo.mc_address;
1620 enum amdgpu_test_gfx_version version = test_priv->info->version;
1621 const struct shader_test_ps_shader *ps = &shader_test_ps[version][test_priv->shader_draw.ps_type];
1622 uint32_t *ptr = test_priv->cmd.ptr;
1623 uint32_t export_shader_offset;
1624
1625 i = test_priv->cmd_curr;
1626
1627 /* SPI_SHADER_PGM_LO_PS
1628 SPI_SHADER_PGM_HI_PS */
1629 shader_addr >>= 8;
1630 if (!test_priv->info->hang) {
1631 export_shader_offset = (round_up_size(ps->shader_size) * 9) >> 8;
1632 shader_addr += export_shader_offset;
1633 }
1634 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 2);
1635 ptr[i++] = 0x8;
1636 ptr[i++] = shader_addr & 0xffffffff;
1637 ptr[i++] = (shader_addr >> 32) & 0xffffffff;
1638 /* mmSPI_SHADER_PGM_RSRC3_PS */
1639 ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1);
1640 ptr[i++] = 0x30000007;
1641 ptr[i++] = 0xffff;
1642 /* mmSPI_SHADER_PGM_RSRC4_PS */
1643 ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1);
1644 ptr[i++] = 0x30000001;
1645 ptr[i++] = 0x3fffff;
1646
1647 for (j = 0; j < ps->num_sh_reg; j++) {
1648 ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1);
1649 ptr[i++] = ps->sh_reg[j].reg_offset - shader_test_gfx_info[version].sh_reg_base;
1650 ptr[i++] = ps->sh_reg[j].reg_value;
1651 }
1652
1653 for (j = 0; j < ps->num_context_reg; j++) {
1654 /* !mmSPI_SHADER_COL_FORMAT */
1655 if (ps->context_reg[j].reg_offset != 0xA1C5) {
1656 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1657 ptr[i++] = ps->context_reg[j].reg_offset - shader_test_gfx_info[version].context_reg_base;
1658 ptr[i++] = ps->context_reg[j].reg_value;
1659 }
1660
1661 /* mmSPI_PS_INPUT_ADDR */
1662 if (ps->context_reg[j].reg_offset == 0xA1B4) {
1663 ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
1664 ptr[i++] = 0x1b3;
1665 ptr[i++] = 2;
1666 }
1667 }
1668
1669 test_priv->cmd_curr = i;
1670 }
1671
amdgpu_draw_ps_write2hw(struct shader_test_priv * test_priv)1672 static void amdgpu_draw_ps_write2hw(struct shader_test_priv *test_priv)
1673 {
1674 switch (test_priv->info->version) {
1675 case AMDGPU_TEST_GFX_V9:
1676 case AMDGPU_TEST_GFX_V10:
1677 amdgpu_draw_ps_write2hw_gfx9_10(test_priv);
1678 break;
1679 case AMDGPU_TEST_GFX_V11:
1680 amdgpu_draw_ps_write2hw_gfx11(test_priv);
1681 break;
1682 }
1683 }
1684
amdgpu_draw_draw(struct shader_test_priv * test_priv)1685 static void amdgpu_draw_draw(struct shader_test_priv *test_priv)
1686 {
1687 int i = test_priv->cmd_curr;
1688 uint32_t *ptr = test_priv->cmd.ptr;
1689
1690 switch (test_priv->info->version) {
1691 case AMDGPU_TEST_GFX_V9:
1692 /* mmIA_MULTI_VGT_PARAM */
1693 ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
1694 ptr[i++] = 0x40000258;
1695 ptr[i++] = 0xd00ff;
1696 /* mmVGT_PRIMITIVE_TYPE */
1697 ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
1698 ptr[i++] = 0x10000242;
1699 ptr[i++] = 0x11;
1700 break;
1701 case AMDGPU_TEST_GFX_V10:
1702 /* mmGE_CNTL */
1703 ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
1704 ptr[i++] = 0x25b;
1705 ptr[i++] = 0xff;
1706 /* mmVGT_PRIMITIVE_TYPE */
1707 ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
1708 ptr[i++] = 0x242;
1709 ptr[i++] = 0x11;
1710 break;
1711 case AMDGPU_TEST_GFX_V11:
1712 /* mmGE_CNTL */
1713 ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
1714 ptr[i++] = 0x25b;
1715 ptr[i++] = 0x80fc80;
1716 /* mmVGT_PRIMITIVE_TYPE */
1717 ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
1718 ptr[i++] = 0x242;
1719 ptr[i++] = 0x11;
1720 break;
1721 }
1722
1723 ptr[i++] = PACKET3(PACKET3_DRAW_INDEX_AUTO, 1);
1724 ptr[i++] = 3;
1725 ptr[i++] = 2;
1726
1727 test_priv->cmd_curr = i;
1728 }
1729
amdgpu_memset_draw_test(struct shader_test_info * test_info)1730 static void amdgpu_memset_draw_test(struct shader_test_info *test_info)
1731 {
1732 struct shader_test_priv test_priv;
1733 amdgpu_context_handle context_handle;
1734 struct shader_test_bo *ps_bo = &(test_priv.shader_draw.ps_bo);
1735 struct shader_test_bo *vs_bo = &(test_priv.shader_draw.vs_bo);
1736 struct shader_test_bo *dst = &(test_priv.dst);
1737 struct shader_test_bo *cmd = &(test_priv.cmd);
1738 struct shader_test_bo *vtx_attributes_mem = &(test_priv.vtx_attributes_mem);
1739 amdgpu_bo_handle resources[5];
1740 uint8_t *ptr_dst;
1741 uint32_t *ptr_cmd;
1742 int i, r;
1743 struct amdgpu_cs_request ibs_request = {0};
1744 struct amdgpu_cs_ib_info ib_info = {0};
1745 struct amdgpu_cs_fence fence_status = {0};
1746 uint32_t expired;
1747 amdgpu_bo_list_handle bo_list;
1748 uint8_t cptr[16];
1749
1750 memset(&test_priv, 0, sizeof(test_priv));
1751 test_priv.info = test_info;
1752
1753 r = amdgpu_cs_ctx_create(test_info->device_handle, &context_handle);
1754 CU_ASSERT_EQUAL(r, 0);
1755
1756 ps_bo->size = 0x2000;
1757 ps_bo->heap = AMDGPU_GEM_DOMAIN_VRAM;
1758 r = shader_test_bo_alloc(test_info->device_handle, ps_bo);
1759 CU_ASSERT_EQUAL(r, 0);
1760 memset(ps_bo->ptr, 0, ps_bo->size);
1761
1762 vs_bo->size = 4096;
1763 vs_bo->heap = AMDGPU_GEM_DOMAIN_VRAM;
1764 r = shader_test_bo_alloc(test_info->device_handle, vs_bo);
1765 CU_ASSERT_EQUAL(r, 0);
1766 memset(vs_bo->ptr, 0, vs_bo->size);
1767
1768 test_priv.shader_draw.ps_type = PS_CONST;
1769 amdgpu_draw_load_ps_shader(&test_priv);
1770
1771 test_priv.shader_draw.vs_type = VS_RECTPOSTEXFAST;
1772 amdgpu_draw_load_vs_shader(&test_priv);
1773
1774 cmd->size = 4096;
1775 cmd->heap = AMDGPU_GEM_DOMAIN_GTT;
1776 r = shader_test_bo_alloc(test_info->device_handle, cmd);
1777 CU_ASSERT_EQUAL(r, 0);
1778 ptr_cmd = cmd->ptr;
1779 memset(ptr_cmd, 0, cmd->size);
1780
1781 dst->size = 0x4000;
1782 dst->heap = AMDGPU_GEM_DOMAIN_VRAM;
1783 r = shader_test_bo_alloc(test_info->device_handle, dst);
1784 CU_ASSERT_EQUAL(r, 0);
1785
1786 if (test_info->version == AMDGPU_TEST_GFX_V11) {
1787 vtx_attributes_mem->size = 0x4040000;
1788 vtx_attributes_mem->heap = AMDGPU_GEM_DOMAIN_VRAM;
1789
1790 r = shader_test_bo_alloc(test_info->device_handle, vtx_attributes_mem);
1791 CU_ASSERT_EQUAL(r, 0);
1792 }
1793
1794 amdgpu_draw_init(&test_priv);
1795
1796 amdgpu_draw_setup_and_write_drawblt_surf_info(&test_priv);
1797
1798 amdgpu_draw_setup_and_write_drawblt_state(&test_priv);
1799
1800 amdgpu_draw_vs_RectPosTexFast_write2hw(&test_priv);
1801
1802 amdgpu_draw_ps_write2hw(&test_priv);
1803
1804 i = test_priv.cmd_curr;
1805 /* ps constant data */
1806 ptr_cmd[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
1807 ptr_cmd[i++] = 0xc;
1808 ptr_cmd[i++] = 0x33333333;
1809 ptr_cmd[i++] = 0x33333333;
1810 ptr_cmd[i++] = 0x33333333;
1811 ptr_cmd[i++] = 0x33333333;
1812 test_priv.cmd_curr = i;
1813
1814 amdgpu_draw_draw(&test_priv);
1815
1816 i = test_priv.cmd_curr;
1817 while (i & 7)
1818 ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
1819 test_priv.cmd_curr = i;
1820
1821 i = 0;
1822 resources[i++] = dst->bo;
1823 resources[i++] = ps_bo->bo;
1824 resources[i++] = vs_bo->bo;
1825 resources[i++] = cmd->bo;
1826 if (vtx_attributes_mem->size)
1827 resources[i++] = vtx_attributes_mem->bo;
1828 r = amdgpu_bo_list_create(test_info->device_handle, i, resources, NULL, &bo_list);
1829 CU_ASSERT_EQUAL(r, 0);
1830
1831 ib_info.ib_mc_address = cmd->mc_address;
1832 ib_info.size = test_priv.cmd_curr;
1833 ibs_request.ip_type = test_info->ip;
1834 ibs_request.ring = test_info->ring;
1835 ibs_request.resources = bo_list;
1836 ibs_request.number_of_ibs = 1;
1837 ibs_request.ibs = &ib_info;
1838 ibs_request.fence_info.handle = NULL;
1839
1840 /* submit CS */
1841 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
1842 CU_ASSERT_EQUAL(r, 0);
1843
1844 r = amdgpu_bo_list_destroy(bo_list);
1845 CU_ASSERT_EQUAL(r, 0);
1846
1847 fence_status.ip_type = test_info->ip;
1848 fence_status.ip_instance = 0;
1849 fence_status.ring = test_info->ring;
1850 fence_status.context = context_handle;
1851 fence_status.fence = ibs_request.seq_no;
1852
1853 /* wait for IB accomplished */
1854 r = amdgpu_cs_query_fence_status(&fence_status,
1855 AMDGPU_TIMEOUT_INFINITE,
1856 0, &expired);
1857 CU_ASSERT_EQUAL(r, 0);
1858 CU_ASSERT_EQUAL(expired, true);
1859
1860 /* verify if memset test result meets with expected */
1861 i = 0;
1862 ptr_dst = dst->ptr;
1863 memset(cptr, 0x33, 16);
1864 CU_ASSERT_EQUAL(memcmp(ptr_dst + i, cptr, 16), 0);
1865 i = dst->size - 16;
1866 CU_ASSERT_EQUAL(memcmp(ptr_dst + i, cptr, 16), 0);
1867 i = dst->size / 2;
1868 CU_ASSERT_EQUAL(memcmp(ptr_dst + i, cptr, 16), 0);
1869
1870 if (vtx_attributes_mem->size) {
1871 r = shader_test_bo_free(vtx_attributes_mem);
1872 CU_ASSERT_EQUAL(r, 0);
1873 }
1874
1875 r = shader_test_bo_free(dst);
1876 CU_ASSERT_EQUAL(r, 0);
1877
1878 r = shader_test_bo_free(cmd);
1879 CU_ASSERT_EQUAL(r, 0);
1880
1881 r = shader_test_bo_free(ps_bo);
1882 CU_ASSERT_EQUAL(r, 0);
1883
1884 r = shader_test_bo_free(vs_bo);
1885 CU_ASSERT_EQUAL(r, 0);
1886
1887 r = amdgpu_cs_ctx_free(context_handle);
1888 CU_ASSERT_EQUAL(r, 0);
1889 }
1890
amdgpu_memcpy_draw_test(struct shader_test_info * test_info)1891 static void amdgpu_memcpy_draw_test(struct shader_test_info *test_info)
1892 {
1893 struct shader_test_priv test_priv;
1894 amdgpu_context_handle context_handle;
1895 struct shader_test_bo *ps_bo = &(test_priv.shader_draw.ps_bo);
1896 struct shader_test_bo *vs_bo = &(test_priv.shader_draw.vs_bo);
1897 struct shader_test_bo *src = &(test_priv.src);
1898 struct shader_test_bo *dst = &(test_priv.dst);
1899 struct shader_test_bo *cmd = &(test_priv.cmd);
1900 struct shader_test_bo *vtx_attributes_mem = &(test_priv.vtx_attributes_mem);
1901 amdgpu_bo_handle resources[6];
1902 uint8_t *ptr_dst;
1903 uint8_t *ptr_src;
1904 uint32_t *ptr_cmd;
1905 int i, r;
1906 struct amdgpu_cs_request ibs_request = {0};
1907 struct amdgpu_cs_ib_info ib_info = {0};
1908 uint32_t hang_state, hangs;
1909 uint32_t expired;
1910 amdgpu_bo_list_handle bo_list;
1911 struct amdgpu_cs_fence fence_status = {0};
1912
1913 memset(&test_priv, 0, sizeof(test_priv));
1914 test_priv.info = test_info;
1915 test_priv.cmd.size = 4096;
1916 test_priv.cmd.heap = AMDGPU_GEM_DOMAIN_GTT;
1917
1918 ps_bo->heap = AMDGPU_GEM_DOMAIN_VRAM;
1919 test_priv.shader_draw.ps_type = PS_TEX;
1920 vs_bo->size = 4096;
1921 vs_bo->heap = AMDGPU_GEM_DOMAIN_VRAM;
1922 test_priv.shader_draw.vs_type = VS_RECTPOSTEXFAST;
1923 test_priv.src.heap = AMDGPU_GEM_DOMAIN_VRAM;
1924 test_priv.dst.heap = AMDGPU_GEM_DOMAIN_VRAM;
1925 if (test_info->hang_slow) {
1926 test_priv.shader_draw.ps_bo.size = 16*1024*1024;
1927 test_priv.src.size = 0x4000000;
1928 test_priv.dst.size = 0x4000000;
1929 } else {
1930 test_priv.shader_draw.ps_bo.size = 0x2000;
1931 test_priv.src.size = 0x4000;
1932 test_priv.dst.size = 0x4000;
1933 }
1934
1935 r = amdgpu_cs_ctx_create(test_info->device_handle, &context_handle);
1936 CU_ASSERT_EQUAL(r, 0);
1937
1938 r = shader_test_bo_alloc(test_info->device_handle, ps_bo);
1939 CU_ASSERT_EQUAL(r, 0);
1940 memset(ps_bo->ptr, 0, ps_bo->size);
1941
1942 r = shader_test_bo_alloc(test_info->device_handle, vs_bo);
1943 CU_ASSERT_EQUAL(r, 0);
1944 memset(vs_bo->ptr, 0, vs_bo->size);
1945
1946 amdgpu_draw_load_ps_shader(&test_priv);
1947 amdgpu_draw_load_vs_shader(&test_priv);
1948
1949 r = shader_test_bo_alloc(test_info->device_handle, cmd);
1950 CU_ASSERT_EQUAL(r, 0);
1951 ptr_cmd = cmd->ptr;
1952 memset(ptr_cmd, 0, cmd->size);
1953
1954 r = shader_test_bo_alloc(test_info->device_handle, src);
1955 CU_ASSERT_EQUAL(r, 0);
1956 ptr_src = src->ptr;
1957 memset(ptr_src, 0x55, src->size);
1958
1959 r = shader_test_bo_alloc(test_info->device_handle, dst);
1960 CU_ASSERT_EQUAL(r, 0);
1961
1962 if (test_info->version == AMDGPU_TEST_GFX_V11) {
1963 vtx_attributes_mem->size = 0x4040000;
1964 vtx_attributes_mem->heap = AMDGPU_GEM_DOMAIN_VRAM;
1965
1966 r = shader_test_bo_alloc(test_info->device_handle, vtx_attributes_mem);
1967 CU_ASSERT_EQUAL(r, 0);
1968 }
1969
1970 amdgpu_draw_init(&test_priv);
1971
1972 amdgpu_draw_setup_and_write_drawblt_surf_info(&test_priv);
1973
1974 amdgpu_draw_setup_and_write_drawblt_state(&test_priv);
1975
1976 amdgpu_draw_vs_RectPosTexFast_write2hw(&test_priv);
1977
1978 amdgpu_draw_ps_write2hw(&test_priv);
1979
1980 // write ps user constant data
1981 i = test_priv.cmd_curr;
1982 ptr_cmd[i++] = PACKET3(PACKET3_SET_SH_REG, 8);
1983 switch (test_info->version) {
1984 case AMDGPU_TEST_GFX_V9:
1985 ptr_cmd[i++] = 0xc;
1986 ptr_cmd[i++] = src->mc_address >> 8;
1987 ptr_cmd[i++] = src->mc_address >> 40 | 0x10e00000;
1988 ptr_cmd[i++] = test_info->hang_slow ? 0x1ffcfff : 0x7c01f;
1989 ptr_cmd[i++] = 0x90500fac;
1990 ptr_cmd[i++] = test_info->hang_slow ? 0x1ffe000 : 0x3e000;
1991 i += 3;
1992 break;
1993 case AMDGPU_TEST_GFX_V10:
1994 ptr_cmd[i++] = 0xc;
1995 ptr_cmd[i++] = src->mc_address >> 8;
1996 ptr_cmd[i++] = src->mc_address >> 40 | 0xc4b00000;
1997 ptr_cmd[i++] = test_info->hang_slow ? 0x81ffc1ff : 0x8007c007;
1998 ptr_cmd[i++] = 0x90500fac;
1999 i += 2;
2000 ptr_cmd[i++] = test_info->hang_slow ? 0 : 0x400;
2001 i++;
2002 break;
2003 case AMDGPU_TEST_GFX_V11:
2004 ptr_cmd[i++] = 0xc;
2005 ptr_cmd[i++] = src->mc_address >> 8;
2006 ptr_cmd[i++] = src->mc_address >> 40 | 0xc4b00000;
2007 ptr_cmd[i++] = test_info->hang_slow ? 0x1ffc1ff : 0x7c007;
2008 ptr_cmd[i++] = test_info->hang_slow ? 0x90a00fac : 0x90600fac;
2009 i += 2;
2010 ptr_cmd[i++] = 0x400;
2011 i++;
2012 break;
2013 }
2014
2015 ptr_cmd[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
2016 ptr_cmd[i++] = 0x14;
2017 ptr_cmd[i++] = 0x92;
2018 i += 3;
2019
2020 ptr_cmd[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
2021 ptr_cmd[i++] = 0x191;
2022 ptr_cmd[i++] = 0;
2023 test_priv.cmd_curr = i;
2024
2025 amdgpu_draw_draw(&test_priv);
2026
2027 i = test_priv.cmd_curr;
2028 while (i & 7)
2029 ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
2030 test_priv.cmd_curr = i;
2031
2032 i = 0;
2033 resources[i++] = dst->bo;
2034 resources[i++] = src->bo;
2035 resources[i++] = ps_bo->bo;
2036 resources[i++] = vs_bo->bo;
2037 resources[i++] = cmd->bo;
2038 if (vtx_attributes_mem->size)
2039 resources[i++] = vtx_attributes_mem->bo;
2040 r = amdgpu_bo_list_create(test_info->device_handle, i, resources, NULL, &bo_list);
2041 CU_ASSERT_EQUAL(r, 0);
2042
2043 ib_info.ib_mc_address = cmd->mc_address;
2044 ib_info.size = test_priv.cmd_curr;
2045 ibs_request.ip_type = test_info->ip;
2046 ibs_request.ring = test_info->ring;
2047 ibs_request.resources = bo_list;
2048 ibs_request.number_of_ibs = 1;
2049 ibs_request.ibs = &ib_info;
2050 ibs_request.fence_info.handle = NULL;
2051 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
2052 CU_ASSERT_EQUAL(r, 0);
2053
2054 fence_status.ip_type = test_info->ip;
2055 fence_status.ip_instance = 0;
2056 fence_status.ring = test_info->ring;
2057 fence_status.context = context_handle;
2058 fence_status.fence = ibs_request.seq_no;
2059
2060 /* wait for IB accomplished */
2061 r = amdgpu_cs_query_fence_status(&fence_status,
2062 AMDGPU_TIMEOUT_INFINITE,
2063 0, &expired);
2064 if (!test_info->hang) {
2065 CU_ASSERT_EQUAL(r, 0);
2066 CU_ASSERT_EQUAL(expired, true);
2067
2068 /* verify if memcpy test result meets with expected */
2069 i = 0;
2070 ptr_dst = dst->ptr;
2071 CU_ASSERT_EQUAL(memcmp(ptr_dst + i, ptr_src + i, 16), 0);
2072 i = dst->size - 16;
2073 CU_ASSERT_EQUAL(memcmp(ptr_dst + i, ptr_src + i, 16), 0);
2074 i = dst->size / 2;
2075 CU_ASSERT_EQUAL(memcmp(ptr_dst + i, ptr_src + i, 16), 0);
2076 } else {
2077 r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs);
2078 CU_ASSERT_EQUAL(r, 0);
2079 CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET);
2080 }
2081
2082 r = amdgpu_bo_list_destroy(bo_list);
2083 CU_ASSERT_EQUAL(r, 0);
2084
2085 if (vtx_attributes_mem->size) {
2086 r = shader_test_bo_free(vtx_attributes_mem);
2087 CU_ASSERT_EQUAL(r, 0);
2088 }
2089
2090 r = shader_test_bo_free(src);
2091 CU_ASSERT_EQUAL(r, 0);
2092
2093 r = shader_test_bo_free(dst);
2094 CU_ASSERT_EQUAL(r, 0);
2095
2096 r = shader_test_bo_free(cmd);
2097 CU_ASSERT_EQUAL(r, 0);
2098
2099 r = shader_test_bo_free(ps_bo);
2100 CU_ASSERT_EQUAL(r, 0);
2101
2102 r = shader_test_bo_free(vs_bo);
2103 CU_ASSERT_EQUAL(r, 0);
2104
2105 r = amdgpu_cs_ctx_free(context_handle);
2106 CU_ASSERT_EQUAL(r, 0);
2107 }
2108
shader_test_draw_cb(struct shader_test_info * test_info)2109 static void shader_test_draw_cb(struct shader_test_info *test_info)
2110 {
2111 amdgpu_memset_draw_test(test_info);
2112 amdgpu_memcpy_draw_test(test_info);
2113 }
2114
shader_test_draw_hang_cb(struct shader_test_info * test_info)2115 static void shader_test_draw_hang_cb(struct shader_test_info *test_info)
2116 {
2117 test_info->hang = 0;
2118 amdgpu_memcpy_draw_test(test_info);
2119
2120 test_info->hang = 1;
2121 amdgpu_memcpy_draw_test(test_info);
2122
2123 test_info->hang = 0;
2124 amdgpu_memcpy_draw_test(test_info);
2125 }
2126
shader_test_draw_hang_slow_cb(struct shader_test_info * test_info)2127 static void shader_test_draw_hang_slow_cb(struct shader_test_info *test_info)
2128 {
2129 test_info->hang = 0;
2130 test_info->hang_slow = 0;
2131 amdgpu_memcpy_draw_test(test_info);
2132
2133 test_info->hang = 1;
2134 test_info->hang_slow = 1;
2135 amdgpu_memcpy_draw_test(test_info);
2136
2137 test_info->hang = 0;
2138 test_info->hang_slow = 0;
2139 amdgpu_memcpy_draw_test(test_info);
2140 }
2141
2142
amdgpu_test_draw_helper(amdgpu_device_handle device_handle)2143 void amdgpu_test_draw_helper(amdgpu_device_handle device_handle)
2144 {
2145 shader_test_for_each(device_handle, AMDGPU_HW_IP_GFX, shader_test_draw_cb);
2146 }
2147
amdgpu_test_draw_hang_helper(amdgpu_device_handle device_handle)2148 void amdgpu_test_draw_hang_helper(amdgpu_device_handle device_handle)
2149 {
2150 shader_test_for_each(device_handle, AMDGPU_HW_IP_GFX, shader_test_draw_hang_cb);
2151 }
2152
amdgpu_test_draw_hang_slow_helper(amdgpu_device_handle device_handle)2153 void amdgpu_test_draw_hang_slow_helper(amdgpu_device_handle device_handle)
2154 {
2155 shader_test_for_each(device_handle, AMDGPU_HW_IP_GFX, shader_test_draw_hang_slow_cb);
2156 }
2157