1 /* 2 * Copyright © 2017 Advanced Micro Devices, Inc. 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef AC_GPU_INFO_H 8 #define AC_GPU_INFO_H 9 10 #include <stdbool.h> 11 #include "util/macros.h" 12 #include "amd_family.h" 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 #define AMD_MAX_SE 32 19 #define AMD_MAX_SA_PER_SE 2 20 #define AMD_MAX_WGP 60 21 22 struct amdgpu_gpu_info; 23 24 struct amd_ip_info { 25 uint8_t ver_major; 26 uint8_t ver_minor; 27 uint8_t ver_rev; 28 uint8_t num_queues; 29 uint8_t num_instances; 30 uint32_t ib_alignment; 31 uint32_t ib_pad_dw_mask; 32 }; 33 34 struct radeon_info { 35 /* Device info. */ 36 const char *name; 37 char lowercase_name[32]; 38 const char *marketing_name; 39 char dev_filename[32]; 40 uint32_t num_se; /* only enabled SEs */ 41 uint32_t num_rb; /* only enabled RBs */ 42 uint32_t num_cu; /* only enabled CUs */ 43 uint32_t max_gpu_freq_mhz; /* also known as the shader clock */ 44 uint32_t max_gflops; 45 uint32_t sqc_inst_cache_size; 46 uint32_t sqc_scalar_cache_size; 47 uint32_t num_sqc_per_wgp; 48 uint32_t tcp_cache_size; 49 uint32_t l1_cache_size; 50 uint32_t l2_cache_size; 51 uint32_t l3_cache_size_mb; 52 uint32_t num_tcc_blocks; /* also the number of memory channels */ 53 uint32_t memory_freq_mhz; 54 uint32_t memory_freq_mhz_effective; 55 uint32_t memory_bus_width; 56 uint32_t memory_bandwidth_gbps; 57 uint32_t pcie_gen; 58 uint32_t pcie_num_lanes; 59 uint32_t pcie_bandwidth_mbps; 60 uint32_t clock_crystal_freq; 61 struct amd_ip_info ip[AMD_NUM_IP_TYPES]; 62 63 /* Identification. */ 64 /* PCI info: domain:bus:dev:func */ 65 struct { 66 uint32_t domain; 67 uint32_t bus; 68 uint32_t dev; 69 uint32_t func; 70 bool valid; 71 } pci; 72 73 uint32_t pci_id; 74 uint32_t pci_rev_id; 75 enum radeon_family family; 76 enum amd_gfx_level gfx_level; 77 uint32_t family_id; 78 uint32_t chip_external_rev; 79 uint32_t chip_rev; /* 0 = A0, 1 = A1, etc. */ 80 81 /* Flags. */ 82 bool family_overridden; /* AMD_FORCE_FAMILY was used, skip command submission */ 83 bool is_pro_graphics; 84 bool has_graphics; /* false if the chip is compute-only */ 85 bool has_clear_state; 86 bool has_distributed_tess; 87 bool has_dcc_constant_encode; 88 bool has_tc_compatible_htile; 89 bool has_etc_support; 90 bool has_rbplus; /* if RB+ registers exist */ 91 bool rbplus_allowed; /* if RB+ is allowed */ 92 bool has_load_ctx_reg_pkt; 93 bool has_out_of_order_rast; 94 bool has_packed_math_16bit; 95 bool has_accelerated_dot_product; 96 bool cpdma_prefetch_writes_memory; 97 bool has_gfx9_scissor_bug; 98 bool has_tc_compat_zrange_bug; 99 bool has_small_prim_filter_sample_loc_bug; 100 bool has_ls_vgpr_init_bug; 101 bool has_pops_missed_overlap_bug; 102 bool has_null_index_buffer_clamping_bug; 103 bool has_zero_index_buffer_bug; 104 bool has_image_load_dcc_bug; 105 bool has_two_planes_iterate256_bug; 106 bool has_vgt_flush_ngg_legacy_bug; 107 bool has_cs_regalloc_hang_bug; 108 bool has_async_compute_threadgroup_bug; 109 bool has_async_compute_align32_bug; 110 bool has_32bit_predication; 111 bool has_3d_cube_border_color_mipmap; 112 bool has_image_opcodes; 113 bool never_stop_sq_perf_counters; 114 bool has_sqtt_rb_harvest_bug; 115 bool has_sqtt_auto_flush_mode_bug; 116 bool never_send_perfcounter_stop; 117 bool discardable_allows_big_page; 118 bool has_ngg_fully_culled_bug; 119 bool has_ngg_passthru_no_msg; 120 bool has_export_conflict_bug; 121 bool has_attr_ring_wait_bug; 122 bool has_vrs_ds_export_bug; 123 bool has_taskmesh_indirect0_bug; 124 bool sdma_supports_sparse; /* Whether SDMA can safely access sparse resources. */ 125 bool sdma_supports_compression; /* Whether SDMA supports DCC and HTILE. */ 126 bool has_set_context_pairs; 127 bool has_set_context_pairs_packed; 128 bool has_set_sh_pairs; 129 bool has_set_sh_pairs_packed; 130 bool has_set_uconfig_pairs; 131 bool needs_llvm_wait_wa; /* True if the chip needs to workarounds based on s_waitcnt_deptr but 132 * the LLVM version doesn't work with multiparts shaders. 133 */ 134 135 /* conformant_trunc_coord is equal to TA_CNTL2.TRUNCATE_COORD_MODE, which exists since gfx11. 136 * 137 * If TA_CNTL2.TRUNCATE_COORD_MODE == 0, coordinate truncation is the same as gfx10 and older. 138 * 139 * If TA_CNTL2.TRUNCATE_COORD_MODE == 1, coordinate truncation is adjusted to be D3D9/GL/Vulkan 140 * conformant if you also set TRUNC_COORD. Coordinate truncation uses D3D10+ behaviour if 141 * TRUNC_COORD is unset. 142 * 143 * Behavior if TA_CNTL2.TRUNCATE_COORD_MODE == 1: 144 * truncate_coord_xy = TRUNC_COORD && (xy_filter == Point && !gather); 145 * truncate_coord_z = TRUNC_COORD && (z_filter == Point); 146 * truncate_coord_layer = false; 147 * 148 * Behavior if TA_CNTL2.TRUNCATE_COORD_MODE == 0: 149 * truncate_coord_xy = TRUNC_COORD; 150 * truncate_coord_z = TRUNC_COORD; 151 * truncate_coord_layer = TRUNC_COORD; 152 * 153 * AnisoPoint is treated as Point. 154 */ 155 bool conformant_trunc_coord; 156 157 /* Display features. */ 158 /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ 159 /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ 160 bool use_display_dcc_unaligned; 161 /* Allocate both aligned and unaligned DCC and use the retile blit. */ 162 bool use_display_dcc_with_retile_blit; 163 bool gfx12_supports_display_dcc; 164 bool gfx12_supports_dcc_write_compress_disable; 165 166 /* Memory info. */ 167 uint32_t pte_fragment_size; 168 uint32_t gart_page_size; 169 uint32_t gart_size_kb; 170 uint32_t vram_size_kb; 171 uint64_t vram_vis_size_kb; 172 uint32_t vram_type; 173 uint32_t max_heap_size_kb; 174 uint32_t min_alloc_size; 175 uint32_t address32_hi; 176 bool has_dedicated_vram; 177 bool all_vram_visible; 178 bool has_l2_uncached; 179 bool r600_has_virtual_memory; 180 uint32_t max_tcc_blocks; 181 uint32_t tcc_cache_line_size; 182 bool tcc_rb_non_coherent; /* whether L2 inv is needed for render->texture transitions */ 183 bool cp_sdma_ge_use_system_memory_scope; 184 bool cp_dma_use_L2; 185 unsigned pc_lines; 186 uint32_t lds_size_per_workgroup; 187 uint32_t lds_alloc_granularity; 188 uint32_t lds_encode_granularity; 189 190 /* CP info. */ 191 bool gfx_ib_pad_with_type2; 192 bool has_cp_dma; 193 uint32_t me_fw_version; 194 uint32_t me_fw_feature; 195 uint32_t mec_fw_version; 196 uint32_t mec_fw_feature; 197 uint32_t pfp_fw_version; 198 uint32_t pfp_fw_feature; 199 200 /* Multimedia info. */ 201 uint32_t uvd_fw_version; 202 uint32_t vce_fw_version; 203 uint32_t vce_harvest_config; 204 uint32_t vcn_dec_version; 205 uint32_t vcn_enc_major_version; 206 uint32_t vcn_enc_minor_version; 207 struct video_caps_info { 208 struct video_codec_cap { 209 uint32_t valid; 210 uint32_t max_width; 211 uint32_t max_height; 212 uint32_t max_pixels_per_frame; 213 uint32_t max_level; 214 uint32_t pad; 215 } codec_info[8]; /* the number of available codecs */ 216 } dec_caps, enc_caps; 217 218 enum vcn_version vcn_ip_version; 219 enum sdma_version sdma_ip_version; 220 221 /* Kernel & winsys capabilities. */ 222 uint32_t drm_major; /* version */ 223 uint32_t drm_minor; 224 uint32_t drm_patchlevel; 225 uint32_t max_submitted_ibs[AMD_NUM_IP_TYPES]; 226 bool is_amdgpu; 227 bool is_virtio; 228 bool has_userptr; 229 bool has_syncobj; 230 bool has_timeline_syncobj; 231 bool has_fence_to_handle; 232 bool has_local_buffers; 233 bool has_bo_metadata; 234 bool has_eqaa_surface_allocator; 235 bool has_sparse_vm_mappings; 236 bool has_scheduled_fence_dependency; 237 bool has_gang_submit; 238 bool has_gpuvm_fault_query; 239 bool has_pcie_bandwidth_info; 240 bool has_stable_pstate; 241 /* Whether SR-IOV is enabled or amdgpu.mcbp=1 was set on the kernel command line. */ 242 bool register_shadowing_required; 243 bool has_tmz_support; 244 bool has_trap_handler_support; 245 bool kernel_has_modifiers; 246 bool use_userq; 247 248 /* If the kernel driver uses CU reservation for high priority compute on gfx10+, it programs 249 * a global CU mask in the hw that is AND'ed with CU_EN register fields set by userspace. 250 * The packet that does the AND'ing is SET_SH_REG_INDEX(index = 3). If you don't use 251 * SET_SH_REG_INDEX, the global CU mask will not be applied. 252 * 253 * If uses_kernel_cu_mask is true, use SET_SH_REG_INDEX. 254 * 255 * If uses_kernel_cu_mask is false, SET_SH_REG_INDEX shouldn't be used because it only 256 * increases CP overhead and doesn't have any other effect. 257 * 258 * The alternative to this is to set the AMD_CU_MASK environment variable that has the same 259 * effect on radeonsi and RADV and doesn't need SET_SH_REG_INDEX. 260 */ 261 bool uses_kernel_cu_mask; 262 263 /* Shader cores. */ 264 uint16_t cu_mask[AMD_MAX_SE][AMD_MAX_SA_PER_SE]; 265 uint32_t r600_max_quad_pipes; /* wave size / 16 */ 266 uint32_t max_good_cu_per_sa; 267 uint32_t min_good_cu_per_sa; /* min != max if SAs have different # of CUs */ 268 uint32_t max_se; /* number of shader engines incl. disabled ones */ 269 uint32_t max_sa_per_se; /* shader arrays per shader engine */ 270 uint32_t num_cu_per_sh; 271 uint32_t max_waves_per_simd; 272 uint32_t num_physical_sgprs_per_simd; 273 uint32_t num_physical_wave64_vgprs_per_simd; 274 uint32_t num_simd_per_compute_unit; 275 uint32_t min_sgpr_alloc; 276 uint32_t max_sgpr_alloc; 277 uint32_t sgpr_alloc_granularity; 278 uint32_t min_wave64_vgpr_alloc; 279 uint32_t max_vgpr_alloc; 280 uint32_t wave64_vgpr_alloc_granularity; 281 uint32_t max_scratch_waves; 282 bool has_scratch_base_registers; 283 284 /* Pos, prim, and attribute rings. */ 285 uint32_t attribute_ring_size_per_se; /* GFX11+ */ 286 uint32_t pos_ring_size_per_se; /* GFX12+ */ 287 uint32_t prim_ring_size_per_se; /* GFX12+ */ 288 uint32_t pos_ring_offset; /* GFX12+ */ 289 uint32_t prim_ring_offset; /* GFX12+ */ 290 uint32_t total_attribute_pos_prim_ring_size; /* GFX11+ */ 291 bool has_attr_ring; 292 293 /* Render backends (color + depth blocks). */ 294 uint32_t r300_num_gb_pipes; 295 uint32_t r300_num_z_pipes; 296 uint32_t r600_gb_backend_map; /* R600 harvest config */ 297 bool r600_gb_backend_map_valid; 298 uint32_t r600_num_banks; 299 uint32_t mc_arb_ramcfg; 300 uint32_t gb_addr_config; 301 uint32_t pa_sc_tile_steering_override; /* CLEAR_STATE also sets this */ 302 uint32_t max_render_backends; /* number of render backends incl. disabled ones */ 303 uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */ 304 uint32_t pipe_interleave_bytes; 305 uint64_t enabled_rb_mask; /* bitmask of enabled physical RBs, up to max_render_backends bits */ 306 uint64_t max_alignment; /* from addrlib */ 307 uint32_t pbb_max_alloc_count; 308 309 /* Tile modes. */ 310 uint32_t si_tile_mode_array[32]; 311 uint32_t cik_macrotile_mode_array[16]; 312 313 /* AMD_CU_MASK environment variable or ~0. */ 314 bool spi_cu_en_has_effect; 315 uint32_t spi_cu_en; 316 317 struct { 318 uint32_t shadow_size; 319 uint32_t shadow_alignment; 320 uint32_t csa_size; 321 uint32_t csa_alignment; 322 } fw_based_mcbp; 323 bool has_fw_based_shadowing; 324 325 /* Device supports hardware-accelerated raytracing using 326 * image_bvh*_intersect_ray instructions 327 */ 328 bool has_image_bvh_intersect_ray; 329 }; 330 331 bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, 332 bool require_pci_bus_info); 333 334 void ac_compute_driver_uuid(char *uuid, size_t size); 335 336 void ac_compute_device_uuid(const struct radeon_info *info, char *uuid, size_t size); 337 void ac_print_gpu_info(const struct radeon_info *info, FILE *f); 338 int ac_get_gs_table_depth(enum amd_gfx_level gfx_level, enum radeon_family family); 339 void ac_get_raster_config(const struct radeon_info *info, uint32_t *raster_config_p, 340 uint32_t *raster_config_1_p, uint32_t *se_tile_repeat_p); 341 void ac_get_harvested_configs(const struct radeon_info *info, unsigned raster_config, 342 unsigned *cik_raster_config_1_p, unsigned *raster_config_se); 343 unsigned ac_get_compute_resource_limits(const struct radeon_info *info, 344 unsigned waves_per_threadgroup, unsigned max_waves_per_sh, 345 unsigned threadgroups_per_cu); 346 347 struct ac_hs_info { 348 uint32_t tess_offchip_block_dw_size; 349 uint32_t max_offchip_buffers; 350 uint32_t hs_offchip_param; 351 uint32_t tess_factor_ring_size; 352 uint32_t tess_offchip_ring_offset; 353 uint32_t tess_offchip_ring_size; 354 }; 355 356 void ac_get_hs_info(const struct radeon_info *info, 357 struct ac_hs_info *hs); 358 359 /* Task rings BO layout information. 360 * This BO is shared between GFX and ACE queues so that the ACE and GFX 361 * firmware can cooperate on task->mesh dispatches and is also used to 362 * store the task payload which is passed to mesh shaders. 363 * 364 * The driver only needs to create this BO once, 365 * and it will always be able to accommodate the maximum needed 366 * task payload size. 367 * 368 * The following memory layout is used: 369 * 1. Control buffer: 9 DWORDs, 256 byte aligned 370 * Used by the firmware to maintain the current state. 371 * (padding) 372 * 2. Draw ring: 4 DWORDs per entry, 256 byte aligned 373 * Task shaders store the mesh dispatch size here. 374 * (padding) 375 * 3. Payload ring: 16K bytes per entry, 256 byte aligned. 376 * This is where task payload is stored by task shaders and 377 * read by mesh shaders. 378 * 379 */ 380 struct ac_task_info { 381 uint32_t draw_ring_offset; 382 uint32_t payload_ring_offset; 383 uint32_t bo_size_bytes; 384 uint16_t num_entries; 385 }; 386 387 /* Size of each payload entry in the task payload ring. 388 * Spec requires minimum 16K bytes. 389 */ 390 #define AC_TASK_PAYLOAD_ENTRY_BYTES 16384 391 392 /* Size of each draw entry in the task draw ring. 393 * 4 DWORDs per entry. 394 */ 395 #define AC_TASK_DRAW_ENTRY_BYTES 16 396 397 /* Size of the task control buffer. 9 DWORDs. */ 398 #define AC_TASK_CTRLBUF_BYTES 36 399 400 void ac_get_task_info(const struct radeon_info *info, 401 struct ac_task_info *task_info); 402 403 uint32_t ac_memory_ops_per_clock(uint32_t vram_type); 404 405 uint32_t ac_gfx103_get_cu_mask_ps(const struct radeon_info *info); 406 407 #ifdef __cplusplus 408 } 409 #endif 410 411 #endif /* AC_GPU_INFO_H */ 412